arch/arm/boot/dts/sun8i-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "sun8i-a23-a33.dtsi"
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 / {
  49         cpu0_opp_table: opp_table0 {
  50                 compatible = "operating-points-v2";
  51                 opp-shared;
  52
  53                 opp-120000000 {
  54                         opp-hz = /bits/ 64 <120000000>;
  55                         opp-microvolt = <1040000>;
  56                         clock-latency-ns = <244144>; /* 8 32k periods */
  57                 };
  58
  59                 opp-240000000 {
  60                         opp-hz = /bits/ 64 <240000000>;
  61                         opp-microvolt = <1040000>;
  62                         clock-latency-ns = <244144>; /* 8 32k periods */
  63                 };
  64
  65                 opp-312000000 {
  66                         opp-hz = /bits/ 64 <312000000>;
  67                         opp-microvolt = <1040000>;
  68                         clock-latency-ns = <244144>; /* 8 32k periods */
  69                 };
  70
  71                 opp-408000000 {
  72                         opp-hz = /bits/ 64 <408000000>;
  73                         opp-microvolt = <1040000>;
  74                         clock-latency-ns = <244144>; /* 8 32k periods */
  75                 };
  76
  77                 opp-480000000 {
  78                         opp-hz = /bits/ 64 <480000000>;
  79                         opp-microvolt = <1040000>;
  80                         clock-latency-ns = <244144>; /* 8 32k periods */
  81                 };
  82
  83                 opp-504000000 {
  84                         opp-hz = /bits/ 64 <504000000>;
  85                         opp-microvolt = <1040000>;
  86                         clock-latency-ns = <244144>; /* 8 32k periods */
  87                 };
  88
  89                 opp-600000000 {
  90                         opp-hz = /bits/ 64 <600000000>;
  91                         opp-microvolt = <1040000>;
  92                         clock-latency-ns = <244144>; /* 8 32k periods */
  93                 };
  94
  95                 opp-648000000 {
  96                         opp-hz = /bits/ 64 <648000000>;
  97                         opp-microvolt = <1040000>;
  98                         clock-latency-ns = <244144>; /* 8 32k periods */
  99                 };
 100
 101                 opp-720000000 {
 102                         opp-hz = /bits/ 64 <720000000>;
 103                         opp-microvolt = <1100000>;
 104                         clock-latency-ns = <244144>; /* 8 32k periods */
 105                 };
 106
 107                 opp-816000000 {
 108                         opp-hz = /bits/ 64 <816000000>;
 109                         opp-microvolt = <1100000>;
 110                         clock-latency-ns = <244144>; /* 8 32k periods */
 111                 };
 112
 113                 opp-912000000 {
 114                         opp-hz = /bits/ 64 <912000000>;
 115                         opp-microvolt = <1200000>;
 116                         clock-latency-ns = <244144>; /* 8 32k periods */
 117                 };
 118
 119                 opp-1008000000 {
 120                         opp-hz = /bits/ 64 <1008000000>;
 121                         opp-microvolt = <1200000>;
 122                         clock-latency-ns = <244144>; /* 8 32k periods */
 123                 };
 124         };
 125
 126         cpus {
 127                 cpu@0 {
 128                         clocks = <&ccu CLK_CPUX>;
 129                         clock-names = "cpu";
 130                         operating-points-v2 = <&cpu0_opp_table>;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu@1 {
 135                         clocks = <&ccu CLK_CPUX>;
 136                         clock-names = "cpu";
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         #cooling-cells = <2>;
 139                 };
 140
 141                 cpu@2 {
 142                         compatible = "arm,cortex-a7";
 143                         device_type = "cpu";
 144                         reg = <2>;
 145                         clocks = <&ccu CLK_CPUX>;
 146                         clock-names = "cpu";
 147                         operating-points-v2 = <&cpu0_opp_table>;
 148                         #cooling-cells = <2>;
 149                 };
 150
 151                 cpu@3 {
 152                         compatible = "arm,cortex-a7";
 153                         device_type = "cpu";
 154                         reg = <3>;
 155                         clocks = <&ccu CLK_CPUX>;
 156                         clock-names = "cpu";
 157                         operating-points-v2 = <&cpu0_opp_table>;
 158                         #cooling-cells = <2>;
 159                 };
 160         };
 161
 162         de: display-engine {
 163                 compatible = "allwinner,sun8i-a33-display-engine";
 164                 allwinner,pipelines = <&fe0>;
 165                 status = "disabled";
 166         };
 167
 168         iio-hwmon {
 169                 compatible = "iio-hwmon";
 170                 io-channels = <&ths>;
 171         };
 172
 173         mali_opp_table: gpu-opp-table {
 174                 compatible = "operating-points-v2";
 175
 176                 opp-144000000 {
 177                         opp-hz = /bits/ 64 <144000000>;
 178                 };
 179
 180                 opp-240000000 {
 181                         opp-hz = /bits/ 64 <240000000>;
 182                 };
 183
 184                 opp-384000000 {
 185                         opp-hz = /bits/ 64 <384000000>;
 186                 };
 187         };
 188
 189         memory {
 190                 reg = <0x40000000 0x80000000>;
 191         };
 192
 193         reserved-memory {
 194                 #address-cells = <1>;
 195                 #size-cells = <1>;
 196                 ranges;
 197
 198                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 199                 cma_pool: cma@4a000000 {
 200                         compatible = "shared-dma-pool";
 201                         size = <0x6000000>;
 202                         alloc-ranges = <0x4a000000 0x6000000>;
 203                         reusable;
 204                         linux,cma-default;
 205                 };
 206         };
 207
 208         sound: sound {
 209                 compatible = "simple-audio-card";
 210                 simple-audio-card,name = "sun8i-a33-audio";
 211                 simple-audio-card,format = "i2s";
 212                 simple-audio-card,frame-master = <&link_codec>;
 213                 simple-audio-card,bitclock-master = <&link_codec>;
 214                 simple-audio-card,mclk-fs = <512>;
 215                 simple-audio-card,aux-devs = <&codec_analog>;
 216                 simple-audio-card,routing =
 217                         "Left DAC", "AIF1 Slot 0 Left",
 218                         "Right DAC", "AIF1 Slot 0 Right";
 219                 status = "disabled";
 220
 221                 simple-audio-card,cpu {
 222                         sound-dai = <&dai>;
 223                 };
 224
 225                 link_codec: simple-audio-card,codec {
 226                         sound-dai = <&codec>;
 227                 };
 228         };
 229
 230         soc@1c00000 {
 231                 tcon0: lcd-controller@1c0c000 {
 232                         compatible = "allwinner,sun8i-a33-tcon";
 233                         reg = <0x01c0c000 0x1000>;
 234                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 235                         clocks = <&ccu CLK_BUS_LCD>,
 236                                  <&ccu CLK_LCD_CH0>;
 237                         clock-names = "ahb",
 238                                       "tcon-ch0";
 239                         clock-output-names = "tcon-pixel-clock";
 240                         resets = <&ccu RST_BUS_LCD>;
 241                         reset-names = "lcd";
 242                         status = "disabled";
 243
 244                         ports {
 245                                 #address-cells = <1>;
 246                                 #size-cells = <0>;
 247
 248                                 tcon0_in: port@0 {
 249                                         #address-cells = <1>;
 250                                         #size-cells = <0>;
 251                                         reg = <0>;
 252
 253                                         tcon0_in_drc0: endpoint@0 {
 254                                                 reg = <0>;
 255                                                 remote-endpoint = <&drc0_out_tcon0>;
 256                                         };
 257                                 };
 258
 259                                 tcon0_out: port@1 {
 260                                         #address-cells = <1>;
 261                                         #size-cells = <0>;
 262                                         reg = <1>;
 263
 264                                         tcon0_out_dsi: endpoint@1 {
 265                                                 reg = <1>;
 266                                                 remote-endpoint = <&dsi_in_tcon0>;
 267                                         };
 268                                 };
 269                         };
 270                 };
 271
 272                 video-codec@01c0e000 {
 273                         compatible = "allwinner,sun8i-a33-video-engine";
 274                         reg = <0x01c0e000 0x1000>;
 275                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 276                                  <&ccu CLK_DRAM_VE>;
 277                         clock-names = "ahb", "mod", "ram";
 278                         resets = <&ccu RST_BUS_VE>;
 279                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 280                         allwinner,sram = <&ve_sram 1>;
 281                 };
 282
 283                 crypto: crypto-engine@1c15000 {
 284                         compatible = "allwinner,sun4i-a10-crypto";
 285                         reg = <0x01c15000 0x1000>;
 286                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
 288                         clock-names = "ahb", "mod";
 289                         resets = <&ccu RST_BUS_SS>;
 290                         reset-names = "ahb";
 291                 };
 292
 293                 dai: dai@1c22c00 {
 294                         #sound-dai-cells = <0>;
 295                         compatible = "allwinner,sun6i-a31-i2s";
 296                         reg = <0x01c22c00 0x200>;
 297                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 298                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 299                         clock-names = "apb", "mod";
 300                         resets = <&ccu RST_BUS_CODEC>;
 301                         dmas = <&dma 15>, <&dma 15>;
 302                         dma-names = "rx", "tx";
 303                         status = "disabled";
 304                 };
 305
 306                 codec: codec@1c22e00 {
 307                         #sound-dai-cells = <0>;
 308                         compatible = "allwinner,sun8i-a33-codec";
 309                         reg = <0x01c22e00 0x400>;
 310                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 312                         clock-names = "bus", "mod";
 313                         status = "disabled";
 314                 };
 315
 316                 ths: ths@1c25000 {
 317                         compatible = "allwinner,sun8i-a33-ths";
 318                         reg = <0x01c25000 0x100>;
 319                         #thermal-sensor-cells = <0>;
 320                         #io-channel-cells = <0>;
 321                 };
 322
 323                 dsi: dsi@1ca0000 {
 324                         compatible = "allwinner,sun6i-a31-mipi-dsi";
 325                         reg = <0x01ca0000 0x1000>;
 326                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 328                                  <&ccu CLK_DSI_SCLK>;
 329                         clock-names = "bus", "mod";
 330                         resets = <&ccu RST_BUS_MIPI_DSI>;
 331                         phys = <&dphy>;
 332                         phy-names = "dphy";
 333                         status = "disabled";
 334
 335                         ports {
 336                                 #address-cells = <1>;
 337                                 #size-cells = <0>;
 338
 339                                 port@0 {
 340                                         #address-cells = <1>;
 341                                         #size-cells = <0>;
 342                                         reg = <0>;
 343
 344                                         dsi_in_tcon0: endpoint {
 345                                                 remote-endpoint = <&tcon0_out_dsi>;
 346                                         };
 347                                 };
 348                         };
 349                 };
 350
 351                 dphy: d-phy@1ca1000 {
 352                         compatible = "allwinner,sun6i-a31-mipi-dphy";
 353                         reg = <0x01ca1000 0x1000>;
 354                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 355                                  <&ccu CLK_DSI_DPHY>;
 356                         clock-names = "bus", "mod";
 357                         resets = <&ccu RST_BUS_MIPI_DSI>;
 358                         status = "disabled";
 359                         #phy-cells = <0>;
 360                 };
 361
 362                 fe0: display-frontend@1e00000 {
 363                         compatible = "allwinner,sun8i-a33-display-frontend";
 364                         reg = <0x01e00000 0x20000>;
 365                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
 367                                  <&ccu CLK_DRAM_DE_FE>;
 368                         clock-names = "ahb", "mod",
 369                                       "ram";
 370                         resets = <&ccu RST_BUS_DE_FE>;
 371
 372                         ports {
 373                                 #address-cells = <1>;
 374                                 #size-cells = <0>;
 375
 376                                 fe0_out: port@1 {
 377                                         #address-cells = <1>;
 378                                         #size-cells = <0>;
 379                                         reg = <1>;
 380
 381                                         fe0_out_be0: endpoint@0 {
 382                                                 reg = <0>;
 383                                                 remote-endpoint = <&be0_in_fe0>;
 384                                         };
 385                                 };
 386                         };
 387                 };
 388
 389                 be0: display-backend@1e60000 {
 390                         compatible = "allwinner,sun8i-a33-display-backend";
 391                         reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
 392                         reg-names = "be", "sat";
 393                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 395                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
 396                         clock-names = "ahb", "mod",
 397                                       "ram", "sat";
 398                         resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
 399                         reset-names = "be", "sat";
 400                         assigned-clocks = <&ccu CLK_DE_BE>;
 401                         assigned-clock-rates = <300000000>;
 402
 403                         ports {
 404                                 #address-cells = <1>;
 405                                 #size-cells = <0>;
 406
 407                                 be0_in: port@0 {
 408                                         #address-cells = <1>;
 409                                         #size-cells = <0>;
 410                                         reg = <0>;
 411
 412                                         be0_in_fe0: endpoint@0 {
 413                                                 reg = <0>;
 414                                                 remote-endpoint = <&fe0_out_be0>;
 415                                         };
 416                                 };
 417
 418                                 be0_out: port@1 {
 419                                         #address-cells = <1>;
 420                                         #size-cells = <0>;
 421                                         reg = <1>;
 422
 423                                         be0_out_drc0: endpoint@0 {
 424                                                 reg = <0>;
 425                                                 remote-endpoint = <&drc0_in_be0>;
 426                                         };
 427                                 };
 428                         };
 429                 };
 430
 431                 drc0: drc@1e70000 {
 432                         compatible = "allwinner,sun8i-a33-drc";
 433                         reg = <0x01e70000 0x10000>;
 434                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
 436                                  <&ccu CLK_DRAM_DRC>;
 437                         clock-names = "ahb", "mod", "ram";
 438                         resets = <&ccu RST_BUS_DRC>;
 439
 440                         assigned-clocks = <&ccu CLK_DRC>;
 441                         assigned-clock-rates = <300000000>;
 442
 443                         ports {
 444                                 #address-cells = <1>;
 445                                 #size-cells = <0>;
 446
 447                                 drc0_in: port@0 {
 448                                         #address-cells = <1>;
 449                                         #size-cells = <0>;
 450                                         reg = <0>;
 451
 452                                         drc0_in_be0: endpoint@0 {
 453                                                 reg = <0>;
 454                                                 remote-endpoint = <&be0_out_drc0>;
 455                                         };
 456                                 };
 457
 458                                 drc0_out: port@1 {
 459                                         #address-cells = <1>;
 460                                         #size-cells = <0>;
 461                                         reg = <1>;
 462
 463                                         drc0_out_tcon0: endpoint@0 {
 464                                                 reg = <0>;
 465                                                 remote-endpoint = <&tcon0_in_drc0>;
 466                                         };
 467                                 };
 468                         };
 469                 };
 470         };
 471
 472         thermal-zones {
 473                 cpu_thermal {
 474                         /* milliseconds */
 475                         polling-delay-passive = <250>;
 476                         polling-delay = <1000>;
 477                         thermal-sensors = <&ths>;
 478
 479                         cooling-maps {
 480                                 map0 {
 481                                         trip = <&cpu_alert0>;
 482                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 483                                 };
 484                                 map1 {
 485                                         trip = <&cpu_alert1>;
 486                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 487                                 };
 488
 489                                 map2 {
 490                                         trip = <&gpu_alert0>;
 491                                         cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
 492                                 };
 493
 494                                 map3 {
 495                                         trip = <&gpu_alert1>;
 496                                         cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
 497                                 };
 498                         };
 499
 500                         trips {
 501                                 cpu_alert0: cpu_alert0 {
 502                                         /* milliCelsius */
 503                                         temperature = <75000>;
 504                                         hysteresis = <2000>;
 505                                         type = "passive";
 506                                 };
 507
 508                                 gpu_alert0: gpu_alert0 {
 509                                         /* milliCelsius */
 510                                         temperature = <85000>;
 511                                         hysteresis = <2000>;
 512                                         type = "passive";
 513                                 };
 514
 515                                 cpu_alert1: cpu_alert1 {
 516                                         /* milliCelsius */
 517                                         temperature = <90000>;
 518                                         hysteresis = <2000>;
 519                                         type = "hot";
 520                                 };
 521
 522                                 gpu_alert1: gpu_alert1 {
 523                                         /* milliCelsius */
 524                                         temperature = <95000>;
 525                                         hysteresis = <2000>;
 526                                         type = "hot";
 527                                 };
 528
 529                                 cpu_crit: cpu_crit {
 530                                         /* milliCelsius */
 531                                         temperature = <110000>;
 532                                         hysteresis = <2000>;
 533                                         type = "critical";
 534                                 };
 535                         };
 536                 };
 537         };
 538 };
 539
 540 &ccu {
 541         compatible = "allwinner,sun8i-a33-ccu";
 542 };
 543
 544 &mali {
 545         operating-points-v2 = <&mali_opp_table>;
 546 };
 547
 548 &pio {
 549         compatible = "allwinner,sun8i-a33-pinctrl";
 550         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 551                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 552
 553         uart0_pins_b: uart0@1 {
 554                 pins = "PB0", "PB1";
 555                 function = "uart0";
 556         };
 557
 558 };
 559
 560 &usb_otg {
 561         compatible = "allwinner,sun8i-a33-musb";
 562 };
 563
 564 &usbphy {
 565         compatible = "allwinner,sun8i-a33-usb-phy";
 566         reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
 567         reg-names = "phy_ctrl", "pmu1";
 568 };