arch/arm/boot/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this library; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 /include/ "skeleton.dtsi"
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 serial0 = &uart0;
  57                 serial1 = &uart1;
  58                 serial2 = &uart2;
  59                 serial3 = &uart3;
  60                 serial4 = &uart4;
  61                 serial5 = &r_uart;
  62         };
  63
  64         cpus {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67
  68                 cpu@0 {
  69                         compatible = "arm,cortex-a7";
  70                         device_type = "cpu";
  71                         reg = <0>;
  72                 };
  73
  74                 cpu@1 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         reg = <1>;
  78                 };
  79         };
  80
  81         memory {
  82                 reg = <0x40000000 0x40000000>;
  83         };
  84
  85         clocks {
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges;
  89
  90                 osc24M: osc24M_clk {
  91                         #clock-cells = <0>;
  92                         compatible = "fixed-clock";
  93                         clock-frequency = <24000000>;
  94                         clock-output-names = "osc24M";
  95                 };
  96
  97                 osc32k: osc32k_clk {
  98                         #clock-cells = <0>;
  99                         compatible = "fixed-clock";
 100                         clock-frequency = <32768>;
 101                         clock-output-names = "osc32k";
 102                 };
 103
 104                 pll1: clk@01c20000 {
 105                         #clock-cells = <0>;
 106                         compatible = "allwinner,sun8i-a23-pll1-clk";
 107                         reg = <0x01c20000 0x4>;
 108                         clocks = <&osc24M>;
 109                         clock-output-names = "pll1";
 110                 };
 111
 112                 /* dummy clock until actually implemented */
 113                 pll6: pll6_clk {
 114                         #clock-cells = <0>;
 115                         compatible = "fixed-clock";
 116                         clock-frequency = <600000000>;
 117                         clock-output-names = "pll6";
 118                 };
 119
 120                 cpu: cpu_clk@01c20050 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-a10-cpu-clk";
 123                         reg = <0x01c20050 0x4>;
 124
 125                         /*
 126                          * PLL1 is listed twice here.
 127                          * While it looks suspicious, it's actually documented
 128                          * that way both in the datasheet and in the code from
 129                          * Allwinner.
 130                          */
 131                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 132                         clock-output-names = "cpu";
 133                 };
 134
 135                 axi: axi_clk@01c20050 {
 136                         #clock-cells = <0>;
 137                         compatible = "allwinner,sun8i-a23-axi-clk";
 138                         reg = <0x01c20050 0x4>;
 139                         clocks = <&cpu>;
 140                         clock-output-names = "axi";
 141                 };
 142
 143                 ahb1_mux: ahb1_mux_clk@01c20054 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 146                         reg = <0x01c20054 0x4>;
 147                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 148                         clock-output-names = "ahb1_mux";
 149                 };
 150
 151                 ahb1: ahb1_clk@01c20054 {
 152                         #clock-cells = <0>;
 153                         compatible = "allwinner,sun4i-a10-ahb-clk";
 154                         reg = <0x01c20054 0x4>;
 155                         clocks = <&ahb1_mux>;
 156                         clock-output-names = "ahb1";
 157                 };
 158
 159                 apb1: apb1_clk@01c20054 {
 160                         #clock-cells = <0>;
 161                         compatible = "allwinner,sun4i-a10-apb0-clk";
 162                         reg = <0x01c20054 0x4>;
 163                         clocks = <&ahb1>;
 164                         clock-output-names = "apb1";
 165                 };
 166
 167                 ahb1_gates: clk@01c20060 {
 168                         #clock-cells = <1>;
 169                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 170                         reg = <0x01c20060 0x8>;
 171                         clocks = <&ahb1>;
 172                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 173                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 174                                         "ahb1_nand", "ahb1_sdram",
 175                                         "ahb1_hstimer", "ahb1_spi0",
 176                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
 177                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
 178                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
 179                                         "ahb1_gpu", "ahb1_spinlock",
 180                                         "ahb1_drc";
 181                 };
 182
 183                 apb1_gates: clk@01c20068 {
 184                         #clock-cells = <1>;
 185                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 186                         reg = <0x01c20068 0x4>;
 187                         clocks = <&apb1>;
 188                         clock-output-names = "apb1_codec", "apb1_pio",
 189                                         "apb1_daudio0", "apb1_daudio1";
 190                 };
 191
 192                 apb2_mux: apb2_mux_clk@01c20058 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 195                         reg = <0x01c20058 0x4>;
 196                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 197                         clock-output-names = "apb2_mux";
 198                 };
 199
 200                 apb2: apb2_clk@01c20058 {
 201                         #clock-cells = <0>;
 202                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 203                         reg = <0x01c20058 0x4>;
 204                         clocks = <&apb2_mux>;
 205                         clock-output-names = "apb2";
 206                 };
 207
 208                 apb2_gates: clk@01c2006c {
 209                         #clock-cells = <1>;
 210                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 211                         reg = <0x01c2006c 0x4>;
 212                         clocks = <&apb2>;
 213                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 214                                         "apb2_i2c2", "apb2_uart0",
 215                                         "apb2_uart1", "apb2_uart2",
 216                                         "apb2_uart3", "apb2_uart4";
 217                 };
 218
 219                 mmc0_clk: clk@01c20088 {
 220                         #clock-cells = <0>;
 221                         compatible = "allwinner,sun4i-a10-mod0-clk";
 222                         reg = <0x01c20088 0x4>;
 223                         clocks = <&osc24M>, <&pll6>;
 224                         clock-output-names = "mmc0";
 225                 };
 226
 227                 mmc1_clk: clk@01c2008c {
 228                         #clock-cells = <0>;
 229                         compatible = "allwinner,sun4i-a10-mod0-clk";
 230                         reg = <0x01c2008c 0x4>;
 231                         clocks = <&osc24M>, <&pll6>;
 232                         clock-output-names = "mmc1";
 233                 };
 234
 235                 mmc2_clk: clk@01c20090 {
 236                         #clock-cells = <0>;
 237                         compatible = "allwinner,sun4i-a10-mod0-clk";
 238                         reg = <0x01c20090 0x4>;
 239                         clocks = <&osc24M>, <&pll6>;
 240                         clock-output-names = "mmc2";
 241                 };
 242         };
 243
 244         soc@01c00000 {
 245                 compatible = "simple-bus";
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 ranges;
 249
 250                 dma: dma-controller@01c02000 {
 251                         compatible = "allwinner,sun8i-a23-dma";
 252                         reg = <0x01c02000 0x1000>;
 253                         interrupts = <0 50 4>;
 254                         clocks = <&ahb1_gates 6>;
 255                         resets = <&ahb1_rst 6>;
 256                         #dma-cells = <1>;
 257                 };
 258
 259                 mmc0: mmc@01c0f000 {
 260                         compatible = "allwinner,sun5i-a13-mmc";
 261                         reg = <0x01c0f000 0x1000>;
 262                         clocks = <&ahb1_gates 8>, <&mmc0_clk>;
 263                         clock-names = "ahb", "mmc";
 264                         resets = <&ahb1_rst 8>;
 265                         reset-names = "ahb";
 266                         interrupts = <0 60 4>;
 267                         status = "disabled";
 268                 };
 269
 270                 mmc1: mmc@01c10000 {
 271                         compatible = "allwinner,sun5i-a13-mmc";
 272                         reg = <0x01c10000 0x1000>;
 273                         clocks = <&ahb1_gates 9>, <&mmc1_clk>;
 274                         clock-names = "ahb", "mmc";
 275                         resets = <&ahb1_rst 9>;
 276                         reset-names = "ahb";
 277                         interrupts = <0 61 4>;
 278                         status = "disabled";
 279                 };
 280
 281                 mmc2: mmc@01c11000 {
 282                         compatible = "allwinner,sun5i-a13-mmc";
 283                         reg = <0x01c11000 0x1000>;
 284                         clocks = <&ahb1_gates 10>, <&mmc2_clk>;
 285                         clock-names = "ahb", "mmc";
 286                         resets = <&ahb1_rst 10>;
 287                         reset-names = "ahb";
 288                         interrupts = <0 62 4>;
 289                         status = "disabled";
 290                 };
 291
 292                 pio: pinctrl@01c20800 {
 293                         compatible = "allwinner,sun8i-a23-pinctrl";
 294                         reg = <0x01c20800 0x400>;
 295                         interrupts = <0 11 4>,
 296                                      <0 15 4>,
 297                                      <0 17 4>;
 298                         clocks = <&apb1_gates 5>;
 299                         gpio-controller;
 300                         interrupt-controller;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         #gpio-cells = <3>;
 304
 305                         uart0_pins_a: uart0@0 {
 306                                 allwinner,pins = "PF2", "PF4";
 307                                 allwinner,function = "uart0";
 308                                 allwinner,drive = <0>;
 309                                 allwinner,pull = <0>;
 310                         };
 311
 312                         mmc0_pins_a: mmc0@0 {
 313                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 314                                 allwinner,function = "mmc0";
 315                                 allwinner,drive = <2>;
 316                                 allwinner,pull = <0>;
 317                         };
 318
 319                         mmc1_pins_a: mmc1@0 {
 320                                 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
 321                                 allwinner,function = "mmc1";
 322                                 allwinner,drive = <2>;
 323                                 allwinner,pull = <0>;
 324                         };
 325
 326                         i2c0_pins_a: i2c0@0 {
 327                                 allwinner,pins = "PH2", "PH3";
 328                                 allwinner,function = "i2c0";
 329                                 allwinner,drive = <0>;
 330                                 allwinner,pull = <0>;
 331                         };
 332
 333                         i2c1_pins_a: i2c1@0 {
 334                                 allwinner,pins = "PH4", "PH5";
 335                                 allwinner,function = "i2c1";
 336                                 allwinner,drive = <0>;
 337                                 allwinner,pull = <0>;
 338                         };
 339
 340                         i2c2_pins_a: i2c2@0 {
 341                                 allwinner,pins = "PE12", "PE13";
 342                                 allwinner,function = "i2c2";
 343                                 allwinner,drive = <0>;
 344                                 allwinner,pull = <0>;
 345                         };
 346                 };
 347
 348                 ahb1_rst: reset@01c202c0 {
 349                         #reset-cells = <1>;
 350                         compatible = "allwinner,sun6i-a31-clock-reset";
 351                         reg = <0x01c202c0 0xc>;
 352                 };
 353
 354                 apb1_rst: reset@01c202d0 {
 355                         #reset-cells = <1>;
 356                         compatible = "allwinner,sun6i-a31-clock-reset";
 357                         reg = <0x01c202d0 0x4>;
 358                 };
 359
 360                 apb2_rst: reset@01c202d8 {
 361                         #reset-cells = <1>;
 362                         compatible = "allwinner,sun6i-a31-clock-reset";
 363                         reg = <0x01c202d8 0x4>;
 364                 };
 365
 366                 timer@01c20c00 {
 367                         compatible = "allwinner,sun4i-a10-timer";
 368                         reg = <0x01c20c00 0xa0>;
 369                         interrupts = <0 18 4>,
 370                                      <0 19 4>;
 371                         clocks = <&osc24M>;
 372                 };
 373
 374                 wdt0: watchdog@01c20ca0 {
 375                         compatible = "allwinner,sun6i-a31-wdt";
 376                         reg = <0x01c20ca0 0x20>;
 377                         interrupts = <0 25 4>;
 378                 };
 379
 380                 uart0: serial@01c28000 {
 381                         compatible = "snps,dw-apb-uart";
 382                         reg = <0x01c28000 0x400>;
 383                         interrupts = <0 0 4>;
 384                         reg-shift = <2>;
 385                         reg-io-width = <4>;
 386                         clocks = <&apb2_gates 16>;
 387                         resets = <&apb2_rst 16>;
 388                         dmas = <&dma 6>, <&dma 6>;
 389                         dma-names = "rx", "tx";
 390                         status = "disabled";
 391                 };
 392
 393                 uart1: serial@01c28400 {
 394                         compatible = "snps,dw-apb-uart";
 395                         reg = <0x01c28400 0x400>;
 396                         interrupts = <0 1 4>;
 397                         reg-shift = <2>;
 398                         reg-io-width = <4>;
 399                         clocks = <&apb2_gates 17>;
 400                         resets = <&apb2_rst 17>;
 401                         dmas = <&dma 7>, <&dma 7>;
 402                         dma-names = "rx", "tx";
 403                         status = "disabled";
 404                 };
 405
 406                 uart2: serial@01c28800 {
 407                         compatible = "snps,dw-apb-uart";
 408                         reg = <0x01c28800 0x400>;
 409                         interrupts = <0 2 4>;
 410                         reg-shift = <2>;
 411                         reg-io-width = <4>;
 412                         clocks = <&apb2_gates 18>;
 413                         resets = <&apb2_rst 18>;
 414                         dmas = <&dma 8>, <&dma 8>;
 415                         dma-names = "rx", "tx";
 416                         status = "disabled";
 417                 };
 418
 419                 uart3: serial@01c28c00 {
 420                         compatible = "snps,dw-apb-uart";
 421                         reg = <0x01c28c00 0x400>;
 422                         interrupts = <0 3 4>;
 423                         reg-shift = <2>;
 424                         reg-io-width = <4>;
 425                         clocks = <&apb2_gates 19>;
 426                         resets = <&apb2_rst 19>;
 427                         dmas = <&dma 9>, <&dma 9>;
 428                         dma-names = "rx", "tx";
 429                         status = "disabled";
 430                 };
 431
 432                 uart4: serial@01c29000 {
 433                         compatible = "snps,dw-apb-uart";
 434                         reg = <0x01c29000 0x400>;
 435                         interrupts = <0 4 4>;
 436                         reg-shift = <2>;
 437                         reg-io-width = <4>;
 438                         clocks = <&apb2_gates 20>;
 439                         resets = <&apb2_rst 20>;
 440                         dmas = <&dma 10>, <&dma 10>;
 441                         dma-names = "rx", "tx";
 442                         status = "disabled";
 443                 };
 444
 445                 i2c0: i2c@01c2ac00 {
 446                         compatible = "allwinner,sun6i-a31-i2c";
 447                         reg = <0x01c2ac00 0x400>;
 448                         interrupts = <0 6 4>;
 449                         clocks = <&apb2_gates 0>;
 450                         resets = <&apb2_rst 0>;
 451                         status = "disabled";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                 };
 455
 456                 i2c1: i2c@01c2b000 {
 457                         compatible = "allwinner,sun6i-a31-i2c";
 458                         reg = <0x01c2b000 0x400>;
 459                         interrupts = <0 7 4>;
 460                         clocks = <&apb2_gates 1>;
 461                         resets = <&apb2_rst 1>;
 462                         status = "disabled";
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                 };
 466
 467                 i2c2: i2c@01c2b400 {
 468                         compatible = "allwinner,sun6i-a31-i2c";
 469                         reg = <0x01c2b400 0x400>;
 470                         interrupts = <0 8 4>;
 471                         clocks = <&apb2_gates 2>;
 472                         resets = <&apb2_rst 2>;
 473                         status = "disabled";
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                 };
 477
 478                 gic: interrupt-controller@01c81000 {
 479                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 480                         reg = <0x01c81000 0x1000>,
 481                               <0x01c82000 0x1000>,
 482                               <0x01c84000 0x2000>,
 483                               <0x01c86000 0x2000>;
 484                         interrupt-controller;
 485                         #interrupt-cells = <3>;
 486                         interrupts = <1 9 0xf04>;
 487                 };
 488
 489                 rtc: rtc@01f00000 {
 490                         compatible = "allwinner,sun6i-a31-rtc";
 491                         reg = <0x01f00000 0x54>;
 492                         interrupts = <0 40 4>, <0 41 4>;
 493                 };
 494
 495                 prcm@01f01400 {
 496                         compatible = "allwinner,sun8i-a23-prcm";
 497                         reg = <0x01f01400 0x200>;
 498
 499                         ar100: ar100_clk {
 500                                 compatible = "fixed-factor-clock";
 501                                 #clock-cells = <0>;
 502                                 clock-div = <1>;
 503                                 clock-mult = <1>;
 504                                 clocks = <&osc24M>;
 505                                 clock-output-names = "ar100";
 506                         };
 507
 508                         ahb0: ahb0_clk {
 509                                 compatible = "fixed-factor-clock";
 510                                 #clock-cells = <0>;
 511                                 clock-div = <1>;
 512                                 clock-mult = <1>;
 513                                 clocks = <&ar100>;
 514                                 clock-output-names = "ahb0";
 515                         };
 516
 517                         apb0: apb0_clk {
 518                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 519                                 #clock-cells = <0>;
 520                                 clocks = <&ahb0>;
 521                                 clock-output-names = "apb0";
 522                         };
 523
 524                         apb0_gates: apb0_gates_clk {
 525                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 526                                 #clock-cells = <1>;
 527                                 clocks = <&apb0>;
 528                                 clock-output-names = "apb0_pio", "apb0_timer",
 529                                                 "apb0_rsb", "apb0_uart",
 530                                                 "apb0_i2c";
 531                         };
 532
 533                         apb0_rst: apb0_rst {
 534                                 compatible = "allwinner,sun6i-a31-clock-reset";
 535                                 #reset-cells = <1>;
 536                         };
 537                 };
 538
 539                 r_uart: serial@01f02800 {
 540                         compatible = "snps,dw-apb-uart";
 541                         reg = <0x01f02800 0x400>;
 542                         interrupts = <0 38 4>;
 543                         reg-shift = <2>;
 544                         reg-io-width = <4>;
 545                         clocks = <&apb0_gates 4>;
 546                         resets = <&apb0_rst 4>;
 547                         status = "disabled";
 548                 };
 549
 550                 r_pio: pinctrl@01f02c00 {
 551                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 552                         reg = <0x01f02c00 0x400>;
 553                         interrupts = <0 45 4>;
 554                         clocks = <&apb0_gates 0>;
 555                         resets = <&apb0_rst 0>;
 556                         gpio-controller;
 557                         interrupt-controller;
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         #gpio-cells = <3>;
 561
 562                         r_uart_pins_a: r_uart@0 {
 563                                 allwinner,pins = "PL2", "PL3";
 564                                 allwinner,function = "s_uart";
 565                                 allwinner,drive = <0>;
 566                                 allwinner,pull = <0>;
 567                         };
 568                 };
 569         };
 570 };