arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 simplefb_lcd: framebuffer@0 {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "de_be0-lcd0";
  64                         clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
  65                                  <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
  66                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
  67                         status = "disabled";
  68                 };
  69         };
  70
  71         timer {
  72                 compatible = "arm,armv7-timer";
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  77                 clock-frequency = <24000000>;
  78                 arm,cpu-registers-not-fw-configured;
  79         };
  80
  81         cpus {
  82                 enable-method = "allwinner,sun8i-a23";
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85
  86                 cpu0: cpu@0 {
  87                         compatible = "arm,cortex-a7";
  88                         device_type = "cpu";
  89                         reg = <0>;
  90                 };
  91
  92                 cpu@1 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         reg = <1>;
  96                 };
  97         };
  98
  99         clocks {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 osc24M: osc24M_clk {
 105                         #clock-cells = <0>;
 106                         compatible = "fixed-clock";
 107                         clock-frequency = <24000000>;
 108                         clock-accuracy = <50000>;
 109                         clock-output-names = "osc24M";
 110                 };
 111
 112                 ext_osc32k: ext_osc32k_clk {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-clock";
 115                         clock-frequency = <32768>;
 116                         clock-accuracy = <50000>;
 117                         clock-output-names = "ext-osc32k";
 118                 };
 119         };
 120
 121         soc@1c00000 {
 122                 compatible = "simple-bus";
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 ranges;
 126
 127                 system-control@1c00000 {
 128                         compatible = "allwinner,sun8i-a23-system-control";
 129                         reg = <0x01c00000 0x30>;
 130                         #address-cells = <1>;
 131                         #size-cells = <1>;
 132                         ranges;
 133
 134                         sram_c: sram@1d00000 {
 135                                 compatible = "mmio-sram";
 136                                 reg = <0x01d00000 0x80000>;
 137                                 #address-cells = <1>;
 138                                 #size-cells = <1>;
 139                                 ranges = <0 0x01d00000 0x80000>;
 140
 141                                 ve_sram: sram-section@0 {
 142                                         compatible = "allwinner,sun8i-a23-sram-c1",
 143                                                      "allwinner,sun4i-a10-sram-c1";
 144                                         reg = <0x000000 0x80000>;
 145                                 };
 146                         };
 147                 };
 148
 149                 dma: dma-controller@1c02000 {
 150                         compatible = "allwinner,sun8i-a23-dma";
 151                         reg = <0x01c02000 0x1000>;
 152                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 153                         clocks = <&ccu CLK_BUS_DMA>;
 154                         resets = <&ccu RST_BUS_DMA>;
 155                         #dma-cells = <1>;
 156                 };
 157
 158                 mmc0: mmc@1c0f000 {
 159                         compatible = "allwinner,sun7i-a20-mmc";
 160                         reg = <0x01c0f000 0x1000>;
 161                         clocks = <&ccu CLK_BUS_MMC0>,
 162                                  <&ccu CLK_MMC0>,
 163                                  <&ccu CLK_MMC0_OUTPUT>,
 164                                  <&ccu CLK_MMC0_SAMPLE>;
 165                         clock-names = "ahb",
 166                                       "mmc",
 167                                       "output",
 168                                       "sample";
 169                         resets = <&ccu RST_BUS_MMC0>;
 170                         reset-names = "ahb";
 171                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 172                         status = "disabled";
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                 };
 176
 177                 mmc1: mmc@1c10000 {
 178                         compatible = "allwinner,sun7i-a20-mmc";
 179                         reg = <0x01c10000 0x1000>;
 180                         clocks = <&ccu CLK_BUS_MMC1>,
 181                                  <&ccu CLK_MMC1>,
 182                                  <&ccu CLK_MMC1_OUTPUT>,
 183                                  <&ccu CLK_MMC1_SAMPLE>;
 184                         clock-names = "ahb",
 185                                       "mmc",
 186                                       "output",
 187                                       "sample";
 188                         resets = <&ccu RST_BUS_MMC1>;
 189                         reset-names = "ahb";
 190                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 191                         status = "disabled";
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                 };
 195
 196                 mmc2: mmc@1c11000 {
 197                         compatible = "allwinner,sun7i-a20-mmc";
 198                         reg = <0x01c11000 0x1000>;
 199                         clocks = <&ccu CLK_BUS_MMC2>,
 200                                  <&ccu CLK_MMC2>,
 201                                  <&ccu CLK_MMC2_OUTPUT>,
 202                                  <&ccu CLK_MMC2_SAMPLE>;
 203                         clock-names = "ahb",
 204                                       "mmc",
 205                                       "output",
 206                                       "sample";
 207                         resets = <&ccu RST_BUS_MMC2>;
 208                         reset-names = "ahb";
 209                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 210                         status = "disabled";
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                 };
 214
 215                 nfc: nand@1c03000 {
 216                         compatible = "allwinner,sun4i-a10-nand";
 217                         reg = <0x01c03000 0x1000>;
 218                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 220                         clock-names = "ahb", "mod";
 221                         resets = <&ccu RST_BUS_NAND>;
 222                         reset-names = "ahb";
 223                         pinctrl-names = "default";
 224                         pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
 225                         status = "disabled";
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                 };
 229
 230                 usb_otg: usb@1c19000 {
 231                         /* compatible gets set in SoC specific dtsi file */
 232                         reg = <0x01c19000 0x0400>;
 233                         clocks = <&ccu CLK_BUS_OTG>;
 234                         resets = <&ccu RST_BUS_OTG>;
 235                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 236                         interrupt-names = "mc";
 237                         phys = <&usbphy 0>;
 238                         phy-names = "usb";
 239                         extcon = <&usbphy 0>;
 240                         status = "disabled";
 241                 };
 242
 243                 usbphy: phy@1c19400 {
 244                         /*
 245                          * compatible and address regions get set in
 246                          * SoC specific dtsi file
 247                          */
 248                         clocks = <&ccu CLK_USB_PHY0>,
 249                                  <&ccu CLK_USB_PHY1>;
 250                         clock-names = "usb0_phy",
 251                                       "usb1_phy";
 252                         resets = <&ccu RST_USB_PHY0>,
 253                                  <&ccu RST_USB_PHY1>;
 254                         reset-names = "usb0_reset",
 255                                       "usb1_reset";
 256                         status = "disabled";
 257                         #phy-cells = <1>;
 258                 };
 259
 260                 ehci0: usb@1c1a000 {
 261                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 262                         reg = <0x01c1a000 0x100>;
 263                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&ccu CLK_BUS_EHCI>;
 265                         resets = <&ccu RST_BUS_EHCI>;
 266                         phys = <&usbphy 1>;
 267                         phy-names = "usb";
 268                         status = "disabled";
 269                 };
 270
 271                 ohci0: usb@1c1a400 {
 272                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 273                         reg = <0x01c1a400 0x100>;
 274                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
 276                         resets = <&ccu RST_BUS_OHCI>;
 277                         phys = <&usbphy 1>;
 278                         phy-names = "usb";
 279                         status = "disabled";
 280                 };
 281
 282                 ccu: clock@1c20000 {
 283                         reg = <0x01c20000 0x400>;
 284                         clocks = <&osc24M>, <&rtc 0>;
 285                         clock-names = "hosc", "losc";
 286                         #clock-cells = <1>;
 287                         #reset-cells = <1>;
 288                 };
 289
 290                 pio: pinctrl@1c20800 {
 291                         /* compatible gets set in SoC specific dtsi file */
 292                         reg = <0x01c20800 0x400>;
 293                         /* interrupts get set in SoC specific dtsi file */
 294                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 295                         clock-names = "apb", "hosc", "losc";
 296                         gpio-controller;
 297                         interrupt-controller;
 298                         #interrupt-cells = <3>;
 299                         #gpio-cells = <3>;
 300
 301                         uart0_pins_a: uart0@0 {
 302                                 pins = "PF2", "PF4";
 303                                 function = "uart0";
 304                         };
 305
 306                         uart1_pins_a: uart1@0 {
 307                                 pins = "PG6", "PG7";
 308                                 function = "uart1";
 309                         };
 310
 311                         uart1_pins_cts_rts_a: uart1-cts-rts@0 {
 312                                 pins = "PG8", "PG9";
 313                                 function = "uart1";
 314                         };
 315
 316                         mmc0_pins_a: mmc0@0 {
 317                                 pins = "PF0", "PF1", "PF2",
 318                                        "PF3", "PF4", "PF5";
 319                                 function = "mmc0";
 320                                 drive-strength = <30>;
 321                                 bias-pull-up;
 322                         };
 323
 324                         mmc1_pins_a: mmc1@0 {
 325                                 pins = "PG0", "PG1", "PG2",
 326                                        "PG3", "PG4", "PG5";
 327                                 function = "mmc1";
 328                                 drive-strength = <30>;
 329                                 bias-pull-up;
 330                         };
 331
 332                         mmc2_8bit_pins: mmc2_8bit {
 333                                 pins = "PC5", "PC6", "PC8",
 334                                        "PC9", "PC10", "PC11",
 335                                        "PC12", "PC13", "PC14",
 336                                        "PC15", "PC16";
 337                                 function = "mmc2";
 338                                 drive-strength = <30>;
 339                                 bias-pull-up;
 340                         };
 341
 342                         nand_pins: nand-pins {
 343                                 pins = "PC0", "PC1", "PC2", "PC5",
 344                                        "PC8", "PC9", "PC10", "PC11",
 345                                        "PC12", "PC13", "PC14", "PC15";
 346                                 function = "nand0";
 347                         };
 348
 349                         nand_pins_cs0: nand-pins-cs0 {
 350                                 pins = "PC4";
 351                                 function = "nand0";
 352                                 bias-pull-up;
 353                         };
 354
 355                         nand_pins_cs1: nand-pins-cs1 {
 356                                 pins = "PC3";
 357                                 function = "nand0";
 358                                 bias-pull-up;
 359                         };
 360
 361                         nand_pins_rb0: nand-pins-rb0 {
 362                                 pins = "PC6";
 363                                 function = "nand0";
 364                                 bias-pull-up;
 365                         };
 366
 367                         nand_pins_rb1: nand-pins-rb1 {
 368                                 pins = "PC7";
 369                                 function = "nand0";
 370                                 bias-pull-up;
 371                         };
 372
 373                         pwm0_pins: pwm0 {
 374                                 pins = "PH0";
 375                                 function = "pwm0";
 376                         };
 377
 378                         i2c0_pins_a: i2c0@0 {
 379                                 pins = "PH2", "PH3";
 380                                 function = "i2c0";
 381                         };
 382
 383                         i2c1_pins_a: i2c1@0 {
 384                                 pins = "PH4", "PH5";
 385                                 function = "i2c1";
 386                         };
 387
 388                         i2c2_pins_a: i2c2@0 {
 389                                 pins = "PE12", "PE13";
 390                                 function = "i2c2";
 391                         };
 392
 393                         lcd_rgb666_pins: lcd-rgb666@0 {
 394                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 395                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 396                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 397                                        "PD24", "PD25", "PD26", "PD27";
 398                                 function = "lcd0";
 399                         };
 400                 };
 401
 402                 timer@1c20c00 {
 403                         compatible = "allwinner,sun4i-a10-timer";
 404                         reg = <0x01c20c00 0xa0>;
 405                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 406                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&osc24M>;
 408                 };
 409
 410                 wdt0: watchdog@1c20ca0 {
 411                         compatible = "allwinner,sun6i-a31-wdt";
 412                         reg = <0x01c20ca0 0x20>;
 413                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 414                 };
 415
 416                 pwm: pwm@1c21400 {
 417                         compatible = "allwinner,sun7i-a20-pwm";
 418                         reg = <0x01c21400 0xc>;
 419                         clocks = <&osc24M>;
 420                         #pwm-cells = <3>;
 421                         status = "disabled";
 422                 };
 423
 424                 lradc: lradc@1c22800 {
 425                         compatible = "allwinner,sun4i-a10-lradc-keys";
 426                         reg = <0x01c22800 0x100>;
 427                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 428                         status = "disabled";
 429                 };
 430
 431                 uart0: serial@1c28000 {
 432                         compatible = "snps,dw-apb-uart";
 433                         reg = <0x01c28000 0x400>;
 434                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 435                         reg-shift = <2>;
 436                         reg-io-width = <4>;
 437                         clocks = <&ccu CLK_BUS_UART0>;
 438                         resets = <&ccu RST_BUS_UART0>;
 439                         dmas = <&dma 6>, <&dma 6>;
 440                         dma-names = "rx", "tx";
 441                         status = "disabled";
 442                 };
 443
 444                 uart1: serial@1c28400 {
 445                         compatible = "snps,dw-apb-uart";
 446                         reg = <0x01c28400 0x400>;
 447                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 448                         reg-shift = <2>;
 449                         reg-io-width = <4>;
 450                         clocks = <&ccu CLK_BUS_UART1>;
 451                         resets = <&ccu RST_BUS_UART1>;
 452                         dmas = <&dma 7>, <&dma 7>;
 453                         dma-names = "rx", "tx";
 454                         status = "disabled";
 455                 };
 456
 457                 uart2: serial@1c28800 {
 458                         compatible = "snps,dw-apb-uart";
 459                         reg = <0x01c28800 0x400>;
 460                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 461                         reg-shift = <2>;
 462                         reg-io-width = <4>;
 463                         clocks = <&ccu CLK_BUS_UART2>;
 464                         resets = <&ccu RST_BUS_UART2>;
 465                         dmas = <&dma 8>, <&dma 8>;
 466                         dma-names = "rx", "tx";
 467                         status = "disabled";
 468                 };
 469
 470                 uart3: serial@1c28c00 {
 471                         compatible = "snps,dw-apb-uart";
 472                         reg = <0x01c28c00 0x400>;
 473                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 474                         reg-shift = <2>;
 475                         reg-io-width = <4>;
 476                         clocks = <&ccu CLK_BUS_UART3>;
 477                         resets = <&ccu RST_BUS_UART3>;
 478                         dmas = <&dma 9>, <&dma 9>;
 479                         dma-names = "rx", "tx";
 480                         status = "disabled";
 481                 };
 482
 483                 uart4: serial@1c29000 {
 484                         compatible = "snps,dw-apb-uart";
 485                         reg = <0x01c29000 0x400>;
 486                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 487                         reg-shift = <2>;
 488                         reg-io-width = <4>;
 489                         clocks = <&ccu CLK_BUS_UART4>;
 490                         resets = <&ccu RST_BUS_UART4>;
 491                         dmas = <&dma 10>, <&dma 10>;
 492                         dma-names = "rx", "tx";
 493                         status = "disabled";
 494                 };
 495
 496                 i2c0: i2c@1c2ac00 {
 497                         compatible = "allwinner,sun6i-a31-i2c";
 498                         reg = <0x01c2ac00 0x400>;
 499                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&ccu CLK_BUS_I2C0>;
 501                         resets = <&ccu RST_BUS_I2C0>;
 502                         status = "disabled";
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                 };
 506
 507                 i2c1: i2c@1c2b000 {
 508                         compatible = "allwinner,sun6i-a31-i2c";
 509                         reg = <0x01c2b000 0x400>;
 510                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&ccu CLK_BUS_I2C1>;
 512                         resets = <&ccu RST_BUS_I2C1>;
 513                         status = "disabled";
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                 };
 517
 518                 i2c2: i2c@1c2b400 {
 519                         compatible = "allwinner,sun6i-a31-i2c";
 520                         reg = <0x01c2b400 0x400>;
 521                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&ccu CLK_BUS_I2C2>;
 523                         resets = <&ccu RST_BUS_I2C2>;
 524                         status = "disabled";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                 };
 528
 529                 mali: gpu@1c40000 {
 530                         compatible = "allwinner,sun8i-a23-mali",
 531                                      "allwinner,sun7i-a20-mali", "arm,mali-400";
 532                         reg = <0x01c40000 0x10000>;
 533                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 540                         interrupt-names = "gp",
 541                                           "gpmmu",
 542                                           "pp0",
 543                                           "ppmmu0",
 544                                           "pp1",
 545                                           "ppmmu1",
 546                                           "pmu";
 547                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 548                         clock-names = "bus", "core";
 549                         resets = <&ccu RST_BUS_GPU>;
 550                         #cooling-cells = <2>;
 551
 552                         assigned-clocks = <&ccu CLK_GPU>;
 553                         assigned-clock-rates = <384000000>;
 554                 };
 555
 556                 gic: interrupt-controller@1c81000 {
 557                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 558                         reg = <0x01c81000 0x1000>,
 559                               <0x01c82000 0x2000>,
 560                               <0x01c84000 0x2000>,
 561                               <0x01c86000 0x2000>;
 562                         interrupt-controller;
 563                         #interrupt-cells = <3>;
 564                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 565                 };
 566
 567                 rtc: rtc@1f00000 {
 568                         compatible = "allwinner,sun6i-a31-rtc";
 569                         reg = <0x01f00000 0x54>;
 570                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 571                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 572                         clock-output-names = "osc32k";
 573                         clocks = <&ext_osc32k>;
 574                         #clock-cells = <1>;
 575                 };
 576
 577                 nmi_intc: interrupt-controller@1f00c00 {
 578                         compatible = "allwinner,sun6i-a31-r-intc";
 579                         interrupt-controller;
 580                         #interrupt-cells = <2>;
 581                         reg = <0x01f00c00 0x400>;
 582                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 583                 };
 584
 585                 prcm@1f01400 {
 586                         compatible = "allwinner,sun8i-a23-prcm";
 587                         reg = <0x01f01400 0x200>;
 588
 589                         ar100: ar100_clk {
 590                                 compatible = "fixed-factor-clock";
 591                                 #clock-cells = <0>;
 592                                 clock-div = <1>;
 593                                 clock-mult = <1>;
 594                                 clocks = <&osc24M>;
 595                                 clock-output-names = "ar100";
 596                         };
 597
 598                         ahb0: ahb0_clk {
 599                                 compatible = "fixed-factor-clock";
 600                                 #clock-cells = <0>;
 601                                 clock-div = <1>;
 602                                 clock-mult = <1>;
 603                                 clocks = <&ar100>;
 604                                 clock-output-names = "ahb0";
 605                         };
 606
 607                         apb0: apb0_clk {
 608                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 609                                 #clock-cells = <0>;
 610                                 clocks = <&ahb0>;
 611                                 clock-output-names = "apb0";
 612                         };
 613
 614                         apb0_gates: apb0_gates_clk {
 615                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 616                                 #clock-cells = <1>;
 617                                 clocks = <&apb0>;
 618                                 clock-output-names = "apb0_pio", "apb0_timer",
 619                                                 "apb0_rsb", "apb0_uart",
 620                                                 "apb0_i2c";
 621                         };
 622
 623                         apb0_rst: apb0_rst {
 624                                 compatible = "allwinner,sun6i-a31-clock-reset";
 625                                 #reset-cells = <1>;
 626                         };
 627
 628                         codec_analog: codec-analog {
 629                                 compatible = "allwinner,sun8i-a23-codec-analog";
 630                         };
 631                 };
 632
 633                 cpucfg@1f01c00 {
 634                         compatible = "allwinner,sun8i-a23-cpuconfig";
 635                         reg = <0x01f01c00 0x300>;
 636                 };
 637
 638                 r_uart: serial@1f02800 {
 639                         compatible = "snps,dw-apb-uart";
 640                         reg = <0x01f02800 0x400>;
 641                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 642                         reg-shift = <2>;
 643                         reg-io-width = <4>;
 644                         clocks = <&apb0_gates 4>;
 645                         resets = <&apb0_rst 4>;
 646                         status = "disabled";
 647                 };
 648
 649                 r_pio: pinctrl@1f02c00 {
 650                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 651                         reg = <0x01f02c00 0x400>;
 652                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 654                         clock-names = "apb", "hosc", "losc";
 655                         resets = <&apb0_rst 0>;
 656                         gpio-controller;
 657                         interrupt-controller;
 658                         #interrupt-cells = <3>;
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         #gpio-cells = <3>;
 662
 663                         r_rsb_pins: r_rsb {
 664                                 pins = "PL0", "PL1";
 665                                 function = "s_rsb";
 666                                 drive-strength = <20>;
 667                                 bias-pull-up;
 668                         };
 669
 670                         r_uart_pins_a: r_uart@0 {
 671                                 pins = "PL2", "PL3";
 672                                 function = "s_uart";
 673                         };
 674                 };
 675
 676                 r_rsb: rsb@1f03400 {
 677                         compatible = "allwinner,sun8i-a23-rsb";
 678                         reg = <0x01f03400 0x400>;
 679                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 680                         clocks = <&apb0_gates 3>;
 681                         clock-frequency = <3000000>;
 682                         resets = <&apb0_rst 3>;
 683                         pinctrl-names = "default";
 684                         pinctrl-0 = <&r_rsb_pins>;
 685                         status = "disabled";
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                 };
 689         };
 690 };