arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 simplefb_lcd: framebuffer-lcd0 {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "de_be0-lcd0";
  64                         clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
  65                                  <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
  66                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
  67                         status = "disabled";
  68                 };
  69         };
  70
  71         de: display-engine {
  72                 /* compatible gets set in SoC specific dtsi file */
  73                 allwinner,pipelines = <&fe0>;
  74                 status = "disabled";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  83                 clock-frequency = <24000000>;
  84                 arm,cpu-registers-not-fw-configured;
  85         };
  86
  87         cpus {
  88                 enable-method = "allwinner,sun8i-a23";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 cpu0: cpu@0 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         reg = <0>;
  96                 };
  97
  98                 cpu@1 {
  99                         compatible = "arm,cortex-a7";
 100                         device_type = "cpu";
 101                         reg = <1>;
 102                 };
 103         };
 104
 105         clocks {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 osc24M: osc24M_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <24000000>;
 114                         clock-accuracy = <50000>;
 115                         clock-output-names = "osc24M";
 116                 };
 117
 118                 ext_osc32k: ext_osc32k_clk {
 119                         #clock-cells = <0>;
 120                         compatible = "fixed-clock";
 121                         clock-frequency = <32768>;
 122                         clock-accuracy = <50000>;
 123                         clock-output-names = "ext-osc32k";
 124                 };
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132
 133                 system-control@1c00000 {
 134                         compatible = "allwinner,sun8i-a23-system-control";
 135                         reg = <0x01c00000 0x30>;
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         sram_c: sram@1d00000 {
 141                                 compatible = "mmio-sram";
 142                                 reg = <0x01d00000 0x80000>;
 143                                 #address-cells = <1>;
 144                                 #size-cells = <1>;
 145                                 ranges = <0 0x01d00000 0x80000>;
 146
 147                                 ve_sram: sram-section@0 {
 148                                         compatible = "allwinner,sun8i-a23-sram-c1",
 149                                                      "allwinner,sun4i-a10-sram-c1";
 150                                         reg = <0x000000 0x80000>;
 151                                 };
 152                         };
 153                 };
 154
 155                 dma: dma-controller@1c02000 {
 156                         compatible = "allwinner,sun8i-a23-dma";
 157                         reg = <0x01c02000 0x1000>;
 158                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&ccu CLK_BUS_DMA>;
 160                         resets = <&ccu RST_BUS_DMA>;
 161                         #dma-cells = <1>;
 162                 };
 163
 164                 nfc: nand-controller@1c03000 {
 165                         compatible = "allwinner,sun8i-a23-nand-controller";
 166                         reg = <0x01c03000 0x1000>;
 167                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 169                         clock-names = "ahb", "mod";
 170                         resets = <&ccu RST_BUS_NAND>;
 171                         reset-names = "ahb";
 172                         dmas = <&dma 5>;
 173                         dma-names = "rxtx";
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
 176                         status = "disabled";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                 };
 180
 181                 tcon0: lcd-controller@1c0c000 {
 182                         /* compatible gets set in SoC specific dtsi file */
 183                         reg = <0x01c0c000 0x1000>;
 184                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 185                         clocks = <&ccu CLK_BUS_LCD>,
 186                                  <&ccu CLK_LCD_CH0>;
 187                         clock-names = "ahb",
 188                                       "tcon-ch0";
 189                         clock-output-names = "tcon-pixel-clock";
 190                         #clock-cells = <0>;
 191                         resets = <&ccu RST_BUS_LCD>;
 192                         reset-names = "lcd";
 193                         status = "disabled";
 194
 195                         ports {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198
 199                                 tcon0_in: port@0 {
 200                                         reg = <0>;
 201
 202                                         tcon0_in_drc0: endpoint {
 203                                                 remote-endpoint = <&drc0_out_tcon0>;
 204                                         };
 205                                 };
 206
 207                                 tcon0_out: port@1 {
 208                                         reg = <1>;
 209                                 };
 210                         };
 211                 };
 212
 213                 mmc0: mmc@1c0f000 {
 214                         compatible = "allwinner,sun7i-a20-mmc";
 215                         reg = <0x01c0f000 0x1000>;
 216                         clocks = <&ccu CLK_BUS_MMC0>,
 217                                  <&ccu CLK_MMC0>,
 218                                  <&ccu CLK_MMC0_OUTPUT>,
 219                                  <&ccu CLK_MMC0_SAMPLE>;
 220                         clock-names = "ahb",
 221                                       "mmc",
 222                                       "output",
 223                                       "sample";
 224                         resets = <&ccu RST_BUS_MMC0>;
 225                         reset-names = "ahb";
 226                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 227                         pinctrl-names = "default";
 228                         pinctrl-0 = <&mmc0_pins>;
 229                         status = "disabled";
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                 };
 233
 234                 mmc1: mmc@1c10000 {
 235                         compatible = "allwinner,sun7i-a20-mmc";
 236                         reg = <0x01c10000 0x1000>;
 237                         clocks = <&ccu CLK_BUS_MMC1>,
 238                                  <&ccu CLK_MMC1>,
 239                                  <&ccu CLK_MMC1_OUTPUT>,
 240                                  <&ccu CLK_MMC1_SAMPLE>;
 241                         clock-names = "ahb",
 242                                       "mmc",
 243                                       "output",
 244                                       "sample";
 245                         resets = <&ccu RST_BUS_MMC1>;
 246                         reset-names = "ahb";
 247                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 248                         status = "disabled";
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                 };
 252
 253                 mmc2: mmc@1c11000 {
 254                         compatible = "allwinner,sun7i-a20-mmc";
 255                         reg = <0x01c11000 0x1000>;
 256                         clocks = <&ccu CLK_BUS_MMC2>,
 257                                  <&ccu CLK_MMC2>,
 258                                  <&ccu CLK_MMC2_OUTPUT>,
 259                                  <&ccu CLK_MMC2_SAMPLE>;
 260                         clock-names = "ahb",
 261                                       "mmc",
 262                                       "output",
 263                                       "sample";
 264                         resets = <&ccu RST_BUS_MMC2>;
 265                         reset-names = "ahb";
 266                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 267                         status = "disabled";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                 };
 271
 272                 usb_otg: usb@1c19000 {
 273                         /* compatible gets set in SoC specific dtsi file */
 274                         reg = <0x01c19000 0x0400>;
 275                         clocks = <&ccu CLK_BUS_OTG>;
 276                         resets = <&ccu RST_BUS_OTG>;
 277                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 278                         interrupt-names = "mc";
 279                         phys = <&usbphy 0>;
 280                         phy-names = "usb";
 281                         extcon = <&usbphy 0>;
 282                         dr_mode = "otg";
 283                         status = "disabled";
 284                 };
 285
 286                 usbphy: phy@1c19400 {
 287                         /*
 288                          * compatible and address regions get set in
 289                          * SoC specific dtsi file
 290                          */
 291                         clocks = <&ccu CLK_USB_PHY0>,
 292                                  <&ccu CLK_USB_PHY1>;
 293                         clock-names = "usb0_phy",
 294                                       "usb1_phy";
 295                         resets = <&ccu RST_USB_PHY0>,
 296                                  <&ccu RST_USB_PHY1>;
 297                         reset-names = "usb0_reset",
 298                                       "usb1_reset";
 299                         status = "disabled";
 300                         #phy-cells = <1>;
 301                 };
 302
 303                 ehci0: usb@1c1a000 {
 304                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 305                         reg = <0x01c1a000 0x100>;
 306                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&ccu CLK_BUS_EHCI>;
 308                         resets = <&ccu RST_BUS_EHCI>;
 309                         phys = <&usbphy 1>;
 310                         status = "disabled";
 311                 };
 312
 313                 ohci0: usb@1c1a400 {
 314                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 315                         reg = <0x01c1a400 0x100>;
 316                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
 318                         resets = <&ccu RST_BUS_OHCI>;
 319                         phys = <&usbphy 1>;
 320                         status = "disabled";
 321                 };
 322
 323                 ccu: clock@1c20000 {
 324                         reg = <0x01c20000 0x400>;
 325                         clocks = <&osc24M>, <&rtc 0>;
 326                         clock-names = "hosc", "losc";
 327                         #clock-cells = <1>;
 328                         #reset-cells = <1>;
 329                 };
 330
 331                 pio: pinctrl@1c20800 {
 332                         /* compatible gets set in SoC specific dtsi file */
 333                         reg = <0x01c20800 0x400>;
 334                         /* interrupts get set in SoC specific dtsi file */
 335                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 336                         clock-names = "apb", "hosc", "losc";
 337                         gpio-controller;
 338                         interrupt-controller;
 339                         #interrupt-cells = <3>;
 340                         #gpio-cells = <3>;
 341
 342                         i2c0_pins: i2c0-pins {
 343                                 pins = "PH2", "PH3";
 344                                 function = "i2c0";
 345                         };
 346
 347                         i2c1_pins: i2c1-pins {
 348                                 pins = "PH4", "PH5";
 349                                 function = "i2c1";
 350                         };
 351
 352                         i2c2_pins: i2c2-pins {
 353                                 pins = "PE12", "PE13";
 354                                 function = "i2c2";
 355                         };
 356
 357                         lcd_rgb666_pins: lcd-rgb666-pins {
 358                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 359                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 360                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 361                                        "PD24", "PD25", "PD26", "PD27";
 362                                 function = "lcd0";
 363                         };
 364
 365                         mmc0_pins: mmc0-pins {
 366                                 pins = "PF0", "PF1", "PF2",
 367                                        "PF3", "PF4", "PF5";
 368                                 function = "mmc0";
 369                                 drive-strength = <30>;
 370                                 bias-pull-up;
 371                         };
 372
 373                         mmc1_pg_pins: mmc1-pg-pins {
 374                                 pins = "PG0", "PG1", "PG2",
 375                                        "PG3", "PG4", "PG5";
 376                                 function = "mmc1";
 377                                 drive-strength = <30>;
 378                                 bias-pull-up;
 379                         };
 380
 381                         mmc2_8bit_pins: mmc2-8bit-pins {
 382                                 pins = "PC5", "PC6", "PC8",
 383                                        "PC9", "PC10", "PC11",
 384                                        "PC12", "PC13", "PC14",
 385                                        "PC15", "PC16";
 386                                 function = "mmc2";
 387                                 drive-strength = <30>;
 388                                 bias-pull-up;
 389                         };
 390
 391                         nand_pins: nand-pins {
 392                                 pins = "PC0", "PC1", "PC2", "PC5",
 393                                        "PC8", "PC9", "PC10", "PC11",
 394                                        "PC12", "PC13", "PC14", "PC15";
 395                                 function = "nand0";
 396                         };
 397
 398                         nand_cs0_pin: nand-cs0-pin {
 399                                 pins = "PC4";
 400                                 function = "nand0";
 401                                 bias-pull-up;
 402                         };
 403
 404                         nand_cs1_pin: nand-cs1-pin {
 405                                 pins = "PC3";
 406                                 function = "nand0";
 407                                 bias-pull-up;
 408                         };
 409
 410                         nand_rb0_pin: nand-rb0-pin {
 411                                 pins = "PC6";
 412                                 function = "nand0";
 413                                 bias-pull-up;
 414                         };
 415
 416                         nand_rb1_pin: nand-rb1-pin {
 417                                 pins = "PC7";
 418                                 function = "nand0";
 419                                 bias-pull-up;
 420                         };
 421
 422                         pwm0_pin: pwm0-pin {
 423                                 pins = "PH0";
 424                                 function = "pwm0";
 425                         };
 426
 427                         uart0_pf_pins: uart0-pf-pins {
 428                                 pins = "PF2", "PF4";
 429                                 function = "uart0";
 430                         };
 431
 432                         uart1_pg_pins: uart1-pg-pins {
 433                                 pins = "PG6", "PG7";
 434                                 function = "uart1";
 435                         };
 436
 437                         uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
 438                                 pins = "PG8", "PG9";
 439                                 function = "uart1";
 440                         };
 441                 };
 442
 443                 timer@1c20c00 {
 444                         compatible = "allwinner,sun8i-a23-timer";
 445                         reg = <0x01c20c00 0xa0>;
 446                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 447                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 448                         clocks = <&osc24M>;
 449                 };
 450
 451                 wdt0: watchdog@1c20ca0 {
 452                         compatible = "allwinner,sun6i-a31-wdt";
 453                         reg = <0x01c20ca0 0x20>;
 454                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&osc24M>;
 456                 };
 457
 458                 pwm: pwm@1c21400 {
 459                         compatible = "allwinner,sun7i-a20-pwm";
 460                         reg = <0x01c21400 0xc>;
 461                         clocks = <&osc24M>;
 462                         #pwm-cells = <3>;
 463                         status = "disabled";
 464                 };
 465
 466                 lradc: lradc@1c22800 {
 467                         compatible = "allwinner,sun4i-a10-lradc-keys";
 468                         reg = <0x01c22800 0x100>;
 469                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 470                         status = "disabled";
 471                 };
 472
 473                 uart0: serial@1c28000 {
 474                         compatible = "snps,dw-apb-uart";
 475                         reg = <0x01c28000 0x400>;
 476                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 477                         reg-shift = <2>;
 478                         reg-io-width = <4>;
 479                         clocks = <&ccu CLK_BUS_UART0>;
 480                         resets = <&ccu RST_BUS_UART0>;
 481                         dmas = <&dma 6>, <&dma 6>;
 482                         dma-names = "rx", "tx";
 483                         status = "disabled";
 484                 };
 485
 486                 uart1: serial@1c28400 {
 487                         compatible = "snps,dw-apb-uart";
 488                         reg = <0x01c28400 0x400>;
 489                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 490                         reg-shift = <2>;
 491                         reg-io-width = <4>;
 492                         clocks = <&ccu CLK_BUS_UART1>;
 493                         resets = <&ccu RST_BUS_UART1>;
 494                         dmas = <&dma 7>, <&dma 7>;
 495                         dma-names = "rx", "tx";
 496                         status = "disabled";
 497                 };
 498
 499                 uart2: serial@1c28800 {
 500                         compatible = "snps,dw-apb-uart";
 501                         reg = <0x01c28800 0x400>;
 502                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 503                         reg-shift = <2>;
 504                         reg-io-width = <4>;
 505                         clocks = <&ccu CLK_BUS_UART2>;
 506                         resets = <&ccu RST_BUS_UART2>;
 507                         dmas = <&dma 8>, <&dma 8>;
 508                         dma-names = "rx", "tx";
 509                         status = "disabled";
 510                 };
 511
 512                 uart3: serial@1c28c00 {
 513                         compatible = "snps,dw-apb-uart";
 514                         reg = <0x01c28c00 0x400>;
 515                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 516                         reg-shift = <2>;
 517                         reg-io-width = <4>;
 518                         clocks = <&ccu CLK_BUS_UART3>;
 519                         resets = <&ccu RST_BUS_UART3>;
 520                         dmas = <&dma 9>, <&dma 9>;
 521                         dma-names = "rx", "tx";
 522                         status = "disabled";
 523                 };
 524
 525                 uart4: serial@1c29000 {
 526                         compatible = "snps,dw-apb-uart";
 527                         reg = <0x01c29000 0x400>;
 528                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 529                         reg-shift = <2>;
 530                         reg-io-width = <4>;
 531                         clocks = <&ccu CLK_BUS_UART4>;
 532                         resets = <&ccu RST_BUS_UART4>;
 533                         dmas = <&dma 10>, <&dma 10>;
 534                         dma-names = "rx", "tx";
 535                         status = "disabled";
 536                 };
 537
 538                 i2c0: i2c@1c2ac00 {
 539                         compatible = "allwinner,sun6i-a31-i2c";
 540                         reg = <0x01c2ac00 0x400>;
 541                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 542                         clocks = <&ccu CLK_BUS_I2C0>;
 543                         resets = <&ccu RST_BUS_I2C0>;
 544                         pinctrl-names = "default";
 545                         pinctrl-0 = <&i2c0_pins>;
 546                         status = "disabled";
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                 };
 550
 551                 i2c1: i2c@1c2b000 {
 552                         compatible = "allwinner,sun6i-a31-i2c";
 553                         reg = <0x01c2b000 0x400>;
 554                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&ccu CLK_BUS_I2C1>;
 556                         resets = <&ccu RST_BUS_I2C1>;
 557                         pinctrl-names = "default";
 558                         pinctrl-0 = <&i2c1_pins>;
 559                         status = "disabled";
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                 };
 563
 564                 i2c2: i2c@1c2b400 {
 565                         compatible = "allwinner,sun6i-a31-i2c";
 566                         reg = <0x01c2b400 0x400>;
 567                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 568                         clocks = <&ccu CLK_BUS_I2C2>;
 569                         resets = <&ccu RST_BUS_I2C2>;
 570                         pinctrl-names = "default";
 571                         pinctrl-0 = <&i2c2_pins>;
 572                         status = "disabled";
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                 };
 576
 577                 mali: gpu@1c40000 {
 578                         compatible = "allwinner,sun8i-a23-mali",
 579                                      "allwinner,sun7i-a20-mali", "arm,mali-400";
 580                         reg = <0x01c40000 0x10000>;
 581                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 588                         interrupt-names = "gp",
 589                                           "gpmmu",
 590                                           "pp0",
 591                                           "ppmmu0",
 592                                           "pp1",
 593                                           "ppmmu1",
 594                                           "pmu";
 595                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 596                         clock-names = "bus", "core";
 597                         resets = <&ccu RST_BUS_GPU>;
 598                         #cooling-cells = <2>;
 599
 600                         assigned-clocks = <&ccu CLK_GPU>;
 601                         assigned-clock-rates = <384000000>;
 602                 };
 603
 604                 gic: interrupt-controller@1c81000 {
 605                         compatible = "arm,gic-400";
 606                         reg = <0x01c81000 0x1000>,
 607                               <0x01c82000 0x2000>,
 608                               <0x01c84000 0x2000>,
 609                               <0x01c86000 0x2000>;
 610                         interrupt-controller;
 611                         #interrupt-cells = <3>;
 612                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 613                 };
 614
 615                 fe0: display-frontend@1e00000 {
 616                         /* compatible gets set in SoC specific dtsi file */
 617                         reg = <0x01e00000 0x20000>;
 618                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
 620                                  <&ccu CLK_DRAM_DE_FE>;
 621                         clock-names = "ahb", "mod",
 622                                       "ram";
 623                         resets = <&ccu RST_BUS_DE_FE>;
 624
 625                         ports {
 626                                 #address-cells = <1>;
 627                                 #size-cells = <0>;
 628
 629                                 fe0_out: port@1 {
 630                                         reg = <1>;
 631
 632                                         fe0_out_be0: endpoint {
 633                                                 remote-endpoint = <&be0_in_fe0>;
 634                                         };
 635                                 };
 636                         };
 637                 };
 638
 639                 be0: display-backend@1e60000 {
 640                         /* compatible gets set in SoC specific dtsi file */
 641                         reg = <0x01e60000 0x10000>;
 642                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 644                                  <&ccu CLK_DRAM_DE_BE>;
 645                         clock-names = "ahb", "mod",
 646                                       "ram";
 647                         resets = <&ccu RST_BUS_DE_BE>;
 648
 649                         ports {
 650                                 #address-cells = <1>;
 651                                 #size-cells = <0>;
 652
 653                                 be0_in: port@0 {
 654                                         reg = <0>;
 655
 656                                         be0_in_fe0: endpoint {
 657                                                 remote-endpoint = <&fe0_out_be0>;
 658                                         };
 659                                 };
 660
 661                                 be0_out: port@1 {
 662                                         reg = <1>;
 663
 664                                         be0_out_drc0: endpoint {
 665                                                 remote-endpoint = <&drc0_in_be0>;
 666                                         };
 667                                 };
 668                         };
 669                 };
 670
 671                 drc0: drc@1e70000 {
 672                         /* compatible gets set in SoC specific dtsi file */
 673                         reg = <0x01e70000 0x10000>;
 674                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 675                         clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
 676                                  <&ccu CLK_DRAM_DRC>;
 677                         clock-names = "ahb", "mod", "ram";
 678                         resets = <&ccu RST_BUS_DRC>;
 679
 680                         assigned-clocks = <&ccu CLK_DRC>;
 681                         assigned-clock-rates = <300000000>;
 682
 683                         ports {
 684                                 #address-cells = <1>;
 685                                 #size-cells = <0>;
 686
 687                                 drc0_in: port@0 {
 688                                         reg = <0>;
 689
 690                                         drc0_in_be0: endpoint {
 691                                                 remote-endpoint = <&be0_out_drc0>;
 692                                         };
 693                                 };
 694
 695                                 drc0_out: port@1 {
 696                                         reg = <1>;
 697
 698                                         drc0_out_tcon0: endpoint {
 699                                                 remote-endpoint = <&tcon0_in_drc0>;
 700                                         };
 701                                 };
 702                         };
 703                 };
 704
 705                 rtc: rtc@1f00000 {
 706                         compatible = "allwinner,sun8i-a23-rtc";
 707                         reg = <0x01f00000 0x400>;
 708                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 710                         clock-output-names = "osc32k", "osc32k-out";
 711                         clocks = <&ext_osc32k>;
 712                         #clock-cells = <1>;
 713                 };
 714
 715                 nmi_intc: interrupt-controller@1f00c00 {
 716                         compatible = "allwinner,sun6i-a31-r-intc";
 717                         interrupt-controller;
 718                         #interrupt-cells = <2>;
 719                         reg = <0x01f00c00 0x400>;
 720                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 721                 };
 722
 723                 prcm@1f01400 {
 724                         compatible = "allwinner,sun8i-a23-prcm";
 725                         reg = <0x01f01400 0x200>;
 726
 727                         ar100: ar100_clk {
 728                                 compatible = "fixed-factor-clock";
 729                                 #clock-cells = <0>;
 730                                 clock-div = <1>;
 731                                 clock-mult = <1>;
 732                                 clocks = <&osc24M>;
 733                                 clock-output-names = "ar100";
 734                         };
 735
 736                         ahb0: ahb0_clk {
 737                                 compatible = "fixed-factor-clock";
 738                                 #clock-cells = <0>;
 739                                 clock-div = <1>;
 740                                 clock-mult = <1>;
 741                                 clocks = <&ar100>;
 742                                 clock-output-names = "ahb0";
 743                         };
 744
 745                         apb0: apb0_clk {
 746                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 747                                 #clock-cells = <0>;
 748                                 clocks = <&ahb0>;
 749                                 clock-output-names = "apb0";
 750                         };
 751
 752                         apb0_gates: apb0_gates_clk {
 753                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 754                                 #clock-cells = <1>;
 755                                 clocks = <&apb0>;
 756                                 clock-output-names = "apb0_pio", "apb0_timer",
 757                                                 "apb0_rsb", "apb0_uart",
 758                                                 "apb0_i2c";
 759                         };
 760
 761                         apb0_rst: apb0_rst {
 762                                 compatible = "allwinner,sun6i-a31-clock-reset";
 763                                 #reset-cells = <1>;
 764                         };
 765
 766                         codec_analog: codec-analog {
 767                                 compatible = "allwinner,sun8i-a23-codec-analog";
 768                         };
 769                 };
 770
 771                 cpucfg@1f01c00 {
 772                         compatible = "allwinner,sun8i-a23-cpuconfig";
 773                         reg = <0x01f01c00 0x300>;
 774                 };
 775
 776                 r_uart: serial@1f02800 {
 777                         compatible = "snps,dw-apb-uart";
 778                         reg = <0x01f02800 0x400>;
 779                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 780                         reg-shift = <2>;
 781                         reg-io-width = <4>;
 782                         clocks = <&apb0_gates 4>;
 783                         resets = <&apb0_rst 4>;
 784                         status = "disabled";
 785                 };
 786
 787                 r_i2c: i2c@1f02400 {
 788                         compatible = "allwinner,sun8i-a23-i2c",
 789                                      "allwinner,sun6i-a31-i2c";
 790                         reg = <0x01f02400 0x400>;
 791                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 792                         pinctrl-names = "default";
 793                         pinctrl-0 = <&r_i2c_pins>;
 794                         clocks = <&apb0_gates 6>;
 795                         resets = <&apb0_rst 6>;
 796                         status = "disabled";
 797                         #address-cells = <1>;
 798                         #size-cells = <0>;
 799                 };
 800
 801                 r_pio: pinctrl@1f02c00 {
 802                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 803                         reg = <0x01f02c00 0x400>;
 804                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 805                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 806                         clock-names = "apb", "hosc", "losc";
 807                         resets = <&apb0_rst 0>;
 808                         gpio-controller;
 809                         interrupt-controller;
 810                         #interrupt-cells = <3>;
 811                         #gpio-cells = <3>;
 812
 813                         r_i2c_pins: r-i2c-pins {
 814                                 pins = "PL0", "PL1";
 815                                 function = "s_i2c";
 816                                 bias-pull-up;
 817                         };
 818
 819                         r_rsb_pins: r-rsb-pins {
 820                                 pins = "PL0", "PL1";
 821                                 function = "s_rsb";
 822                                 drive-strength = <20>;
 823                                 bias-pull-up;
 824                         };
 825
 826                         r_uart_pins_a: r-uart-pins {
 827                                 pins = "PL2", "PL3";
 828                                 function = "s_uart";
 829                         };
 830                 };
 831
 832                 r_rsb: rsb@1f03400 {
 833                         compatible = "allwinner,sun8i-a23-rsb";
 834                         reg = <0x01f03400 0x400>;
 835                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 836                         clocks = <&apb0_gates 3>;
 837                         clock-frequency = <3000000>;
 838                         resets = <&apb0_rst 3>;
 839                         pinctrl-names = "default";
 840                         pinctrl-0 = <&r_rsb_pins>;
 841                         status = "disabled";
 842                         #address-cells = <1>;
 843                         #size-cells = <0>;
 844                 };
 845         };
 846 };