arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 simplefb_lcd: framebuffer-lcd0 {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "de_be0-lcd0";
  64                         clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
  65                                  <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
  66                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
  67                         status = "disabled";
  68                 };
  69         };
  70
  71         de: display-engine {
  72                 /* compatible gets set in SoC specific dtsi file */
  73                 allwinner,pipelines = <&fe0>;
  74                 status = "disabled";
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  83                 clock-frequency = <24000000>;
  84                 arm,cpu-registers-not-fw-configured;
  85         };
  86
  87         cpus {
  88                 enable-method = "allwinner,sun8i-a23";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 cpu0: cpu@0 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         reg = <0>;
  96                 };
  97
  98                 cpu@1 {
  99                         compatible = "arm,cortex-a7";
 100                         device_type = "cpu";
 101                         reg = <1>;
 102                 };
 103         };
 104
 105         clocks {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 osc24M: osc24M_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <24000000>;
 114                         clock-accuracy = <50000>;
 115                         clock-output-names = "osc24M";
 116                 };
 117
 118                 ext_osc32k: ext_osc32k_clk {
 119                         #clock-cells = <0>;
 120                         compatible = "fixed-clock";
 121                         clock-frequency = <32768>;
 122                         clock-accuracy = <50000>;
 123                         clock-output-names = "ext-osc32k";
 124                 };
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132
 133                 system-control@1c00000 {
 134                         compatible = "allwinner,sun8i-a23-system-control";
 135                         reg = <0x01c00000 0x30>;
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         sram_c: sram@1d00000 {
 141                                 compatible = "mmio-sram";
 142                                 reg = <0x01d00000 0x80000>;
 143                                 #address-cells = <1>;
 144                                 #size-cells = <1>;
 145                                 ranges = <0 0x01d00000 0x80000>;
 146
 147                                 ve_sram: sram-section@0 {
 148                                         compatible = "allwinner,sun8i-a23-sram-c1",
 149                                                      "allwinner,sun4i-a10-sram-c1";
 150                                         reg = <0x000000 0x80000>;
 151                                 };
 152                         };
 153                 };
 154
 155                 dma: dma-controller@1c02000 {
 156                         compatible = "allwinner,sun8i-a23-dma";
 157                         reg = <0x01c02000 0x1000>;
 158                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&ccu CLK_BUS_DMA>;
 160                         resets = <&ccu RST_BUS_DMA>;
 161                         #dma-cells = <1>;
 162                 };
 163
 164                 nfc: nand@1c03000 {
 165                         compatible = "allwinner,sun4i-a10-nand";
 166                         reg = <0x01c03000 0x1000>;
 167                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 169                         clock-names = "ahb", "mod";
 170                         resets = <&ccu RST_BUS_NAND>;
 171                         reset-names = "ahb";
 172                         status = "disabled";
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                 };
 176
 177                 tcon0: lcd-controller@1c0c000 {
 178                         /* compatible gets set in SoC specific dtsi file */
 179                         reg = <0x01c0c000 0x1000>;
 180                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&ccu CLK_BUS_LCD>,
 182                                  <&ccu CLK_LCD_CH0>;
 183                         clock-names = "ahb",
 184                                       "tcon-ch0";
 185                         clock-output-names = "tcon-pixel-clock";
 186                         resets = <&ccu RST_BUS_LCD>;
 187                         reset-names = "lcd";
 188                         status = "disabled";
 189
 190                         ports {
 191                                 #address-cells = <1>;
 192                                 #size-cells = <0>;
 193
 194                                 tcon0_in: port@0 {
 195                                         #address-cells = <1>;
 196                                         #size-cells = <0>;
 197                                         reg = <0>;
 198
 199                                         tcon0_in_drc0: endpoint@0 {
 200                                                 reg = <0>;
 201                                                 remote-endpoint = <&drc0_out_tcon0>;
 202                                         };
 203                                 };
 204
 205                                 tcon0_out: port@1 {
 206                                         #address-cells = <1>;
 207                                         #size-cells = <0>;
 208                                         reg = <1>;
 209                                 };
 210                         };
 211                 };
 212
 213                 mmc0: mmc@1c0f000 {
 214                         compatible = "allwinner,sun7i-a20-mmc";
 215                         reg = <0x01c0f000 0x1000>;
 216                         clocks = <&ccu CLK_BUS_MMC0>,
 217                                  <&ccu CLK_MMC0>,
 218                                  <&ccu CLK_MMC0_OUTPUT>,
 219                                  <&ccu CLK_MMC0_SAMPLE>;
 220                         clock-names = "ahb",
 221                                       "mmc",
 222                                       "output",
 223                                       "sample";
 224                         resets = <&ccu RST_BUS_MMC0>;
 225                         reset-names = "ahb";
 226                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 227                         pinctrl-names = "default";
 228                         pinctrl-0 = <&mmc0_pins>;
 229                         status = "disabled";
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                 };
 233
 234                 mmc1: mmc@1c10000 {
 235                         compatible = "allwinner,sun7i-a20-mmc";
 236                         reg = <0x01c10000 0x1000>;
 237                         clocks = <&ccu CLK_BUS_MMC1>,
 238                                  <&ccu CLK_MMC1>,
 239                                  <&ccu CLK_MMC1_OUTPUT>,
 240                                  <&ccu CLK_MMC1_SAMPLE>;
 241                         clock-names = "ahb",
 242                                       "mmc",
 243                                       "output",
 244                                       "sample";
 245                         resets = <&ccu RST_BUS_MMC1>;
 246                         reset-names = "ahb";
 247                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 248                         status = "disabled";
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                 };
 252
 253                 mmc2: mmc@1c11000 {
 254                         compatible = "allwinner,sun7i-a20-mmc";
 255                         reg = <0x01c11000 0x1000>;
 256                         clocks = <&ccu CLK_BUS_MMC2>,
 257                                  <&ccu CLK_MMC2>,
 258                                  <&ccu CLK_MMC2_OUTPUT>,
 259                                  <&ccu CLK_MMC2_SAMPLE>;
 260                         clock-names = "ahb",
 261                                       "mmc",
 262                                       "output",
 263                                       "sample";
 264                         resets = <&ccu RST_BUS_MMC2>;
 265                         reset-names = "ahb";
 266                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 267                         status = "disabled";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                 };
 271
 272                 usb_otg: usb@1c19000 {
 273                         /* compatible gets set in SoC specific dtsi file */
 274                         reg = <0x01c19000 0x0400>;
 275                         clocks = <&ccu CLK_BUS_OTG>;
 276                         resets = <&ccu RST_BUS_OTG>;
 277                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 278                         interrupt-names = "mc";
 279                         phys = <&usbphy 0>;
 280                         phy-names = "usb";
 281                         extcon = <&usbphy 0>;
 282                         status = "disabled";
 283                 };
 284
 285                 usbphy: phy@1c19400 {
 286                         /*
 287                          * compatible and address regions get set in
 288                          * SoC specific dtsi file
 289                          */
 290                         clocks = <&ccu CLK_USB_PHY0>,
 291                                  <&ccu CLK_USB_PHY1>;
 292                         clock-names = "usb0_phy",
 293                                       "usb1_phy";
 294                         resets = <&ccu RST_USB_PHY0>,
 295                                  <&ccu RST_USB_PHY1>;
 296                         reset-names = "usb0_reset",
 297                                       "usb1_reset";
 298                         status = "disabled";
 299                         #phy-cells = <1>;
 300                 };
 301
 302                 ehci0: usb@1c1a000 {
 303                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 304                         reg = <0x01c1a000 0x100>;
 305                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&ccu CLK_BUS_EHCI>;
 307                         resets = <&ccu RST_BUS_EHCI>;
 308                         phys = <&usbphy 1>;
 309                         phy-names = "usb";
 310                         status = "disabled";
 311                 };
 312
 313                 ohci0: usb@1c1a400 {
 314                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 315                         reg = <0x01c1a400 0x100>;
 316                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
 318                         resets = <&ccu RST_BUS_OHCI>;
 319                         phys = <&usbphy 1>;
 320                         phy-names = "usb";
 321                         status = "disabled";
 322                 };
 323
 324                 ccu: clock@1c20000 {
 325                         reg = <0x01c20000 0x400>;
 326                         clocks = <&osc24M>, <&rtc 0>;
 327                         clock-names = "hosc", "losc";
 328                         #clock-cells = <1>;
 329                         #reset-cells = <1>;
 330                 };
 331
 332                 pio: pinctrl@1c20800 {
 333                         /* compatible gets set in SoC specific dtsi file */
 334                         reg = <0x01c20800 0x400>;
 335                         /* interrupts get set in SoC specific dtsi file */
 336                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 337                         clock-names = "apb", "hosc", "losc";
 338                         gpio-controller;
 339                         interrupt-controller;
 340                         #interrupt-cells = <3>;
 341                         #gpio-cells = <3>;
 342
 343                         i2c0_pins: i2c0-pins {
 344                                 pins = "PH2", "PH3";
 345                                 function = "i2c0";
 346                         };
 347
 348                         i2c1_pins: i2c1-pins {
 349                                 pins = "PH4", "PH5";
 350                                 function = "i2c1";
 351                         };
 352
 353                         i2c2_pins: i2c2-pins {
 354                                 pins = "PE12", "PE13";
 355                                 function = "i2c2";
 356                         };
 357
 358                         lcd_rgb666_pins: lcd-rgb666-pins {
 359                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 360                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 361                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 362                                        "PD24", "PD25", "PD26", "PD27";
 363                                 function = "lcd0";
 364                         };
 365
 366                         mmc0_pins: mmc0-pins {
 367                                 pins = "PF0", "PF1", "PF2",
 368                                        "PF3", "PF4", "PF5";
 369                                 function = "mmc0";
 370                                 drive-strength = <30>;
 371                                 bias-pull-up;
 372                         };
 373
 374                         mmc1_pg_pins: mmc1-pg-pins {
 375                                 pins = "PG0", "PG1", "PG2",
 376                                        "PG3", "PG4", "PG5";
 377                                 function = "mmc1";
 378                                 drive-strength = <30>;
 379                                 bias-pull-up;
 380                         };
 381
 382                         mmc2_8bit_pins: mmc2-8bit-pins {
 383                                 pins = "PC5", "PC6", "PC8",
 384                                        "PC9", "PC10", "PC11",
 385                                        "PC12", "PC13", "PC14",
 386                                        "PC15", "PC16";
 387                                 function = "mmc2";
 388                                 drive-strength = <30>;
 389                                 bias-pull-up;
 390                         };
 391
 392                         nand_pins: nand-pins {
 393                                 pins = "PC0", "PC1", "PC2", "PC5",
 394                                        "PC8", "PC9", "PC10", "PC11",
 395                                        "PC12", "PC13", "PC14", "PC15";
 396                                 function = "nand0";
 397                         };
 398
 399                         nand_pins_cs0: nand-pins-cs0 {
 400                                 pins = "PC4";
 401                                 function = "nand0";
 402                                 bias-pull-up;
 403                         };
 404
 405                         nand_pins_cs1: nand-pins-cs1 {
 406                                 pins = "PC3";
 407                                 function = "nand0";
 408                                 bias-pull-up;
 409                         };
 410
 411                         nand_pins_rb0: nand-pins-rb0 {
 412                                 pins = "PC6";
 413                                 function = "nand0";
 414                                 bias-pull-up;
 415                         };
 416
 417                         nand_pins_rb1: nand-pins-rb1 {
 418                                 pins = "PC7";
 419                                 function = "nand0";
 420                                 bias-pull-up;
 421                         };
 422
 423                         pwm0_pin: pwm0-pin {
 424                                 pins = "PH0";
 425                                 function = "pwm0";
 426                         };
 427
 428                         uart0_pf_pins: uart0-pf-pins {
 429                                 pins = "PF2", "PF4";
 430                                 function = "uart0";
 431                         };
 432
 433                         uart1_pg_pins: uart1-pg-pins {
 434                                 pins = "PG6", "PG7";
 435                                 function = "uart1";
 436                         };
 437
 438                         uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
 439                                 pins = "PG8", "PG9";
 440                                 function = "uart1";
 441                         };
 442                 };
 443
 444                 timer@1c20c00 {
 445                         compatible = "allwinner,sun4i-a10-timer";
 446                         reg = <0x01c20c00 0xa0>;
 447                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 448                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&osc24M>;
 450                 };
 451
 452                 wdt0: watchdog@1c20ca0 {
 453                         compatible = "allwinner,sun6i-a31-wdt";
 454                         reg = <0x01c20ca0 0x20>;
 455                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 456                 };
 457
 458                 pwm: pwm@1c21400 {
 459                         compatible = "allwinner,sun7i-a20-pwm";
 460                         reg = <0x01c21400 0xc>;
 461                         clocks = <&osc24M>;
 462                         #pwm-cells = <3>;
 463                         status = "disabled";
 464                 };
 465
 466                 lradc: lradc@1c22800 {
 467                         compatible = "allwinner,sun4i-a10-lradc-keys";
 468                         reg = <0x01c22800 0x100>;
 469                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 470                         status = "disabled";
 471                 };
 472
 473                 uart0: serial@1c28000 {
 474                         compatible = "snps,dw-apb-uart";
 475                         reg = <0x01c28000 0x400>;
 476                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 477                         reg-shift = <2>;
 478                         reg-io-width = <4>;
 479                         clocks = <&ccu CLK_BUS_UART0>;
 480                         resets = <&ccu RST_BUS_UART0>;
 481                         dmas = <&dma 6>, <&dma 6>;
 482                         dma-names = "rx", "tx";
 483                         status = "disabled";
 484                 };
 485
 486                 uart1: serial@1c28400 {
 487                         compatible = "snps,dw-apb-uart";
 488                         reg = <0x01c28400 0x400>;
 489                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 490                         reg-shift = <2>;
 491                         reg-io-width = <4>;
 492                         clocks = <&ccu CLK_BUS_UART1>;
 493                         resets = <&ccu RST_BUS_UART1>;
 494                         dmas = <&dma 7>, <&dma 7>;
 495                         dma-names = "rx", "tx";
 496                         status = "disabled";
 497                 };
 498
 499                 uart2: serial@1c28800 {
 500                         compatible = "snps,dw-apb-uart";
 501                         reg = <0x01c28800 0x400>;
 502                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 503                         reg-shift = <2>;
 504                         reg-io-width = <4>;
 505                         clocks = <&ccu CLK_BUS_UART2>;
 506                         resets = <&ccu RST_BUS_UART2>;
 507                         dmas = <&dma 8>, <&dma 8>;
 508                         dma-names = "rx", "tx";
 509                         status = "disabled";
 510                 };
 511
 512                 uart3: serial@1c28c00 {
 513                         compatible = "snps,dw-apb-uart";
 514                         reg = <0x01c28c00 0x400>;
 515                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 516                         reg-shift = <2>;
 517                         reg-io-width = <4>;
 518                         clocks = <&ccu CLK_BUS_UART3>;
 519                         resets = <&ccu RST_BUS_UART3>;
 520                         dmas = <&dma 9>, <&dma 9>;
 521                         dma-names = "rx", "tx";
 522                         status = "disabled";
 523                 };
 524
 525                 uart4: serial@1c29000 {
 526                         compatible = "snps,dw-apb-uart";
 527                         reg = <0x01c29000 0x400>;
 528                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 529                         reg-shift = <2>;
 530                         reg-io-width = <4>;
 531                         clocks = <&ccu CLK_BUS_UART4>;
 532                         resets = <&ccu RST_BUS_UART4>;
 533                         dmas = <&dma 10>, <&dma 10>;
 534                         dma-names = "rx", "tx";
 535                         status = "disabled";
 536                 };
 537
 538                 i2c0: i2c@1c2ac00 {
 539                         compatible = "allwinner,sun6i-a31-i2c";
 540                         reg = <0x01c2ac00 0x400>;
 541                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 542                         clocks = <&ccu CLK_BUS_I2C0>;
 543                         resets = <&ccu RST_BUS_I2C0>;
 544                         pinctrl-names = "default";
 545                         pinctrl-0 = <&i2c0_pins>;
 546                         status = "disabled";
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                 };
 550
 551                 i2c1: i2c@1c2b000 {
 552                         compatible = "allwinner,sun6i-a31-i2c";
 553                         reg = <0x01c2b000 0x400>;
 554                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&ccu CLK_BUS_I2C1>;
 556                         resets = <&ccu RST_BUS_I2C1>;
 557                         pinctrl-names = "default";
 558                         pinctrl-0 = <&i2c1_pins>;
 559                         status = "disabled";
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                 };
 563
 564                 i2c2: i2c@1c2b400 {
 565                         compatible = "allwinner,sun6i-a31-i2c";
 566                         reg = <0x01c2b400 0x400>;
 567                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 568                         clocks = <&ccu CLK_BUS_I2C2>;
 569                         resets = <&ccu RST_BUS_I2C2>;
 570                         pinctrl-names = "default";
 571                         pinctrl-0 = <&i2c2_pins>;
 572                         status = "disabled";
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                 };
 576
 577                 mali: gpu@1c40000 {
 578                         compatible = "allwinner,sun8i-a23-mali",
 579                                      "allwinner,sun7i-a20-mali", "arm,mali-400";
 580                         reg = <0x01c40000 0x10000>;
 581                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 588                         interrupt-names = "gp",
 589                                           "gpmmu",
 590                                           "pp0",
 591                                           "ppmmu0",
 592                                           "pp1",
 593                                           "ppmmu1",
 594                                           "pmu";
 595                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 596                         clock-names = "bus", "core";
 597                         resets = <&ccu RST_BUS_GPU>;
 598                         #cooling-cells = <2>;
 599
 600                         assigned-clocks = <&ccu CLK_GPU>;
 601                         assigned-clock-rates = <384000000>;
 602                 };
 603
 604                 gic: interrupt-controller@1c81000 {
 605                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 606                         reg = <0x01c81000 0x1000>,
 607                               <0x01c82000 0x2000>,
 608                               <0x01c84000 0x2000>,
 609                               <0x01c86000 0x2000>;
 610                         interrupt-controller;
 611                         #interrupt-cells = <3>;
 612                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 613                 };
 614
 615                 fe0: display-frontend@1e00000 {
 616                         /* compatible gets set in SoC specific dtsi file */
 617                         reg = <0x01e00000 0x20000>;
 618                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
 620                                  <&ccu CLK_DRAM_DE_FE>;
 621                         clock-names = "ahb", "mod",
 622                                       "ram";
 623                         resets = <&ccu RST_BUS_DE_FE>;
 624
 625                         ports {
 626                                 #address-cells = <1>;
 627                                 #size-cells = <0>;
 628
 629                                 fe0_out: port@1 {
 630                                         #address-cells = <1>;
 631                                         #size-cells = <0>;
 632                                         reg = <1>;
 633
 634                                         fe0_out_be0: endpoint@0 {
 635                                                 reg = <0>;
 636                                                 remote-endpoint = <&be0_in_fe0>;
 637                                         };
 638                                 };
 639                         };
 640                 };
 641
 642                 be0: display-backend@1e60000 {
 643                         /* compatible gets set in SoC specific dtsi file */
 644                         reg = <0x01e60000 0x10000>;
 645                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 646                         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 647                                  <&ccu CLK_DRAM_DE_BE>;
 648                         clock-names = "ahb", "mod",
 649                                       "ram";
 650                         resets = <&ccu RST_BUS_DE_BE>;
 651
 652                         ports {
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655
 656                                 be0_in: port@0 {
 657                                         #address-cells = <1>;
 658                                         #size-cells = <0>;
 659                                         reg = <0>;
 660
 661                                         be0_in_fe0: endpoint@0 {
 662                                                 reg = <0>;
 663                                                 remote-endpoint = <&fe0_out_be0>;
 664                                         };
 665                                 };
 666
 667                                 be0_out: port@1 {
 668                                         #address-cells = <1>;
 669                                         #size-cells = <0>;
 670                                         reg = <1>;
 671
 672                                         be0_out_drc0: endpoint@0 {
 673                                                 reg = <0>;
 674                                                 remote-endpoint = <&drc0_in_be0>;
 675                                         };
 676                                 };
 677                         };
 678                 };
 679
 680                 drc0: drc@1e70000 {
 681                         /* compatible gets set in SoC specific dtsi file */
 682                         reg = <0x01e70000 0x10000>;
 683                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
 685                                  <&ccu CLK_DRAM_DRC>;
 686                         clock-names = "ahb", "mod", "ram";
 687                         resets = <&ccu RST_BUS_DRC>;
 688
 689                         assigned-clocks = <&ccu CLK_DRC>;
 690                         assigned-clock-rates = <300000000>;
 691
 692                         ports {
 693                                 #address-cells = <1>;
 694                                 #size-cells = <0>;
 695
 696                                 drc0_in: port@0 {
 697                                         #address-cells = <1>;
 698                                         #size-cells = <0>;
 699                                         reg = <0>;
 700
 701                                         drc0_in_be0: endpoint@0 {
 702                                                 reg = <0>;
 703                                                 remote-endpoint = <&be0_out_drc0>;
 704                                         };
 705                                 };
 706
 707                                 drc0_out: port@1 {
 708                                         #address-cells = <1>;
 709                                         #size-cells = <0>;
 710                                         reg = <1>;
 711
 712                                         drc0_out_tcon0: endpoint@0 {
 713                                                 reg = <0>;
 714                                                 remote-endpoint = <&tcon0_in_drc0>;
 715                                         };
 716                                 };
 717                         };
 718                 };
 719
 720                 rtc: rtc@1f00000 {
 721                         compatible = "allwinner,sun8i-a23-rtc";
 722                         reg = <0x01f00000 0x400>;
 723                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 724                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 725                         clock-output-names = "osc32k", "osc32k-out";
 726                         clocks = <&ext_osc32k>;
 727                         #clock-cells = <1>;
 728                 };
 729
 730                 nmi_intc: interrupt-controller@1f00c00 {
 731                         compatible = "allwinner,sun6i-a31-r-intc";
 732                         interrupt-controller;
 733                         #interrupt-cells = <2>;
 734                         reg = <0x01f00c00 0x400>;
 735                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 736                 };
 737
 738                 prcm@1f01400 {
 739                         compatible = "allwinner,sun8i-a23-prcm";
 740                         reg = <0x01f01400 0x200>;
 741
 742                         ar100: ar100_clk {
 743                                 compatible = "fixed-factor-clock";
 744                                 #clock-cells = <0>;
 745                                 clock-div = <1>;
 746                                 clock-mult = <1>;
 747                                 clocks = <&osc24M>;
 748                                 clock-output-names = "ar100";
 749                         };
 750
 751                         ahb0: ahb0_clk {
 752                                 compatible = "fixed-factor-clock";
 753                                 #clock-cells = <0>;
 754                                 clock-div = <1>;
 755                                 clock-mult = <1>;
 756                                 clocks = <&ar100>;
 757                                 clock-output-names = "ahb0";
 758                         };
 759
 760                         apb0: apb0_clk {
 761                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 762                                 #clock-cells = <0>;
 763                                 clocks = <&ahb0>;
 764                                 clock-output-names = "apb0";
 765                         };
 766
 767                         apb0_gates: apb0_gates_clk {
 768                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 769                                 #clock-cells = <1>;
 770                                 clocks = <&apb0>;
 771                                 clock-output-names = "apb0_pio", "apb0_timer",
 772                                                 "apb0_rsb", "apb0_uart",
 773                                                 "apb0_i2c";
 774                         };
 775
 776                         apb0_rst: apb0_rst {
 777                                 compatible = "allwinner,sun6i-a31-clock-reset";
 778                                 #reset-cells = <1>;
 779                         };
 780
 781                         codec_analog: codec-analog {
 782                                 compatible = "allwinner,sun8i-a23-codec-analog";
 783                         };
 784                 };
 785
 786                 cpucfg@1f01c00 {
 787                         compatible = "allwinner,sun8i-a23-cpuconfig";
 788                         reg = <0x01f01c00 0x300>;
 789                 };
 790
 791                 r_uart: serial@1f02800 {
 792                         compatible = "snps,dw-apb-uart";
 793                         reg = <0x01f02800 0x400>;
 794                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 795                         reg-shift = <2>;
 796                         reg-io-width = <4>;
 797                         clocks = <&apb0_gates 4>;
 798                         resets = <&apb0_rst 4>;
 799                         status = "disabled";
 800                 };
 801
 802                 r_pio: pinctrl@1f02c00 {
 803                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 804                         reg = <0x01f02c00 0x400>;
 805                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 806                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 807                         clock-names = "apb", "hosc", "losc";
 808                         resets = <&apb0_rst 0>;
 809                         gpio-controller;
 810                         interrupt-controller;
 811                         #interrupt-cells = <3>;
 812                         #gpio-cells = <3>;
 813
 814                         r_rsb_pins: r-rsb-pins {
 815                                 pins = "PL0", "PL1";
 816                                 function = "s_rsb";
 817                                 drive-strength = <20>;
 818                                 bias-pull-up;
 819                         };
 820
 821                         r_uart_pins_a: r-uart-pins {
 822                                 pins = "PL2", "PL3";
 823                                 function = "s_uart";
 824                         };
 825                 };
 826
 827                 r_rsb: rsb@1f03400 {
 828                         compatible = "allwinner,sun8i-a23-rsb";
 829                         reg = <0x01f03400 0x400>;
 830                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 831                         clocks = <&apb0_gates 3>;
 832                         clock-frequency = <3000000>;
 833                         resets = <&apb0_rst 3>;
 834                         pinctrl-names = "default";
 835                         pinctrl-0 = <&r_rsb_pins>;
 836                         status = "disabled";
 837                         #address-cells = <1>;
 838                         #size-cells = <0>;
 839                 };
 840         };
 841 };