arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 simplefb_hdmi: framebuffer@0 {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  70                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  71                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  72                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 simplefb_lcd: framebuffer@1 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  81                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  82                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  83                         status = "disabled";
  84                 };
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93                 clock-frequency = <24000000>;
  94                 arm,cpu-registers-not-fw-configured;
  95         };
  96
  97         cpus {
  98                 enable-method = "allwinner,sun6i-a31";
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 1008000 1200000
 111                                 864000  1200000
 112                                 720000  1100000
 113                                 480000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                         cooling-min-level = <0>;
 117                         cooling-max-level = <3>;
 118                 };
 119
 120                 cpu@1 {
 121                         compatible = "arm,cortex-a7";
 122                         device_type = "cpu";
 123                         reg = <1>;
 124                 };
 125
 126                 cpu@2 {
 127                         compatible = "arm,cortex-a7";
 128                         device_type = "cpu";
 129                         reg = <2>;
 130                 };
 131
 132                 cpu@3 {
 133                         compatible = "arm,cortex-a7";
 134                         device_type = "cpu";
 135                         reg = <3>;
 136                 };
 137         };
 138
 139         thermal-zones {
 140                 cpu_thermal {
 141                         /* milliseconds */
 142                         polling-delay-passive = <250>;
 143                         polling-delay = <1000>;
 144                         thermal-sensors = <&rtp>;
 145
 146                         cooling-maps {
 147                                 map0 {
 148                                         trip = <&cpu_alert0>;
 149                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 150                                 };
 151                         };
 152
 153                         trips {
 154                                 cpu_alert0: cpu_alert0 {
 155                                         /* milliCelsius */
 156                                         temperature = <70000>;
 157                                         hysteresis = <2000>;
 158                                         type = "passive";
 159                                 };
 160
 161                                 cpu_crit: cpu_crit {
 162                                         /* milliCelsius */
 163                                         temperature = <100000>;
 164                                         hysteresis = <2000>;
 165                                         type = "critical";
 166                                 };
 167                         };
 168                 };
 169         };
 170
 171         memory {
 172                 reg = <0x40000000 0x80000000>;
 173         };
 174
 175         pmu {
 176                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 177                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 181         };
 182
 183         clocks {
 184                 #address-cells = <1>;
 185                 #size-cells = <1>;
 186                 ranges;
 187
 188                 osc24M: osc24M {
 189                         #clock-cells = <0>;
 190                         compatible = "fixed-clock";
 191                         clock-frequency = <24000000>;
 192                 };
 193
 194                 osc32k: clk@0 {
 195                         #clock-cells = <0>;
 196                         compatible = "fixed-clock";
 197                         clock-frequency = <32768>;
 198                         clock-output-names = "osc32k";
 199                 };
 200
 201                 /*
 202                  * The following two are dummy clocks, placeholders
 203                  * used in the gmac_tx clock. The gmac driver will
 204                  * choose one parent depending on the PHY interface
 205                  * mode, using clk_set_rate auto-reparenting.
 206                  *
 207                  * The actual TX clock rate is not controlled by the
 208                  * gmac_tx clock.
 209                  */
 210                 mii_phy_tx_clk: clk@1 {
 211                         #clock-cells = <0>;
 212                         compatible = "fixed-clock";
 213                         clock-frequency = <25000000>;
 214                         clock-output-names = "mii_phy_tx";
 215                 };
 216
 217                 gmac_int_tx_clk: clk@2 {
 218                         #clock-cells = <0>;
 219                         compatible = "fixed-clock";
 220                         clock-frequency = <125000000>;
 221                         clock-output-names = "gmac_int_tx";
 222                 };
 223
 224                 gmac_tx_clk: clk@1c200d0 {
 225                         #clock-cells = <0>;
 226                         compatible = "allwinner,sun7i-a20-gmac-clk";
 227                         reg = <0x01c200d0 0x4>;
 228                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 229                         clock-output-names = "gmac_tx";
 230                 };
 231         };
 232
 233         de: display-engine {
 234                 compatible = "allwinner,sun6i-a31-display-engine";
 235                 allwinner,pipelines = <&fe0>, <&fe1>;
 236                 status = "disabled";
 237         };
 238
 239         soc@1c00000 {
 240                 compatible = "simple-bus";
 241                 #address-cells = <1>;
 242                 #size-cells = <1>;
 243                 ranges;
 244
 245                 dma: dma-controller@1c02000 {
 246                         compatible = "allwinner,sun6i-a31-dma";
 247                         reg = <0x01c02000 0x1000>;
 248                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 249                         clocks = <&ccu CLK_AHB1_DMA>;
 250                         resets = <&ccu RST_AHB1_DMA>;
 251                         #dma-cells = <1>;
 252                 };
 253
 254                 tcon0: lcd-controller@1c0c000 {
 255                         compatible = "allwinner,sun6i-a31-tcon";
 256                         reg = <0x01c0c000 0x1000>;
 257                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 258                         resets = <&ccu RST_AHB1_LCD0>;
 259                         reset-names = "lcd";
 260                         clocks = <&ccu CLK_AHB1_LCD0>,
 261                                  <&ccu CLK_LCD0_CH0>,
 262                                  <&ccu CLK_LCD0_CH1>;
 263                         clock-names = "ahb",
 264                                       "tcon-ch0",
 265                                       "tcon-ch1";
 266                         clock-output-names = "tcon0-pixel-clock";
 267
 268                         ports {
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271
 272                                 tcon0_in: port@0 {
 273                                         #address-cells = <1>;
 274                                         #size-cells = <0>;
 275                                         reg = <0>;
 276
 277                                         tcon0_in_drc0: endpoint@0 {
 278                                                 reg = <0>;
 279                                                 remote-endpoint = <&drc0_out_tcon0>;
 280                                         };
 281
 282                                         tcon0_in_drc1: endpoint@1 {
 283                                                 reg = <1>;
 284                                                 remote-endpoint = <&drc1_out_tcon0>;
 285                                         };
 286                                 };
 287
 288                                 tcon0_out: port@1 {
 289                                         #address-cells = <1>;
 290                                         #size-cells = <0>;
 291                                         reg = <1>;
 292
 293                                         tcon0_out_hdmi: endpoint@1 {
 294                                                 reg = <1>;
 295                                                 remote-endpoint = <&hdmi_in_tcon0>;
 296                                                 allwinner,tcon-channel = <1>;
 297                                         };
 298                                 };
 299                         };
 300                 };
 301
 302                 tcon1: lcd-controller@1c0d000 {
 303                         compatible = "allwinner,sun6i-a31-tcon";
 304                         reg = <0x01c0d000 0x1000>;
 305                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 306                         resets = <&ccu RST_AHB1_LCD1>;
 307                         reset-names = "lcd";
 308                         clocks = <&ccu CLK_AHB1_LCD1>,
 309                                  <&ccu CLK_LCD1_CH0>,
 310                                  <&ccu CLK_LCD1_CH1>;
 311                         clock-names = "ahb",
 312                                       "tcon-ch0",
 313                                       "tcon-ch1";
 314                         clock-output-names = "tcon1-pixel-clock";
 315
 316                         ports {
 317                                 #address-cells = <1>;
 318                                 #size-cells = <0>;
 319
 320                                 tcon1_in: port@0 {
 321                                         #address-cells = <1>;
 322                                         #size-cells = <0>;
 323                                         reg = <0>;
 324
 325                                         tcon1_in_drc0: endpoint@0 {
 326                                                 reg = <0>;
 327                                                 remote-endpoint = <&drc0_out_tcon1>;
 328                                         };
 329
 330                                         tcon1_in_drc1: endpoint@1 {
 331                                                 reg = <1>;
 332                                                 remote-endpoint = <&drc1_out_tcon1>;
 333                                         };
 334                                 };
 335
 336                                 tcon1_out: port@1 {
 337                                         #address-cells = <1>;
 338                                         #size-cells = <0>;
 339                                         reg = <1>;
 340
 341                                         tcon1_out_hdmi: endpoint@1 {
 342                                                 reg = <1>;
 343                                                 remote-endpoint = <&hdmi_in_tcon1>;
 344                                                 allwinner,tcon-channel = <1>;
 345                                         };
 346                                 };
 347                         };
 348                 };
 349
 350                 mmc0: mmc@1c0f000 {
 351                         compatible = "allwinner,sun7i-a20-mmc";
 352                         reg = <0x01c0f000 0x1000>;
 353                         clocks = <&ccu CLK_AHB1_MMC0>,
 354                                  <&ccu CLK_MMC0>,
 355                                  <&ccu CLK_MMC0_OUTPUT>,
 356                                  <&ccu CLK_MMC0_SAMPLE>;
 357                         clock-names = "ahb",
 358                                       "mmc",
 359                                       "output",
 360                                       "sample";
 361                         resets = <&ccu RST_AHB1_MMC0>;
 362                         reset-names = "ahb";
 363                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 364                         status = "disabled";
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                 };
 368
 369                 mmc1: mmc@1c10000 {
 370                         compatible = "allwinner,sun7i-a20-mmc";
 371                         reg = <0x01c10000 0x1000>;
 372                         clocks = <&ccu CLK_AHB1_MMC1>,
 373                                  <&ccu CLK_MMC1>,
 374                                  <&ccu CLK_MMC1_OUTPUT>,
 375                                  <&ccu CLK_MMC1_SAMPLE>;
 376                         clock-names = "ahb",
 377                                       "mmc",
 378                                       "output",
 379                                       "sample";
 380                         resets = <&ccu RST_AHB1_MMC1>;
 381                         reset-names = "ahb";
 382                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 383                         status = "disabled";
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                 };
 387
 388                 mmc2: mmc@1c11000 {
 389                         compatible = "allwinner,sun7i-a20-mmc";
 390                         reg = <0x01c11000 0x1000>;
 391                         clocks = <&ccu CLK_AHB1_MMC2>,
 392                                  <&ccu CLK_MMC2>,
 393                                  <&ccu CLK_MMC2_OUTPUT>,
 394                                  <&ccu CLK_MMC2_SAMPLE>;
 395                         clock-names = "ahb",
 396                                       "mmc",
 397                                       "output",
 398                                       "sample";
 399                         resets = <&ccu RST_AHB1_MMC2>;
 400                         reset-names = "ahb";
 401                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 402                         status = "disabled";
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                 };
 406
 407                 mmc3: mmc@1c12000 {
 408                         compatible = "allwinner,sun7i-a20-mmc";
 409                         reg = <0x01c12000 0x1000>;
 410                         clocks = <&ccu CLK_AHB1_MMC3>,
 411                                  <&ccu CLK_MMC3>,
 412                                  <&ccu CLK_MMC3_OUTPUT>,
 413                                  <&ccu CLK_MMC3_SAMPLE>;
 414                         clock-names = "ahb",
 415                                       "mmc",
 416                                       "output",
 417                                       "sample";
 418                         resets = <&ccu RST_AHB1_MMC3>;
 419                         reset-names = "ahb";
 420                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 421                         status = "disabled";
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                 };
 425
 426                 hdmi: hdmi@1c16000 {
 427                         compatible = "allwinner,sun6i-a31-hdmi";
 428                         reg = <0x01c16000 0x1000>;
 429                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
 431                                  <&ccu CLK_HDMI_DDC>,
 432                                  <&ccu CLK_PLL_VIDEO0_2X>,
 433                                  <&ccu CLK_PLL_VIDEO1_2X>;
 434                         clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
 435                         resets = <&ccu RST_AHB1_HDMI>;
 436                         reset-names = "ahb";
 437                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 438                         dmas = <&dma 13>, <&dma 13>, <&dma 14>;
 439                         status = "disabled";
 440
 441                         ports {
 442                                 #address-cells = <1>;
 443                                 #size-cells = <0>;
 444
 445                                 hdmi_in: port@0 {
 446                                         #address-cells = <1>;
 447                                         #size-cells = <0>;
 448                                         reg = <0>;
 449
 450                                         hdmi_in_tcon0: endpoint@0 {
 451                                                 reg = <0>;
 452                                                 remote-endpoint = <&tcon0_out_hdmi>;
 453                                         };
 454
 455                                         hdmi_in_tcon1: endpoint@1 {
 456                                                 reg = <1>;
 457                                                 remote-endpoint = <&tcon1_out_hdmi>;
 458                                         };
 459                                 };
 460
 461                                 hdmi_out: port@1 {
 462                                         #address-cells = <1>;
 463                                         #size-cells = <0>;
 464                                         reg = <1>;
 465                                 };
 466                         };
 467                 };
 468
 469                 usb_otg: usb@1c19000 {
 470                         compatible = "allwinner,sun6i-a31-musb";
 471                         reg = <0x01c19000 0x0400>;
 472                         clocks = <&ccu CLK_AHB1_OTG>;
 473                         resets = <&ccu RST_AHB1_OTG>;
 474                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 475                         interrupt-names = "mc";
 476                         phys = <&usbphy 0>;
 477                         phy-names = "usb";
 478                         extcon = <&usbphy 0>;
 479                         status = "disabled";
 480                 };
 481
 482                 usbphy: phy@1c19400 {
 483                         compatible = "allwinner,sun6i-a31-usb-phy";
 484                         reg = <0x01c19400 0x10>,
 485                               <0x01c1a800 0x4>,
 486                               <0x01c1b800 0x4>;
 487                         reg-names = "phy_ctrl",
 488                                     "pmu1",
 489                                     "pmu2";
 490                         clocks = <&ccu CLK_USB_PHY0>,
 491                                  <&ccu CLK_USB_PHY1>,
 492                                  <&ccu CLK_USB_PHY2>;
 493                         clock-names = "usb0_phy",
 494                                       "usb1_phy",
 495                                       "usb2_phy";
 496                         resets = <&ccu RST_USB_PHY0>,
 497                                  <&ccu RST_USB_PHY1>,
 498                                  <&ccu RST_USB_PHY2>;
 499                         reset-names = "usb0_reset",
 500                                       "usb1_reset",
 501                                       "usb2_reset";
 502                         status = "disabled";
 503                         #phy-cells = <1>;
 504                 };
 505
 506                 ehci0: usb@1c1a000 {
 507                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 508                         reg = <0x01c1a000 0x100>;
 509                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&ccu CLK_AHB1_EHCI0>;
 511                         resets = <&ccu RST_AHB1_EHCI0>;
 512                         phys = <&usbphy 1>;
 513                         phy-names = "usb";
 514                         status = "disabled";
 515                 };
 516
 517                 ohci0: usb@1c1a400 {
 518                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 519                         reg = <0x01c1a400 0x100>;
 520                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 522                         resets = <&ccu RST_AHB1_OHCI0>;
 523                         phys = <&usbphy 1>;
 524                         phy-names = "usb";
 525                         status = "disabled";
 526                 };
 527
 528                 ehci1: usb@1c1b000 {
 529                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 530                         reg = <0x01c1b000 0x100>;
 531                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&ccu CLK_AHB1_EHCI1>;
 533                         resets = <&ccu RST_AHB1_EHCI1>;
 534                         phys = <&usbphy 2>;
 535                         phy-names = "usb";
 536                         status = "disabled";
 537                 };
 538
 539                 ohci1: usb@1c1b400 {
 540                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 541                         reg = <0x01c1b400 0x100>;
 542                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 544                         resets = <&ccu RST_AHB1_OHCI1>;
 545                         phys = <&usbphy 2>;
 546                         phy-names = "usb";
 547                         status = "disabled";
 548                 };
 549
 550                 ohci2: usb@1c1c400 {
 551                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 552                         reg = <0x01c1c400 0x100>;
 553                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 555                         resets = <&ccu RST_AHB1_OHCI2>;
 556                         status = "disabled";
 557                 };
 558
 559                 ccu: clock@1c20000 {
 560                         compatible = "allwinner,sun6i-a31-ccu";
 561                         reg = <0x01c20000 0x400>;
 562                         clocks = <&osc24M>, <&osc32k>;
 563                         clock-names = "hosc", "losc";
 564                         #clock-cells = <1>;
 565                         #reset-cells = <1>;
 566                 };
 567
 568                 pio: pinctrl@1c20800 {
 569                         compatible = "allwinner,sun6i-a31-pinctrl";
 570                         reg = <0x01c20800 0x400>;
 571                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 572                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 575                         clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
 576                         clock-names = "apb", "hosc", "losc";
 577                         gpio-controller;
 578                         interrupt-controller;
 579                         #interrupt-cells = <3>;
 580                         #gpio-cells = <3>;
 581
 582                         gmac_pins_gmii_a: gmac_gmii@0 {
 583                                 pins = "PA0", "PA1", "PA2", "PA3",
 584                                                 "PA4", "PA5", "PA6", "PA7",
 585                                                 "PA8", "PA9", "PA10", "PA11",
 586                                                 "PA12", "PA13", "PA14", "PA15",
 587                                                 "PA16", "PA17", "PA18", "PA19",
 588                                                 "PA20", "PA21", "PA22", "PA23",
 589                                                 "PA24", "PA25", "PA26", "PA27";
 590                                 function = "gmac";
 591                                 /*
 592                                  * data lines in GMII mode run at 125MHz and
 593                                  * might need a higher signal drive strength
 594                                  */
 595                                 drive-strength = <30>;
 596                         };
 597
 598                         gmac_pins_mii_a: gmac_mii@0 {
 599                                 pins = "PA0", "PA1", "PA2", "PA3",
 600                                                 "PA8", "PA9", "PA11",
 601                                                 "PA12", "PA13", "PA14", "PA19",
 602                                                 "PA20", "PA21", "PA22", "PA23",
 603                                                 "PA24", "PA26", "PA27";
 604                                 function = "gmac";
 605                         };
 606
 607                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 608                                 pins = "PA0", "PA1", "PA2", "PA3",
 609                                                 "PA9", "PA10", "PA11",
 610                                                 "PA12", "PA13", "PA14", "PA19",
 611                                                 "PA20", "PA25", "PA26", "PA27";
 612                                 function = "gmac";
 613                                 /*
 614                                  * data lines in RGMII mode use DDR mode
 615                                  * and need a higher signal drive strength
 616                                  */
 617                                 drive-strength = <40>;
 618                         };
 619
 620                         i2c0_pins_a: i2c0@0 {
 621                                 pins = "PH14", "PH15";
 622                                 function = "i2c0";
 623                         };
 624
 625                         i2c1_pins_a: i2c1@0 {
 626                                 pins = "PH16", "PH17";
 627                                 function = "i2c1";
 628                         };
 629
 630                         i2c2_pins_a: i2c2@0 {
 631                                 pins = "PH18", "PH19";
 632                                 function = "i2c2";
 633                         };
 634
 635                         lcd0_rgb888_pins: lcd0_rgb888 {
 636                                 pins = "PD0", "PD1", "PD2", "PD3",
 637                                                  "PD4", "PD5", "PD6", "PD7",
 638                                                  "PD8", "PD9", "PD10", "PD11",
 639                                                  "PD12", "PD13", "PD14", "PD15",
 640                                                  "PD16", "PD17", "PD18", "PD19",
 641                                                  "PD20", "PD21", "PD22", "PD23",
 642                                                  "PD24", "PD25", "PD26", "PD27";
 643                                 function = "lcd0";
 644                         };
 645
 646                         mmc0_pins_a: mmc0@0 {
 647                                 pins = "PF0", "PF1", "PF2",
 648                                                  "PF3", "PF4", "PF5";
 649                                 function = "mmc0";
 650                                 drive-strength = <30>;
 651                                 bias-pull-up;
 652                         };
 653
 654                         mmc1_pins_a: mmc1@0 {
 655                                 pins = "PG0", "PG1", "PG2", "PG3",
 656                                                  "PG4", "PG5";
 657                                 function = "mmc1";
 658                                 drive-strength = <30>;
 659                                 bias-pull-up;
 660                         };
 661
 662                         mmc2_pins_a: mmc2@0 {
 663                                 pins = "PC6", "PC7", "PC8", "PC9",
 664                                                  "PC10", "PC11";
 665                                 function = "mmc2";
 666                                 drive-strength = <30>;
 667                                 bias-pull-up;
 668                         };
 669
 670                         mmc2_8bit_emmc_pins: mmc2@1 {
 671                                 pins = "PC6", "PC7", "PC8", "PC9",
 672                                                  "PC10", "PC11", "PC12",
 673                                                  "PC13", "PC14", "PC15",
 674                                                  "PC24";
 675                                 function = "mmc2";
 676                                 drive-strength = <30>;
 677                                 bias-pull-up;
 678                         };
 679
 680                         mmc3_8bit_emmc_pins: mmc3@1 {
 681                                 pins = "PC6", "PC7", "PC8", "PC9",
 682                                                  "PC10", "PC11", "PC12",
 683                                                  "PC13", "PC14", "PC15",
 684                                                  "PC24";
 685                                 function = "mmc3";
 686                                 drive-strength = <40>;
 687                                 bias-pull-up;
 688                         };
 689
 690                         spdif_pins_a: spdif@0 {
 691                                 pins = "PH28";
 692                                 function = "spdif";
 693                         };
 694
 695                         uart0_pins_a: uart0@0 {
 696                                 pins = "PH20", "PH21";
 697                                 function = "uart0";
 698                         };
 699                 };
 700
 701                 timer@1c20c00 {
 702                         compatible = "allwinner,sun4i-a10-timer";
 703                         reg = <0x01c20c00 0xa0>;
 704                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&osc24M>;
 710                 };
 711
 712                 wdt1: watchdog@1c20ca0 {
 713                         compatible = "allwinner,sun6i-a31-wdt";
 714                         reg = <0x01c20ca0 0x20>;
 715                 };
 716
 717                 spdif: spdif@1c21000 {
 718                         #sound-dai-cells = <0>;
 719                         compatible = "allwinner,sun6i-a31-spdif";
 720                         reg = <0x01c21000 0x400>;
 721                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
 723                         resets = <&ccu RST_APB1_SPDIF>;
 724                         clock-names = "apb", "spdif";
 725                         dmas = <&dma 2>, <&dma 2>;
 726                         dma-names = "rx", "tx";
 727                         status = "disabled";
 728                 };
 729
 730                 i2s0: i2s@1c22000 {
 731                         #sound-dai-cells = <0>;
 732                         compatible = "allwinner,sun6i-a31-i2s";
 733                         reg = <0x01c22000 0x400>;
 734                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
 736                         resets = <&ccu RST_APB1_DAUDIO0>;
 737                         clock-names = "apb", "mod";
 738                         dmas = <&dma 3>, <&dma 3>;
 739                         dma-names = "rx", "tx";
 740                         status = "disabled";
 741                 };
 742
 743                 i2s1: i2s@1c22400 {
 744                         #sound-dai-cells = <0>;
 745                         compatible = "allwinner,sun6i-a31-i2s";
 746                         reg = <0x01c22400 0x400>;
 747                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
 749                         resets = <&ccu RST_APB1_DAUDIO1>;
 750                         clock-names = "apb", "mod";
 751                         dmas = <&dma 4>, <&dma 4>;
 752                         dma-names = "rx", "tx";
 753                         status = "disabled";
 754                 };
 755
 756                 lradc: lradc@1c22800 {
 757                         compatible = "allwinner,sun4i-a10-lradc-keys";
 758                         reg = <0x01c22800 0x100>;
 759                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 760                         status = "disabled";
 761                 };
 762
 763                 rtp: rtp@1c25000 {
 764                         compatible = "allwinner,sun6i-a31-ts";
 765                         reg = <0x01c25000 0x100>;
 766                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 767                         #thermal-sensor-cells = <0>;
 768                 };
 769
 770                 uart0: serial@1c28000 {
 771                         compatible = "snps,dw-apb-uart";
 772                         reg = <0x01c28000 0x400>;
 773                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 774                         reg-shift = <2>;
 775                         reg-io-width = <4>;
 776                         clocks = <&ccu CLK_APB2_UART0>;
 777                         resets = <&ccu RST_APB2_UART0>;
 778                         dmas = <&dma 6>, <&dma 6>;
 779                         dma-names = "rx", "tx";
 780                         status = "disabled";
 781                 };
 782
 783                 uart1: serial@1c28400 {
 784                         compatible = "snps,dw-apb-uart";
 785                         reg = <0x01c28400 0x400>;
 786                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 787                         reg-shift = <2>;
 788                         reg-io-width = <4>;
 789                         clocks = <&ccu CLK_APB2_UART1>;
 790                         resets = <&ccu RST_APB2_UART1>;
 791                         dmas = <&dma 7>, <&dma 7>;
 792                         dma-names = "rx", "tx";
 793                         status = "disabled";
 794                 };
 795
 796                 uart2: serial@1c28800 {
 797                         compatible = "snps,dw-apb-uart";
 798                         reg = <0x01c28800 0x400>;
 799                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 800                         reg-shift = <2>;
 801                         reg-io-width = <4>;
 802                         clocks = <&ccu CLK_APB2_UART2>;
 803                         resets = <&ccu RST_APB2_UART2>;
 804                         dmas = <&dma 8>, <&dma 8>;
 805                         dma-names = "rx", "tx";
 806                         status = "disabled";
 807                 };
 808
 809                 uart3: serial@1c28c00 {
 810                         compatible = "snps,dw-apb-uart";
 811                         reg = <0x01c28c00 0x400>;
 812                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 813                         reg-shift = <2>;
 814                         reg-io-width = <4>;
 815                         clocks = <&ccu CLK_APB2_UART3>;
 816                         resets = <&ccu RST_APB2_UART3>;
 817                         dmas = <&dma 9>, <&dma 9>;
 818                         dma-names = "rx", "tx";
 819                         status = "disabled";
 820                 };
 821
 822                 uart4: serial@1c29000 {
 823                         compatible = "snps,dw-apb-uart";
 824                         reg = <0x01c29000 0x400>;
 825                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 826                         reg-shift = <2>;
 827                         reg-io-width = <4>;
 828                         clocks = <&ccu CLK_APB2_UART4>;
 829                         resets = <&ccu RST_APB2_UART4>;
 830                         dmas = <&dma 10>, <&dma 10>;
 831                         dma-names = "rx", "tx";
 832                         status = "disabled";
 833                 };
 834
 835                 uart5: serial@1c29400 {
 836                         compatible = "snps,dw-apb-uart";
 837                         reg = <0x01c29400 0x400>;
 838                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 839                         reg-shift = <2>;
 840                         reg-io-width = <4>;
 841                         clocks = <&ccu CLK_APB2_UART5>;
 842                         resets = <&ccu RST_APB2_UART5>;
 843                         dmas = <&dma 22>, <&dma 22>;
 844                         dma-names = "rx", "tx";
 845                         status = "disabled";
 846                 };
 847
 848                 i2c0: i2c@1c2ac00 {
 849                         compatible = "allwinner,sun6i-a31-i2c";
 850                         reg = <0x01c2ac00 0x400>;
 851                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 852                         clocks = <&ccu CLK_APB2_I2C0>;
 853                         resets = <&ccu RST_APB2_I2C0>;
 854                         status = "disabled";
 855                         #address-cells = <1>;
 856                         #size-cells = <0>;
 857                 };
 858
 859                 i2c1: i2c@1c2b000 {
 860                         compatible = "allwinner,sun6i-a31-i2c";
 861                         reg = <0x01c2b000 0x400>;
 862                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 863                         clocks = <&ccu CLK_APB2_I2C1>;
 864                         resets = <&ccu RST_APB2_I2C1>;
 865                         status = "disabled";
 866                         #address-cells = <1>;
 867                         #size-cells = <0>;
 868                 };
 869
 870                 i2c2: i2c@1c2b400 {
 871                         compatible = "allwinner,sun6i-a31-i2c";
 872                         reg = <0x01c2b400 0x400>;
 873                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 874                         clocks = <&ccu CLK_APB2_I2C2>;
 875                         resets = <&ccu RST_APB2_I2C2>;
 876                         status = "disabled";
 877                         #address-cells = <1>;
 878                         #size-cells = <0>;
 879                 };
 880
 881                 i2c3: i2c@1c2b800 {
 882                         compatible = "allwinner,sun6i-a31-i2c";
 883                         reg = <0x01c2b800 0x400>;
 884                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 885                         clocks = <&ccu CLK_APB2_I2C3>;
 886                         resets = <&ccu RST_APB2_I2C3>;
 887                         status = "disabled";
 888                         #address-cells = <1>;
 889                         #size-cells = <0>;
 890                 };
 891
 892                 gmac: ethernet@1c30000 {
 893                         compatible = "allwinner,sun7i-a20-gmac";
 894                         reg = <0x01c30000 0x1054>;
 895                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 896                         interrupt-names = "macirq";
 897                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 898                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 899                         resets = <&ccu RST_AHB1_EMAC>;
 900                         reset-names = "stmmaceth";
 901                         snps,pbl = <2>;
 902                         snps,fixed-burst;
 903                         snps,force_sf_dma_mode;
 904                         status = "disabled";
 905                         #address-cells = <1>;
 906                         #size-cells = <0>;
 907                 };
 908
 909                 crypto: crypto-engine@1c15000 {
 910                         compatible = "allwinner,sun6i-a31-crypto",
 911                                      "allwinner,sun4i-a10-crypto";
 912                         reg = <0x01c15000 0x1000>;
 913                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 914                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 915                         clock-names = "ahb", "mod";
 916                         resets = <&ccu RST_AHB1_SS>;
 917                         reset-names = "ahb";
 918                 };
 919
 920                 codec: codec@1c22c00 {
 921                         #sound-dai-cells = <0>;
 922                         compatible = "allwinner,sun6i-a31-codec";
 923                         reg = <0x01c22c00 0x400>;
 924                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 925                         clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
 926                         clock-names = "apb", "codec";
 927                         resets = <&ccu RST_APB1_CODEC>;
 928                         dmas = <&dma 15>, <&dma 15>;
 929                         dma-names = "rx", "tx";
 930                         status = "disabled";
 931                 };
 932
 933                 timer@1c60000 {
 934                         compatible = "allwinner,sun6i-a31-hstimer",
 935                                      "allwinner,sun7i-a20-hstimer";
 936                         reg = <0x01c60000 0x1000>;
 937                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 938                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 939                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 940                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 941                         clocks = <&ccu CLK_AHB1_HSTIMER>;
 942                         resets = <&ccu RST_AHB1_HSTIMER>;
 943                 };
 944
 945                 spi0: spi@1c68000 {
 946                         compatible = "allwinner,sun6i-a31-spi";
 947                         reg = <0x01c68000 0x1000>;
 948                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 949                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
 950                         clock-names = "ahb", "mod";
 951                         dmas = <&dma 23>, <&dma 23>;
 952                         dma-names = "rx", "tx";
 953                         resets = <&ccu RST_AHB1_SPI0>;
 954                         status = "disabled";
 955                 };
 956
 957                 spi1: spi@1c69000 {
 958                         compatible = "allwinner,sun6i-a31-spi";
 959                         reg = <0x01c69000 0x1000>;
 960                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
 962                         clock-names = "ahb", "mod";
 963                         dmas = <&dma 24>, <&dma 24>;
 964                         dma-names = "rx", "tx";
 965                         resets = <&ccu RST_AHB1_SPI1>;
 966                         status = "disabled";
 967                 };
 968
 969                 spi2: spi@1c6a000 {
 970                         compatible = "allwinner,sun6i-a31-spi";
 971                         reg = <0x01c6a000 0x1000>;
 972                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 973                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
 974                         clock-names = "ahb", "mod";
 975                         dmas = <&dma 25>, <&dma 25>;
 976                         dma-names = "rx", "tx";
 977                         resets = <&ccu RST_AHB1_SPI2>;
 978                         status = "disabled";
 979                 };
 980
 981                 spi3: spi@1c6b000 {
 982                         compatible = "allwinner,sun6i-a31-spi";
 983                         reg = <0x01c6b000 0x1000>;
 984                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 985                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
 986                         clock-names = "ahb", "mod";
 987                         dmas = <&dma 26>, <&dma 26>;
 988                         dma-names = "rx", "tx";
 989                         resets = <&ccu RST_AHB1_SPI3>;
 990                         status = "disabled";
 991                 };
 992
 993                 gic: interrupt-controller@1c81000 {
 994                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 995                         reg = <0x01c81000 0x1000>,
 996                               <0x01c82000 0x2000>,
 997                               <0x01c84000 0x2000>,
 998                               <0x01c86000 0x2000>;
 999                         interrupt-controller;
1000                         #interrupt-cells = <3>;
1001                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1002                 };
1003
1004                 fe0: display-frontend@1e00000 {
1005                         compatible = "allwinner,sun6i-a31-display-frontend";
1006                         reg = <0x01e00000 0x20000>;
1007                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1008                         clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1009                                  <&ccu CLK_DRAM_FE0>;
1010                         clock-names = "ahb", "mod",
1011                                       "ram";
1012                         resets = <&ccu RST_AHB1_FE0>;
1013
1014                         ports {
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017
1018                                 fe0_out: port@1 {
1019                                         #address-cells = <1>;
1020                                         #size-cells = <0>;
1021                                         reg = <1>;
1022
1023                                         fe0_out_be0: endpoint@0 {
1024                                                 reg = <0>;
1025                                                 remote-endpoint = <&be0_in_fe0>;
1026                                         };
1027
1028                                         fe0_out_be1: endpoint@1 {
1029                                                 reg = <1>;
1030                                                 remote-endpoint = <&be1_in_fe0>;
1031                                         };
1032                                 };
1033                         };
1034                 };
1035
1036                 fe1: display-frontend@1e20000 {
1037                         compatible = "allwinner,sun6i-a31-display-frontend";
1038                         reg = <0x01e20000 0x20000>;
1039                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1040                         clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1041                                  <&ccu CLK_DRAM_FE1>;
1042                         clock-names = "ahb", "mod",
1043                                       "ram";
1044                         resets = <&ccu RST_AHB1_FE1>;
1045
1046                         ports {
1047                                 #address-cells = <1>;
1048                                 #size-cells = <0>;
1049
1050                                 fe1_out: port@1 {
1051                                         #address-cells = <1>;
1052                                         #size-cells = <0>;
1053                                         reg = <1>;
1054
1055                                         fe1_out_be0: endpoint@0 {
1056                                                 reg = <0>;
1057                                                 remote-endpoint = <&be0_in_fe1>;
1058                                         };
1059
1060                                         fe1_out_be1: endpoint@1 {
1061                                                 reg = <1>;
1062                                                 remote-endpoint = <&be1_in_fe1>;
1063                                         };
1064                                 };
1065                         };
1066                 };
1067
1068                 be1: display-backend@1e40000 {
1069                         compatible = "allwinner,sun6i-a31-display-backend";
1070                         reg = <0x01e40000 0x10000>;
1071                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1072                         clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1073                                  <&ccu CLK_DRAM_BE1>;
1074                         clock-names = "ahb", "mod",
1075                                       "ram";
1076                         resets = <&ccu RST_AHB1_BE1>;
1077
1078                         assigned-clocks = <&ccu CLK_BE1>;
1079                         assigned-clock-rates = <300000000>;
1080
1081                         ports {
1082                                 #address-cells = <1>;
1083                                 #size-cells = <0>;
1084
1085                                 be1_in: port@0 {
1086                                         #address-cells = <1>;
1087                                         #size-cells = <0>;
1088                                         reg = <0>;
1089
1090                                         be1_in_fe0: endpoint@0 {
1091                                                 reg = <0>;
1092                                                 remote-endpoint = <&fe0_out_be1>;
1093                                         };
1094
1095                                         be1_in_fe1: endpoint@1 {
1096                                                 reg = <1>;
1097                                                 remote-endpoint = <&fe1_out_be1>;
1098                                         };
1099                                 };
1100
1101                                 be1_out: port@1 {
1102                                         #address-cells = <1>;
1103                                         #size-cells = <0>;
1104                                         reg = <1>;
1105
1106                                         be1_out_drc1: endpoint@1 {
1107                                                 reg = <1>;
1108                                                 remote-endpoint = <&drc1_in_be1>;
1109                                         };
1110                                 };
1111                         };
1112                 };
1113
1114                 drc1: drc@1e50000 {
1115                         compatible = "allwinner,sun6i-a31-drc";
1116                         reg = <0x01e50000 0x10000>;
1117                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1118                         clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1119                                  <&ccu CLK_DRAM_DRC1>;
1120                         clock-names = "ahb", "mod",
1121                                       "ram";
1122                         resets = <&ccu RST_AHB1_DRC1>;
1123
1124                         assigned-clocks = <&ccu CLK_IEP_DRC1>;
1125                         assigned-clock-rates = <300000000>;
1126
1127                         ports {
1128                                 #address-cells = <1>;
1129                                 #size-cells = <0>;
1130
1131                                 drc1_in: port@0 {
1132                                         #address-cells = <1>;
1133                                         #size-cells = <0>;
1134                                         reg = <0>;
1135
1136                                         drc1_in_be1: endpoint@1 {
1137                                                 reg = <1>;
1138                                                 remote-endpoint = <&be1_out_drc1>;
1139                                         };
1140                                 };
1141
1142                                 drc1_out: port@1 {
1143                                         #address-cells = <1>;
1144                                         #size-cells = <0>;
1145                                         reg = <1>;
1146
1147                                         drc1_out_tcon0: endpoint@0 {
1148                                                 reg = <0>;
1149                                                 remote-endpoint = <&tcon0_in_drc1>;
1150                                         };
1151
1152                                         drc1_out_tcon1: endpoint@1 {
1153                                                 reg = <1>;
1154                                                 remote-endpoint = <&tcon1_in_drc1>;
1155                                         };
1156                                 };
1157                         };
1158                 };
1159
1160                 be0: display-backend@1e60000 {
1161                         compatible = "allwinner,sun6i-a31-display-backend";
1162                         reg = <0x01e60000 0x10000>;
1163                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1164                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1165                                  <&ccu CLK_DRAM_BE0>;
1166                         clock-names = "ahb", "mod",
1167                                       "ram";
1168                         resets = <&ccu RST_AHB1_BE0>;
1169
1170                         assigned-clocks = <&ccu CLK_BE0>;
1171                         assigned-clock-rates = <300000000>;
1172
1173                         ports {
1174                                 #address-cells = <1>;
1175                                 #size-cells = <0>;
1176
1177                                 be0_in: port@0 {
1178                                         #address-cells = <1>;
1179                                         #size-cells = <0>;
1180                                         reg = <0>;
1181
1182                                         be0_in_fe0: endpoint@0 {
1183                                                 reg = <0>;
1184                                                 remote-endpoint = <&fe0_out_be0>;
1185                                         };
1186
1187                                         be0_in_fe1: endpoint@1 {
1188                                                 reg = <1>;
1189                                                 remote-endpoint = <&fe1_out_be0>;
1190                                         };
1191                                 };
1192
1193                                 be0_out: port@1 {
1194                                         #address-cells = <1>;
1195                                         #size-cells = <0>;
1196                                         reg = <1>;
1197
1198                                         be0_out_drc0: endpoint@0 {
1199                                                 reg = <0>;
1200                                                 remote-endpoint = <&drc0_in_be0>;
1201                                         };
1202                                 };
1203                         };
1204                 };
1205
1206                 drc0: drc@1e70000 {
1207                         compatible = "allwinner,sun6i-a31-drc";
1208                         reg = <0x01e70000 0x10000>;
1209                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1210                         clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1211                                  <&ccu CLK_DRAM_DRC0>;
1212                         clock-names = "ahb", "mod",
1213                                       "ram";
1214                         resets = <&ccu RST_AHB1_DRC0>;
1215
1216                         assigned-clocks = <&ccu CLK_IEP_DRC0>;
1217                         assigned-clock-rates = <300000000>;
1218
1219                         ports {
1220                                 #address-cells = <1>;
1221                                 #size-cells = <0>;
1222
1223                                 drc0_in: port@0 {
1224                                         #address-cells = <1>;
1225                                         #size-cells = <0>;
1226                                         reg = <0>;
1227
1228                                         drc0_in_be0: endpoint@0 {
1229                                                 reg = <0>;
1230                                                 remote-endpoint = <&be0_out_drc0>;
1231                                         };
1232                                 };
1233
1234                                 drc0_out: port@1 {
1235                                         #address-cells = <1>;
1236                                         #size-cells = <0>;
1237                                         reg = <1>;
1238
1239                                         drc0_out_tcon0: endpoint@0 {
1240                                                 reg = <0>;
1241                                                 remote-endpoint = <&tcon0_in_drc0>;
1242                                         };
1243
1244                                         drc0_out_tcon1: endpoint@1 {
1245                                                 reg = <1>;
1246                                                 remote-endpoint = <&tcon1_in_drc0>;
1247                                         };
1248                                 };
1249                         };
1250                 };
1251
1252                 rtc: rtc@1f00000 {
1253                         compatible = "allwinner,sun6i-a31-rtc";
1254                         reg = <0x01f00000 0x54>;
1255                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1256                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1257                 };
1258
1259                 nmi_intc: interrupt-controller@1f00c00 {
1260                         compatible = "allwinner,sun6i-a31-r-intc";
1261                         interrupt-controller;
1262                         #interrupt-cells = <2>;
1263                         reg = <0x01f00c00 0x400>;
1264                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1265                 };
1266
1267                 prcm@1f01400 {
1268                         compatible = "allwinner,sun6i-a31-prcm";
1269                         reg = <0x01f01400 0x200>;
1270
1271                         ar100: ar100_clk {
1272                                 compatible = "allwinner,sun6i-a31-ar100-clk";
1273                                 #clock-cells = <0>;
1274                                 clocks = <&osc32k>, <&osc24M>,
1275                                          <&ccu CLK_PLL_PERIPH>,
1276                                          <&ccu CLK_PLL_PERIPH>;
1277                                 clock-output-names = "ar100";
1278                         };
1279
1280                         ahb0: ahb0_clk {
1281                                 compatible = "fixed-factor-clock";
1282                                 #clock-cells = <0>;
1283                                 clock-div = <1>;
1284                                 clock-mult = <1>;
1285                                 clocks = <&ar100>;
1286                                 clock-output-names = "ahb0";
1287                         };
1288
1289                         apb0: apb0_clk {
1290                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1291                                 #clock-cells = <0>;
1292                                 clocks = <&ahb0>;
1293                                 clock-output-names = "apb0";
1294                         };
1295
1296                         apb0_gates: apb0_gates_clk {
1297                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1298                                 #clock-cells = <1>;
1299                                 clocks = <&apb0>;
1300                                 clock-output-names = "apb0_pio", "apb0_ir",
1301                                                 "apb0_timer", "apb0_p2wi",
1302                                                 "apb0_uart", "apb0_1wire",
1303                                                 "apb0_i2c";
1304                         };
1305
1306                         ir_clk: ir_clk {
1307                                 #clock-cells = <0>;
1308                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1309                                 clocks = <&osc32k>, <&osc24M>;
1310                                 clock-output-names = "ir";
1311                         };
1312
1313                         apb0_rst: apb0_rst {
1314                                 compatible = "allwinner,sun6i-a31-clock-reset";
1315                                 #reset-cells = <1>;
1316                         };
1317                 };
1318
1319                 cpucfg@1f01c00 {
1320                         compatible = "allwinner,sun6i-a31-cpuconfig";
1321                         reg = <0x01f01c00 0x300>;
1322                 };
1323
1324                 ir: ir@1f02000 {
1325                         compatible = "allwinner,sun5i-a13-ir";
1326                         clocks = <&apb0_gates 1>, <&ir_clk>;
1327                         clock-names = "apb", "ir";
1328                         resets = <&apb0_rst 1>;
1329                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1330                         reg = <0x01f02000 0x40>;
1331                         status = "disabled";
1332                 };
1333
1334                 r_pio: pinctrl@1f02c00 {
1335                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1336                         reg = <0x01f02c00 0x400>;
1337                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1338                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1339                         clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1340                         clock-names = "apb", "hosc", "losc";
1341                         resets = <&apb0_rst 0>;
1342                         gpio-controller;
1343                         interrupt-controller;
1344                         #interrupt-cells = <3>;
1345                         #size-cells = <0>;
1346                         #gpio-cells = <3>;
1347
1348                         ir_pins_a: ir@0 {
1349                                 pins = "PL4";
1350                                 function = "s_ir";
1351                         };
1352
1353                         p2wi_pins: p2wi {
1354                                 pins = "PL0", "PL1";
1355                                 function = "s_p2wi";
1356                         };
1357                 };
1358
1359                 p2wi: i2c@1f03400 {
1360                         compatible = "allwinner,sun6i-a31-p2wi";
1361                         reg = <0x01f03400 0x400>;
1362                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1363                         clocks = <&apb0_gates 3>;
1364                         clock-frequency = <100000>;
1365                         resets = <&apb0_rst 3>;
1366                         pinctrl-names = "default";
1367                         pinctrl-0 = <&p2wi_pins>;
1368                         status = "disabled";
1369                         #address-cells = <1>;
1370                         #size-cells = <0>;
1371                 };
1372         };
1373 };