2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
65 simplefb_hdmi: framebuffer-lcd0-hdmi {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
76 simplefb_lcd: framebuffer-lcd0 {
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
98 enable-method = "allwinner,sun6i-a31";
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
122 clocks = <&ccu CLK_CPU>;
123 clock-latency = <244144>; /* 8 32k periods */
131 #cooling-cells = <2>;
135 compatible = "arm,cortex-a7";
138 clocks = <&ccu CLK_CPU>;
139 clock-latency = <244144>; /* 8 32k periods */
147 #cooling-cells = <2>;
151 compatible = "arm,cortex-a7";
154 clocks = <&ccu CLK_CPU>;
155 clock-latency = <244144>; /* 8 32k periods */
163 #cooling-cells = <2>;
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
172 thermal-sensors = <&rtp>;
176 trip = <&cpu_alert0>;
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
180 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185 cpu_alert0: cpu_alert0 {
187 temperature = <70000>;
194 temperature = <100000>;
203 compatible = "arm,cortex-a7-pmu";
204 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
217 compatible = "fixed-clock";
218 clock-frequency = <24000000>;
219 clock-output-names = "osc24M";
224 compatible = "fixed-clock";
225 clock-frequency = <32768>;
226 clock-output-names = "osc32k";
230 * The following two are dummy clocks, placeholders
231 * used in the gmac_tx clock. The gmac driver will
232 * choose one parent depending on the PHY interface
233 * mode, using clk_set_rate auto-reparenting.
235 * The actual TX clock rate is not controlled by the
238 mii_phy_tx_clk: clk-mii-phy-tx {
240 compatible = "fixed-clock";
241 clock-frequency = <25000000>;
242 clock-output-names = "mii_phy_tx";
245 gmac_int_tx_clk: clk-gmac-int-tx {
247 compatible = "fixed-clock";
248 clock-frequency = <125000000>;
249 clock-output-names = "gmac_int_tx";
252 gmac_tx_clk: clk@1c200d0 {
254 compatible = "allwinner,sun7i-a20-gmac-clk";
255 reg = <0x01c200d0 0x4>;
256 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
257 clock-output-names = "gmac_tx";
262 compatible = "allwinner,sun6i-a31-display-engine";
263 allwinner,pipelines = <&fe0>, <&fe1>;
268 compatible = "simple-bus";
269 #address-cells = <1>;
273 dma: dma-controller@1c02000 {
274 compatible = "allwinner,sun6i-a31-dma";
275 reg = <0x01c02000 0x1000>;
276 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&ccu CLK_AHB1_DMA>;
278 resets = <&ccu RST_AHB1_DMA>;
282 tcon0: lcd-controller@1c0c000 {
283 compatible = "allwinner,sun6i-a31-tcon";
284 reg = <0x01c0c000 0x1000>;
285 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
286 resets = <&ccu RST_AHB1_LCD0>;
288 clocks = <&ccu CLK_AHB1_LCD0>,
294 clock-output-names = "tcon0-pixel-clock";
297 #address-cells = <1>;
301 #address-cells = <1>;
305 tcon0_in_drc0: endpoint@0 {
307 remote-endpoint = <&drc0_out_tcon0>;
310 tcon0_in_drc1: endpoint@1 {
312 remote-endpoint = <&drc1_out_tcon0>;
317 #address-cells = <1>;
321 tcon0_out_hdmi: endpoint@1 {
323 remote-endpoint = <&hdmi_in_tcon0>;
324 allwinner,tcon-channel = <1>;
330 tcon1: lcd-controller@1c0d000 {
331 compatible = "allwinner,sun6i-a31-tcon";
332 reg = <0x01c0d000 0x1000>;
333 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
334 resets = <&ccu RST_AHB1_LCD1>;
336 clocks = <&ccu CLK_AHB1_LCD1>,
342 clock-output-names = "tcon1-pixel-clock";
345 #address-cells = <1>;
349 #address-cells = <1>;
353 tcon1_in_drc0: endpoint@0 {
355 remote-endpoint = <&drc0_out_tcon1>;
358 tcon1_in_drc1: endpoint@1 {
360 remote-endpoint = <&drc1_out_tcon1>;
365 #address-cells = <1>;
369 tcon1_out_hdmi: endpoint@1 {
371 remote-endpoint = <&hdmi_in_tcon1>;
372 allwinner,tcon-channel = <1>;
379 compatible = "allwinner,sun7i-a20-mmc";
380 reg = <0x01c0f000 0x1000>;
381 clocks = <&ccu CLK_AHB1_MMC0>,
383 <&ccu CLK_MMC0_OUTPUT>,
384 <&ccu CLK_MMC0_SAMPLE>;
389 resets = <&ccu RST_AHB1_MMC0>;
391 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&mmc0_pins>;
395 #address-cells = <1>;
400 compatible = "allwinner,sun7i-a20-mmc";
401 reg = <0x01c10000 0x1000>;
402 clocks = <&ccu CLK_AHB1_MMC1>,
404 <&ccu CLK_MMC1_OUTPUT>,
405 <&ccu CLK_MMC1_SAMPLE>;
410 resets = <&ccu RST_AHB1_MMC1>;
412 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&mmc1_pins>;
416 #address-cells = <1>;
421 compatible = "allwinner,sun7i-a20-mmc";
422 reg = <0x01c11000 0x1000>;
423 clocks = <&ccu CLK_AHB1_MMC2>,
425 <&ccu CLK_MMC2_OUTPUT>,
426 <&ccu CLK_MMC2_SAMPLE>;
431 resets = <&ccu RST_AHB1_MMC2>;
433 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
440 compatible = "allwinner,sun7i-a20-mmc";
441 reg = <0x01c12000 0x1000>;
442 clocks = <&ccu CLK_AHB1_MMC3>,
444 <&ccu CLK_MMC3_OUTPUT>,
445 <&ccu CLK_MMC3_SAMPLE>;
450 resets = <&ccu RST_AHB1_MMC3>;
452 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
459 compatible = "allwinner,sun6i-a31-hdmi";
460 reg = <0x01c16000 0x1000>;
461 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
464 <&ccu CLK_PLL_VIDEO0_2X>,
465 <&ccu CLK_PLL_VIDEO1_2X>;
466 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
467 resets = <&ccu RST_AHB1_HDMI>;
469 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
470 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
474 #address-cells = <1>;
478 #address-cells = <1>;
482 hdmi_in_tcon0: endpoint@0 {
484 remote-endpoint = <&tcon0_out_hdmi>;
487 hdmi_in_tcon1: endpoint@1 {
489 remote-endpoint = <&tcon1_out_hdmi>;
494 #address-cells = <1>;
501 usb_otg: usb@1c19000 {
502 compatible = "allwinner,sun6i-a31-musb";
503 reg = <0x01c19000 0x0400>;
504 clocks = <&ccu CLK_AHB1_OTG>;
505 resets = <&ccu RST_AHB1_OTG>;
506 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
507 interrupt-names = "mc";
510 extcon = <&usbphy 0>;
514 usbphy: phy@1c19400 {
515 compatible = "allwinner,sun6i-a31-usb-phy";
516 reg = <0x01c19400 0x10>,
519 reg-names = "phy_ctrl",
522 clocks = <&ccu CLK_USB_PHY0>,
525 clock-names = "usb0_phy",
528 resets = <&ccu RST_USB_PHY0>,
531 reset-names = "usb0_reset",
539 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
540 reg = <0x01c1a000 0x100>;
541 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&ccu CLK_AHB1_EHCI0>;
543 resets = <&ccu RST_AHB1_EHCI0>;
550 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
551 reg = <0x01c1a400 0x100>;
552 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
554 resets = <&ccu RST_AHB1_OHCI0>;
561 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
562 reg = <0x01c1b000 0x100>;
563 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_AHB1_EHCI1>;
565 resets = <&ccu RST_AHB1_EHCI1>;
572 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
573 reg = <0x01c1b400 0x100>;
574 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
576 resets = <&ccu RST_AHB1_OHCI1>;
583 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
584 reg = <0x01c1c400 0x100>;
585 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
587 resets = <&ccu RST_AHB1_OHCI2>;
592 compatible = "allwinner,sun6i-a31-ccu";
593 reg = <0x01c20000 0x400>;
594 clocks = <&osc24M>, <&osc32k>;
595 clock-names = "hosc", "losc";
600 pio: pinctrl@1c20800 {
601 compatible = "allwinner,sun6i-a31-pinctrl";
602 reg = <0x01c20800 0x400>;
603 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
608 clock-names = "apb", "hosc", "losc";
610 interrupt-controller;
611 #interrupt-cells = <3>;
614 gmac_gmii_pins: gmac-gmii-pins {
615 pins = "PA0", "PA1", "PA2", "PA3",
616 "PA4", "PA5", "PA6", "PA7",
617 "PA8", "PA9", "PA10", "PA11",
618 "PA12", "PA13", "PA14", "PA15",
619 "PA16", "PA17", "PA18", "PA19",
620 "PA20", "PA21", "PA22", "PA23",
621 "PA24", "PA25", "PA26", "PA27";
624 * data lines in GMII mode run at 125MHz and
625 * might need a higher signal drive strength
627 drive-strength = <30>;
630 gmac_mii_pins: gmac-mii-pins {
631 pins = "PA0", "PA1", "PA2", "PA3",
632 "PA8", "PA9", "PA11",
633 "PA12", "PA13", "PA14", "PA19",
634 "PA20", "PA21", "PA22", "PA23",
635 "PA24", "PA26", "PA27";
639 gmac_rgmii_pins: gmac-rgmii-pins {
640 pins = "PA0", "PA1", "PA2", "PA3",
641 "PA9", "PA10", "PA11",
642 "PA12", "PA13", "PA14", "PA19",
643 "PA20", "PA25", "PA26", "PA27";
646 * data lines in RGMII mode use DDR mode
647 * and need a higher signal drive strength
649 drive-strength = <40>;
652 i2c0_pins: i2c0-pins {
653 pins = "PH14", "PH15";
657 i2c1_pins: i2c1-pins {
658 pins = "PH16", "PH17";
662 i2c2_pins: i2c2-pins {
663 pins = "PH18", "PH19";
667 lcd0_rgb888_pins: lcd0-rgb888-pins {
668 pins = "PD0", "PD1", "PD2", "PD3",
669 "PD4", "PD5", "PD6", "PD7",
670 "PD8", "PD9", "PD10", "PD11",
671 "PD12", "PD13", "PD14", "PD15",
672 "PD16", "PD17", "PD18", "PD19",
673 "PD20", "PD21", "PD22", "PD23",
674 "PD24", "PD25", "PD26", "PD27";
678 mmc0_pins: mmc0-pins {
679 pins = "PF0", "PF1", "PF2",
682 drive-strength = <30>;
686 mmc1_pins: mmc1-pins {
687 pins = "PG0", "PG1", "PG2", "PG3",
690 drive-strength = <30>;
694 mmc2_4bit_pins: mmc2-4bit-pins {
695 pins = "PC6", "PC7", "PC8", "PC9",
698 drive-strength = <30>;
702 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
703 pins = "PC6", "PC7", "PC8", "PC9",
704 "PC10", "PC11", "PC12",
705 "PC13", "PC14", "PC15",
708 drive-strength = <30>;
712 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
713 pins = "PC6", "PC7", "PC8", "PC9",
714 "PC10", "PC11", "PC12",
715 "PC13", "PC14", "PC15",
718 drive-strength = <40>;
722 spdif_tx_pin: spdif-tx-pin {
727 uart0_ph_pins: uart0-ph-pins {
728 pins = "PH20", "PH21";
734 compatible = "allwinner,sun4i-a10-timer";
735 reg = <0x01c20c00 0xa0>;
736 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
744 wdt1: watchdog@1c20ca0 {
745 compatible = "allwinner,sun6i-a31-wdt";
746 reg = <0x01c20ca0 0x20>;
749 spdif: spdif@1c21000 {
750 #sound-dai-cells = <0>;
751 compatible = "allwinner,sun6i-a31-spdif";
752 reg = <0x01c21000 0x400>;
753 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
755 resets = <&ccu RST_APB1_SPDIF>;
756 clock-names = "apb", "spdif";
757 dmas = <&dma 2>, <&dma 2>;
758 dma-names = "rx", "tx";
763 #sound-dai-cells = <0>;
764 compatible = "allwinner,sun6i-a31-i2s";
765 reg = <0x01c22000 0x400>;
766 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
768 resets = <&ccu RST_APB1_DAUDIO0>;
769 clock-names = "apb", "mod";
770 dmas = <&dma 3>, <&dma 3>;
771 dma-names = "rx", "tx";
776 #sound-dai-cells = <0>;
777 compatible = "allwinner,sun6i-a31-i2s";
778 reg = <0x01c22400 0x400>;
779 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
781 resets = <&ccu RST_APB1_DAUDIO1>;
782 clock-names = "apb", "mod";
783 dmas = <&dma 4>, <&dma 4>;
784 dma-names = "rx", "tx";
788 lradc: lradc@1c22800 {
789 compatible = "allwinner,sun4i-a10-lradc-keys";
790 reg = <0x01c22800 0x100>;
791 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
796 compatible = "allwinner,sun6i-a31-ts";
797 reg = <0x01c25000 0x100>;
798 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
799 #thermal-sensor-cells = <0>;
802 uart0: serial@1c28000 {
803 compatible = "snps,dw-apb-uart";
804 reg = <0x01c28000 0x400>;
805 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&ccu CLK_APB2_UART0>;
809 resets = <&ccu RST_APB2_UART0>;
810 dmas = <&dma 6>, <&dma 6>;
811 dma-names = "rx", "tx";
815 uart1: serial@1c28400 {
816 compatible = "snps,dw-apb-uart";
817 reg = <0x01c28400 0x400>;
818 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&ccu CLK_APB2_UART1>;
822 resets = <&ccu RST_APB2_UART1>;
823 dmas = <&dma 7>, <&dma 7>;
824 dma-names = "rx", "tx";
828 uart2: serial@1c28800 {
829 compatible = "snps,dw-apb-uart";
830 reg = <0x01c28800 0x400>;
831 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&ccu CLK_APB2_UART2>;
835 resets = <&ccu RST_APB2_UART2>;
836 dmas = <&dma 8>, <&dma 8>;
837 dma-names = "rx", "tx";
841 uart3: serial@1c28c00 {
842 compatible = "snps,dw-apb-uart";
843 reg = <0x01c28c00 0x400>;
844 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&ccu CLK_APB2_UART3>;
848 resets = <&ccu RST_APB2_UART3>;
849 dmas = <&dma 9>, <&dma 9>;
850 dma-names = "rx", "tx";
854 uart4: serial@1c29000 {
855 compatible = "snps,dw-apb-uart";
856 reg = <0x01c29000 0x400>;
857 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&ccu CLK_APB2_UART4>;
861 resets = <&ccu RST_APB2_UART4>;
862 dmas = <&dma 10>, <&dma 10>;
863 dma-names = "rx", "tx";
867 uart5: serial@1c29400 {
868 compatible = "snps,dw-apb-uart";
869 reg = <0x01c29400 0x400>;
870 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&ccu CLK_APB2_UART5>;
874 resets = <&ccu RST_APB2_UART5>;
875 dmas = <&dma 22>, <&dma 22>;
876 dma-names = "rx", "tx";
881 compatible = "allwinner,sun6i-a31-i2c";
882 reg = <0x01c2ac00 0x400>;
883 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&ccu CLK_APB2_I2C0>;
885 resets = <&ccu RST_APB2_I2C0>;
886 pinctrl-names = "default";
887 pinctrl-0 = <&i2c0_pins>;
889 #address-cells = <1>;
894 compatible = "allwinner,sun6i-a31-i2c";
895 reg = <0x01c2b000 0x400>;
896 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&ccu CLK_APB2_I2C1>;
898 resets = <&ccu RST_APB2_I2C1>;
899 pinctrl-names = "default";
900 pinctrl-0 = <&i2c1_pins>;
902 #address-cells = <1>;
907 compatible = "allwinner,sun6i-a31-i2c";
908 reg = <0x01c2b400 0x400>;
909 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&ccu CLK_APB2_I2C2>;
911 resets = <&ccu RST_APB2_I2C2>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&i2c2_pins>;
915 #address-cells = <1>;
920 compatible = "allwinner,sun6i-a31-i2c";
921 reg = <0x01c2b800 0x400>;
922 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&ccu CLK_APB2_I2C3>;
924 resets = <&ccu RST_APB2_I2C3>;
926 #address-cells = <1>;
930 gmac: ethernet@1c30000 {
931 compatible = "allwinner,sun7i-a20-gmac";
932 reg = <0x01c30000 0x1054>;
933 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
934 interrupt-names = "macirq";
935 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
936 clock-names = "stmmaceth", "allwinner_gmac_tx";
937 resets = <&ccu RST_AHB1_EMAC>;
938 reset-names = "stmmaceth";
941 snps,force_sf_dma_mode;
943 #address-cells = <1>;
947 crypto: crypto-engine@1c15000 {
948 compatible = "allwinner,sun6i-a31-crypto",
949 "allwinner,sun4i-a10-crypto";
950 reg = <0x01c15000 0x1000>;
951 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
953 clock-names = "ahb", "mod";
954 resets = <&ccu RST_AHB1_SS>;
958 codec: codec@1c22c00 {
959 #sound-dai-cells = <0>;
960 compatible = "allwinner,sun6i-a31-codec";
961 reg = <0x01c22c00 0x400>;
962 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
964 clock-names = "apb", "codec";
965 resets = <&ccu RST_APB1_CODEC>;
966 dmas = <&dma 15>, <&dma 15>;
967 dma-names = "rx", "tx";
972 compatible = "allwinner,sun6i-a31-hstimer",
973 "allwinner,sun7i-a20-hstimer";
974 reg = <0x01c60000 0x1000>;
975 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&ccu CLK_AHB1_HSTIMER>;
980 resets = <&ccu RST_AHB1_HSTIMER>;
984 compatible = "allwinner,sun6i-a31-spi";
985 reg = <0x01c68000 0x1000>;
986 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
988 clock-names = "ahb", "mod";
989 dmas = <&dma 23>, <&dma 23>;
990 dma-names = "rx", "tx";
991 resets = <&ccu RST_AHB1_SPI0>;
996 compatible = "allwinner,sun6i-a31-spi";
997 reg = <0x01c69000 0x1000>;
998 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1000 clock-names = "ahb", "mod";
1001 dmas = <&dma 24>, <&dma 24>;
1002 dma-names = "rx", "tx";
1003 resets = <&ccu RST_AHB1_SPI1>;
1004 status = "disabled";
1008 compatible = "allwinner,sun6i-a31-spi";
1009 reg = <0x01c6a000 0x1000>;
1010 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1012 clock-names = "ahb", "mod";
1013 dmas = <&dma 25>, <&dma 25>;
1014 dma-names = "rx", "tx";
1015 resets = <&ccu RST_AHB1_SPI2>;
1016 status = "disabled";
1020 compatible = "allwinner,sun6i-a31-spi";
1021 reg = <0x01c6b000 0x1000>;
1022 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1024 clock-names = "ahb", "mod";
1025 dmas = <&dma 26>, <&dma 26>;
1026 dma-names = "rx", "tx";
1027 resets = <&ccu RST_AHB1_SPI3>;
1028 status = "disabled";
1031 gic: interrupt-controller@1c81000 {
1032 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1033 reg = <0x01c81000 0x1000>,
1034 <0x01c82000 0x2000>,
1035 <0x01c84000 0x2000>,
1036 <0x01c86000 0x2000>;
1037 interrupt-controller;
1038 #interrupt-cells = <3>;
1039 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1042 fe0: display-frontend@1e00000 {
1043 compatible = "allwinner,sun6i-a31-display-frontend";
1044 reg = <0x01e00000 0x20000>;
1045 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1047 <&ccu CLK_DRAM_FE0>;
1048 clock-names = "ahb", "mod",
1050 resets = <&ccu RST_AHB1_FE0>;
1053 #address-cells = <1>;
1057 #address-cells = <1>;
1061 fe0_out_be0: endpoint@0 {
1063 remote-endpoint = <&be0_in_fe0>;
1066 fe0_out_be1: endpoint@1 {
1068 remote-endpoint = <&be1_in_fe0>;
1074 fe1: display-frontend@1e20000 {
1075 compatible = "allwinner,sun6i-a31-display-frontend";
1076 reg = <0x01e20000 0x20000>;
1077 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1079 <&ccu CLK_DRAM_FE1>;
1080 clock-names = "ahb", "mod",
1082 resets = <&ccu RST_AHB1_FE1>;
1085 #address-cells = <1>;
1089 #address-cells = <1>;
1093 fe1_out_be0: endpoint@0 {
1095 remote-endpoint = <&be0_in_fe1>;
1098 fe1_out_be1: endpoint@1 {
1100 remote-endpoint = <&be1_in_fe1>;
1106 be1: display-backend@1e40000 {
1107 compatible = "allwinner,sun6i-a31-display-backend";
1108 reg = <0x01e40000 0x10000>;
1109 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1111 <&ccu CLK_DRAM_BE1>;
1112 clock-names = "ahb", "mod",
1114 resets = <&ccu RST_AHB1_BE1>;
1116 assigned-clocks = <&ccu CLK_BE1>;
1117 assigned-clock-rates = <300000000>;
1120 #address-cells = <1>;
1124 #address-cells = <1>;
1128 be1_in_fe0: endpoint@0 {
1130 remote-endpoint = <&fe0_out_be1>;
1133 be1_in_fe1: endpoint@1 {
1135 remote-endpoint = <&fe1_out_be1>;
1140 #address-cells = <1>;
1144 be1_out_drc1: endpoint@1 {
1146 remote-endpoint = <&drc1_in_be1>;
1153 compatible = "allwinner,sun6i-a31-drc";
1154 reg = <0x01e50000 0x10000>;
1155 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1157 <&ccu CLK_DRAM_DRC1>;
1158 clock-names = "ahb", "mod",
1160 resets = <&ccu RST_AHB1_DRC1>;
1162 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1163 assigned-clock-rates = <300000000>;
1166 #address-cells = <1>;
1170 #address-cells = <1>;
1174 drc1_in_be1: endpoint@1 {
1176 remote-endpoint = <&be1_out_drc1>;
1181 #address-cells = <1>;
1185 drc1_out_tcon0: endpoint@0 {
1187 remote-endpoint = <&tcon0_in_drc1>;
1190 drc1_out_tcon1: endpoint@1 {
1192 remote-endpoint = <&tcon1_in_drc1>;
1198 be0: display-backend@1e60000 {
1199 compatible = "allwinner,sun6i-a31-display-backend";
1200 reg = <0x01e60000 0x10000>;
1201 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1203 <&ccu CLK_DRAM_BE0>;
1204 clock-names = "ahb", "mod",
1206 resets = <&ccu RST_AHB1_BE0>;
1208 assigned-clocks = <&ccu CLK_BE0>;
1209 assigned-clock-rates = <300000000>;
1212 #address-cells = <1>;
1216 #address-cells = <1>;
1220 be0_in_fe0: endpoint@0 {
1222 remote-endpoint = <&fe0_out_be0>;
1225 be0_in_fe1: endpoint@1 {
1227 remote-endpoint = <&fe1_out_be0>;
1232 #address-cells = <1>;
1236 be0_out_drc0: endpoint@0 {
1238 remote-endpoint = <&drc0_in_be0>;
1245 compatible = "allwinner,sun6i-a31-drc";
1246 reg = <0x01e70000 0x10000>;
1247 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1248 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1249 <&ccu CLK_DRAM_DRC0>;
1250 clock-names = "ahb", "mod",
1252 resets = <&ccu RST_AHB1_DRC0>;
1254 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1255 assigned-clock-rates = <300000000>;
1258 #address-cells = <1>;
1262 #address-cells = <1>;
1266 drc0_in_be0: endpoint@0 {
1268 remote-endpoint = <&be0_out_drc0>;
1273 #address-cells = <1>;
1277 drc0_out_tcon0: endpoint@0 {
1279 remote-endpoint = <&tcon0_in_drc0>;
1282 drc0_out_tcon1: endpoint@1 {
1284 remote-endpoint = <&tcon1_in_drc0>;
1291 compatible = "allwinner,sun6i-a31-rtc";
1292 reg = <0x01f00000 0x54>;
1293 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1297 nmi_intc: interrupt-controller@1f00c00 {
1298 compatible = "allwinner,sun6i-a31-r-intc";
1299 interrupt-controller;
1300 #interrupt-cells = <2>;
1301 reg = <0x01f00c00 0x400>;
1302 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1306 compatible = "allwinner,sun6i-a31-prcm";
1307 reg = <0x01f01400 0x200>;
1310 compatible = "allwinner,sun6i-a31-ar100-clk";
1312 clocks = <&osc32k>, <&osc24M>,
1313 <&ccu CLK_PLL_PERIPH>,
1314 <&ccu CLK_PLL_PERIPH>;
1315 clock-output-names = "ar100";
1319 compatible = "fixed-factor-clock";
1324 clock-output-names = "ahb0";
1328 compatible = "allwinner,sun6i-a31-apb0-clk";
1331 clock-output-names = "apb0";
1334 apb0_gates: apb0_gates_clk {
1335 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1338 clock-output-names = "apb0_pio", "apb0_ir",
1339 "apb0_timer", "apb0_p2wi",
1340 "apb0_uart", "apb0_1wire",
1346 compatible = "allwinner,sun4i-a10-mod0-clk";
1347 clocks = <&osc32k>, <&osc24M>;
1348 clock-output-names = "ir";
1351 apb0_rst: apb0_rst {
1352 compatible = "allwinner,sun6i-a31-clock-reset";
1358 compatible = "allwinner,sun6i-a31-cpuconfig";
1359 reg = <0x01f01c00 0x300>;
1363 compatible = "allwinner,sun5i-a13-ir";
1364 clocks = <&apb0_gates 1>, <&ir_clk>;
1365 clock-names = "apb", "ir";
1366 resets = <&apb0_rst 1>;
1367 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1368 reg = <0x01f02000 0x40>;
1369 status = "disabled";
1372 r_pio: pinctrl@1f02c00 {
1373 compatible = "allwinner,sun6i-a31-r-pinctrl";
1374 reg = <0x01f02c00 0x400>;
1375 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1377 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1378 clock-names = "apb", "hosc", "losc";
1379 resets = <&apb0_rst 0>;
1381 interrupt-controller;
1382 #interrupt-cells = <3>;
1386 s_ir_rx_pin: s-ir-rx-pin {
1391 s_p2wi_pins: s-p2wi-pins {
1392 pins = "PL0", "PL1";
1393 function = "s_p2wi";
1398 compatible = "allwinner,sun6i-a31-p2wi";
1399 reg = <0x01f03400 0x400>;
1400 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1401 clocks = <&apb0_gates 3>;
1402 clock-frequency = <100000>;
1403 resets = <&apb0_rst 3>;
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&s_p2wi_pins>;
1406 status = "disabled";
1407 #address-cells = <1>;