arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/sun5i-ccu.h>
  46 #include <dt-bindings/dma/sun4i-a10.h>
  47 #include <dt-bindings/reset/sun5i-ccu.h>
  48
  49 / {
  50         interrupt-parent = <&intc>;
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a8";
  61                         reg = <0x0>;
  62                         clocks = <&ccu CLK_CPU>;
  63                 };
  64         };
  65
  66         chosen {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 framebuffer-lcd0 {
  72                         compatible = "allwinner,simple-framebuffer",
  73                                      "simple-framebuffer";
  74                         allwinner,pipeline = "de_be0-lcd0";
  75                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  76                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  77                         status = "disabled";
  78                 };
  79
  80                 framebuffer-lcd0-tve0 {
  81                         compatible = "allwinner,simple-framebuffer",
  82                                      "simple-framebuffer";
  83                         allwinner,pipeline = "de_be0-lcd0-tve0";
  84                         clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
  85                                  <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  86                                  <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
  87                         status = "disabled";
  88                 };
  89         };
  90
  91         clocks {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 osc24M: clk-24M {
  97                         #clock-cells = <0>;
  98                         compatible = "fixed-clock";
  99                         clock-frequency = <24000000>;
 100                         clock-output-names = "osc24M";
 101                 };
 102
 103                 osc32k: clk-32k {
 104                         #clock-cells = <0>;
 105                         compatible = "fixed-clock";
 106                         clock-frequency = <32768>;
 107                         clock-output-names = "osc32k";
 108                 };
 109         };
 110
 111         reserved-memory {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 ranges;
 115
 116                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 117                 default-pool {
 118                         compatible = "shared-dma-pool";
 119                         size = <0x6000000>;
 120                         alloc-ranges = <0x4a000000 0x6000000>;
 121                         reusable;
 122                         linux,cma-default;
 123                 };
 124         };
 125
 126         soc {
 127                 compatible = "simple-bus";
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 dma-ranges;
 131                 ranges;
 132
 133                 system-control@1c00000 {
 134                         compatible = "allwinner,sun5i-a13-system-control";
 135                         reg = <0x01c00000 0x30>;
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         sram_a: sram@0 {
 141                                 compatible = "mmio-sram";
 142                                 reg = <0x00000000 0xc000>;
 143                                 #address-cells = <1>;
 144                                 #size-cells = <1>;
 145                                 ranges = <0 0x00000000 0xc000>;
 146
 147                                 emac_sram: sram-section@8000 {
 148                                         compatible = "allwinner,sun5i-a13-sram-a3-a4",
 149                                                      "allwinner,sun4i-a10-sram-a3-a4";
 150                                         reg = <0x8000 0x4000>;
 151                                         status = "disabled";
 152                                 };
 153                         };
 154
 155                         sram_d: sram@10000 {
 156                                 compatible = "mmio-sram";
 157                                 reg = <0x00010000 0x1000>;
 158                                 #address-cells = <1>;
 159                                 #size-cells = <1>;
 160                                 ranges = <0 0x00010000 0x1000>;
 161
 162                                 otg_sram: sram-section@0 {
 163                                         compatible = "allwinner,sun5i-a13-sram-d",
 164                                                      "allwinner,sun4i-a10-sram-d";
 165                                         reg = <0x0000 0x1000>;
 166                                         status = "disabled";
 167                                 };
 168                         };
 169
 170                         sram_c: sram@1d00000 {
 171                                 compatible = "mmio-sram";
 172                                 reg = <0x01d00000 0xd0000>;
 173                                 #address-cells = <1>;
 174                                 #size-cells = <1>;
 175                                 ranges = <0 0x01d00000 0xd0000>;
 176
 177                                 ve_sram: sram-section@0 {
 178                                         compatible = "allwinner,sun5i-a13-sram-c1",
 179                                                      "allwinner,sun4i-a10-sram-c1";
 180                                         reg = <0x000000 0x80000>;
 181                                 };
 182                         };
 183                 };
 184
 185                 mbus: dram-controller@1c01000 {
 186                         compatible = "allwinner,sun5i-a13-mbus";
 187                         reg = <0x01c01000 0x1000>;
 188                         clocks = <&ccu 99>;
 189                         dma-ranges = <0x00000000 0x40000000 0x20000000>;
 190                         #interconnect-cells = <1>;
 191                 };
 192
 193                 dma: dma-controller@1c02000 {
 194                         compatible = "allwinner,sun4i-a10-dma";
 195                         reg = <0x01c02000 0x1000>;
 196                         interrupts = <27>;
 197                         clocks = <&ccu CLK_AHB_DMA>;
 198                         #dma-cells = <2>;
 199                 };
 200
 201                 nfc: nand-controller@1c03000 {
 202                         compatible = "allwinner,sun4i-a10-nand";
 203                         reg = <0x01c03000 0x1000>;
 204                         interrupts = <37>;
 205                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 206                         clock-names = "ahb", "mod";
 207                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 208                         dma-names = "rxtx";
 209                         status = "disabled";
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                 };
 213
 214                 spi0: spi@1c05000 {
 215                         compatible = "allwinner,sun4i-a10-spi";
 216                         reg = <0x01c05000 0x1000>;
 217                         interrupts = <10>;
 218                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 219                         clock-names = "ahb", "mod";
 220                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 221                                <&dma SUN4I_DMA_DEDICATED 26>;
 222                         dma-names = "rx", "tx";
 223                         status = "disabled";
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                 };
 227
 228                 spi1: spi@1c06000 {
 229                         compatible = "allwinner,sun4i-a10-spi";
 230                         reg = <0x01c06000 0x1000>;
 231                         interrupts = <11>;
 232                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 233                         clock-names = "ahb", "mod";
 234                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 235                                <&dma SUN4I_DMA_DEDICATED 8>;
 236                         dma-names = "rx", "tx";
 237                         status = "disabled";
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                 };
 241
 242                 tve0: tv-encoder@1c0a000 {
 243                         compatible = "allwinner,sun4i-a10-tv-encoder";
 244                         reg = <0x01c0a000 0x1000>;
 245                         clocks = <&ccu CLK_AHB_TVE>;
 246                         resets = <&ccu RST_TVE>;
 247                         status = "disabled";
 248
 249                         port {
 250
 251                                 tve0_in_tcon0: endpoint {
 252                                         remote-endpoint = <&tcon0_out_tve0>;
 253                                 };
 254                         };
 255                 };
 256
 257                 emac: ethernet@1c0b000 {
 258                         compatible = "allwinner,sun4i-a10-emac";
 259                         reg = <0x01c0b000 0x1000>;
 260                         interrupts = <55>;
 261                         clocks = <&ccu CLK_AHB_EMAC>;
 262                         allwinner,sram = <&emac_sram 1>;
 263                         status = "disabled";
 264                 };
 265
 266                 mdio: mdio@1c0b080 {
 267                         compatible = "allwinner,sun4i-a10-mdio";
 268                         reg = <0x01c0b080 0x14>;
 269                         status = "disabled";
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                 };
 273
 274                 tcon0: lcd-controller@1c0c000 {
 275                         compatible = "allwinner,sun5i-a13-tcon";
 276                         reg = <0x01c0c000 0x1000>;
 277                         interrupts = <44>;
 278                         resets = <&ccu RST_LCD>;
 279                         reset-names = "lcd";
 280                         clocks = <&ccu CLK_AHB_LCD>,
 281                                  <&ccu CLK_TCON_CH0>,
 282                                  <&ccu CLK_TCON_CH1>;
 283                         clock-names = "ahb",
 284                                       "tcon-ch0",
 285                                       "tcon-ch1";
 286                         clock-output-names = "tcon-pixel-clock";
 287                         #clock-cells = <0>;
 288                         status = "disabled";
 289
 290                         ports {
 291                                 #address-cells = <1>;
 292                                 #size-cells = <0>;
 293
 294                                 tcon0_in: port@0 {
 295                                         reg = <0>;
 296
 297                                         tcon0_in_be0: endpoint {
 298                                                 remote-endpoint = <&be0_out_tcon0>;
 299                                         };
 300                                 };
 301
 302                                 tcon0_out: port@1 {
 303                                         #address-cells = <1>;
 304                                         #size-cells = <0>;
 305                                         reg = <1>;
 306
 307                                         tcon0_out_tve0: endpoint@1 {
 308                                                 reg = <1>;
 309                                                 remote-endpoint = <&tve0_in_tcon0>;
 310                                                 allwinner,tcon-channel = <1>;
 311                                         };
 312                                 };
 313                         };
 314                 };
 315
 316                 video-codec@1c0e000 {
 317                         compatible = "allwinner,sun5i-a13-video-engine";
 318                         reg = <0x01c0e000 0x1000>;
 319                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 320                                  <&ccu CLK_DRAM_VE>;
 321                         clock-names = "ahb", "mod", "ram";
 322                         resets = <&ccu RST_VE>;
 323                         interrupts = <53>;
 324                         allwinner,sram = <&ve_sram 1>;
 325                 };
 326
 327                 mmc0: mmc@1c0f000 {
 328                         compatible = "allwinner,sun5i-a13-mmc";
 329                         reg = <0x01c0f000 0x1000>;
 330                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 331                         clock-names = "ahb", "mmc";
 332                         interrupts = <32>;
 333                         pinctrl-names = "default";
 334                         pinctrl-0 = <&mmc0_pins>;
 335                         status = "disabled";
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                 };
 339
 340                 mmc1: mmc@1c10000 {
 341                         compatible = "allwinner,sun5i-a13-mmc";
 342                         reg = <0x01c10000 0x1000>;
 343                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 344                         clock-names = "ahb", "mmc";
 345                         interrupts = <33>;
 346                         status = "disabled";
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                 };
 350
 351                 mmc2: mmc@1c11000 {
 352                         compatible = "allwinner,sun5i-a13-mmc";
 353                         reg = <0x01c11000 0x1000>;
 354                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 355                         clock-names = "ahb", "mmc";
 356                         interrupts = <34>;
 357                         status = "disabled";
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                 };
 361
 362                 usb_otg: usb@1c13000 {
 363                         compatible = "allwinner,sun4i-a10-musb";
 364                         reg = <0x01c13000 0x0400>;
 365                         clocks = <&ccu CLK_AHB_OTG>;
 366                         interrupts = <38>;
 367                         interrupt-names = "mc";
 368                         phys = <&usbphy 0>;
 369                         phy-names = "usb";
 370                         extcon = <&usbphy 0>;
 371                         allwinner,sram = <&otg_sram 1>;
 372                         dr_mode = "otg";
 373                         status = "disabled";
 374                 };
 375
 376                 usbphy: phy@1c13400 {
 377                         #phy-cells = <1>;
 378                         compatible = "allwinner,sun5i-a13-usb-phy";
 379                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
 380                         reg-names = "phy_ctrl", "pmu1";
 381                         clocks = <&ccu CLK_USB_PHY0>;
 382                         clock-names = "usb_phy";
 383                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
 384                         reset-names = "usb0_reset", "usb1_reset";
 385                         status = "disabled";
 386                 };
 387
 388                 ehci0: usb@1c14000 {
 389                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 390                         reg = <0x01c14000 0x100>;
 391                         interrupts = <39>;
 392                         clocks = <&ccu CLK_AHB_EHCI>;
 393                         phys = <&usbphy 1>;
 394                         status = "disabled";
 395                 };
 396
 397                 ohci0: usb@1c14400 {
 398                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 399                         reg = <0x01c14400 0x100>;
 400                         interrupts = <40>;
 401                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
 402                         phys = <&usbphy 1>;
 403                         status = "disabled";
 404                 };
 405
 406                 crypto: crypto-engine@1c15000 {
 407                         compatible = "allwinner,sun5i-a13-crypto",
 408                                      "allwinner,sun4i-a10-crypto";
 409                         reg = <0x01c15000 0x1000>;
 410                         interrupts = <54>;
 411                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 412                         clock-names = "ahb", "mod";
 413                 };
 414
 415                 spi2: spi@1c17000 {
 416                         compatible = "allwinner,sun4i-a10-spi";
 417                         reg = <0x01c17000 0x1000>;
 418                         interrupts = <12>;
 419                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 420                         clock-names = "ahb", "mod";
 421                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 422                                <&dma SUN4I_DMA_DEDICATED 28>;
 423                         dma-names = "rx", "tx";
 424                         status = "disabled";
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                 };
 428
 429                 ccu: clock@1c20000 {
 430                         reg = <0x01c20000 0x400>;
 431                         clocks = <&osc24M>, <&osc32k>;
 432                         clock-names = "hosc", "losc";
 433                         #clock-cells = <1>;
 434                         #reset-cells = <1>;
 435                 };
 436
 437                 intc: interrupt-controller@1c20400 {
 438                         compatible = "allwinner,sun4i-a10-ic";
 439                         reg = <0x01c20400 0x400>;
 440                         interrupt-controller;
 441                         #interrupt-cells = <1>;
 442                 };
 443
 444                 pio: pinctrl@1c20800 {
 445                         reg = <0x01c20800 0x400>;
 446                         interrupts = <28>;
 447                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 448                         clock-names = "apb", "hosc", "losc";
 449                         gpio-controller;
 450                         interrupt-controller;
 451                         #interrupt-cells = <3>;
 452                         #gpio-cells = <3>;
 453
 454                         emac_pd_pins: emac-pd-pins {
 455                                 pins = "PD6", "PD7", "PD10",
 456                                        "PD11", "PD12", "PD13", "PD14",
 457                                        "PD15", "PD18", "PD19", "PD20",
 458                                        "PD21", "PD22", "PD23", "PD24",
 459                                        "PD25", "PD26", "PD27";
 460                                 function = "emac";
 461                         };
 462
 463                         i2c0_pins: i2c0-pins {
 464                                 pins = "PB0", "PB1";
 465                                 function = "i2c0";
 466                         };
 467
 468                         i2c1_pins: i2c1-pins {
 469                                 pins = "PB15", "PB16";
 470                                 function = "i2c1";
 471                         };
 472
 473                         i2c2_pins: i2c2-pins {
 474                                 pins = "PB17", "PB18";
 475                                 function = "i2c2";
 476                         };
 477
 478                         ir0_rx_pin: ir0-rx-pin {
 479                                 pins = "PB4";
 480                                 function = "ir0";
 481                         };
 482
 483                         lcd_rgb565_pins: lcd-rgb565-pins {
 484                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 485                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 486                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 487                                                  "PD24", "PD25", "PD26", "PD27";
 488                                 function = "lcd0";
 489                         };
 490
 491                         lcd_rgb666_pins: lcd-rgb666-pins {
 492                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 493                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 494                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 495                                        "PD24", "PD25", "PD26", "PD27";
 496                                 function = "lcd0";
 497                         };
 498
 499                         mmc0_pins: mmc0-pins {
 500                                 pins = "PF0", "PF1", "PF2", "PF3",
 501                                        "PF4", "PF5";
 502                                 function = "mmc0";
 503                                 drive-strength = <30>;
 504                                 bias-pull-up;
 505                         };
 506
 507                         mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
 508                                 pins = "PC6", "PC7", "PC8", "PC9",
 509                                        "PC10", "PC11";
 510                                 function = "mmc2";
 511                                 drive-strength = <30>;
 512                                 bias-pull-up;
 513                         };
 514
 515                         mmc2_8bit_pins: mmc2-8bit-pins {
 516                                 pins = "PC6", "PC7", "PC8", "PC9",
 517                                        "PC10", "PC11", "PC12", "PC13",
 518                                        "PC14", "PC15";
 519                                 function = "mmc2";
 520                                 drive-strength = <30>;
 521                                 bias-pull-up;
 522                         };
 523
 524                         nand_pins: nand-pins {
 525                                 pins = "PC0", "PC1", "PC2",
 526                                        "PC5", "PC8", "PC9", "PC10",
 527                                        "PC11", "PC12", "PC13", "PC14",
 528                                        "PC15";
 529                                 function = "nand0";
 530                         };
 531
 532                         nand_cs0_pin: nand-cs0-pin {
 533                                 pins = "PC4";
 534                                 function = "nand0";
 535                         };
 536
 537                         nand_rb0_pin: nand-rb0-pin {
 538                                 pins = "PC6";
 539                                 function = "nand0";
 540                         };
 541
 542                         pwm0_pin: pwm0-pin {
 543                                 pins = "PB2";
 544                                 function = "pwm";
 545                         };
 546
 547                         spi2_pe_pins: spi2-pe-pins {
 548                                 pins = "PE1", "PE2", "PE3";
 549                                 function = "spi2";
 550                         };
 551
 552                         spi2_cs0_pe_pin: spi2-cs0-pe-pin {
 553                                 pins = "PE0";
 554                                 function = "spi2";
 555                         };
 556
 557                         uart1_pe_pins: uart1-pe-pins {
 558                                 pins = "PE10", "PE11";
 559                                 function = "uart1";
 560                         };
 561
 562                         uart1_pg_pins: uart1-pg-pins {
 563                                 pins = "PG3", "PG4";
 564                                 function = "uart1";
 565                         };
 566
 567                         uart2_pd_pins: uart2-pd-pins {
 568                                 pins = "PD2", "PD3";
 569                                 function = "uart2";
 570                         };
 571
 572                         uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
 573                                 pins = "PD4", "PD5";
 574                                 function = "uart2";
 575                         };
 576
 577                         uart3_pg_pins: uart3-pg-pins {
 578                                 pins = "PG9", "PG10";
 579                                 function = "uart3";
 580                         };
 581
 582                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
 583                                 pins = "PG11", "PG12";
 584                                 function = "uart3";
 585                         };
 586                 };
 587
 588                 timer@1c20c00 {
 589                         compatible = "allwinner,sun4i-a10-timer";
 590                         reg = <0x01c20c00 0x90>;
 591                         interrupts = <22>,
 592                                      <23>,
 593                                      <24>,
 594                                      <25>,
 595                                      <67>,
 596                                      <68>;
 597                         clocks = <&ccu CLK_HOSC>;
 598                 };
 599
 600                 wdt: watchdog@1c20c90 {
 601                         compatible = "allwinner,sun4i-a10-wdt";
 602                         reg = <0x01c20c90 0x10>;
 603                         interrupts = <24>;
 604                         clocks = <&osc24M>;
 605                 };
 606
 607                 ir0: ir@1c21800 {
 608                         compatible = "allwinner,sun4i-a10-ir";
 609                         clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
 610                         clock-names = "apb", "ir";
 611                         interrupts = <5>;
 612                         reg = <0x01c21800 0x40>;
 613                         status = "disabled";
 614                 };
 615
 616                 lradc: lradc@1c22800 {
 617                         compatible = "allwinner,sun4i-a10-lradc-keys";
 618                         reg = <0x01c22800 0x100>;
 619                         interrupts = <31>;
 620                         status = "disabled";
 621                 };
 622
 623                 codec: codec@1c22c00 {
 624                         #sound-dai-cells = <0>;
 625                         compatible = "allwinner,sun4i-a10-codec";
 626                         reg = <0x01c22c00 0x40>;
 627                         interrupts = <30>;
 628                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 629                         clock-names = "apb", "codec";
 630                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 631                                <&dma SUN4I_DMA_NORMAL 19>;
 632                         dma-names = "rx", "tx";
 633                         status = "disabled";
 634                 };
 635
 636                 sid: eeprom@1c23800 {
 637                         compatible = "allwinner,sun4i-a10-sid";
 638                         reg = <0x01c23800 0x10>;
 639                 };
 640
 641                 rtp: rtp@1c25000 {
 642                         compatible = "allwinner,sun5i-a13-ts";
 643                         reg = <0x01c25000 0x100>;
 644                         interrupts = <29>;
 645                         #thermal-sensor-cells = <0>;
 646                 };
 647
 648                 uart0: serial@1c28000 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x01c28000 0x400>;
 651                         interrupts = <1>;
 652                         reg-shift = <2>;
 653                         reg-io-width = <4>;
 654                         clocks = <&ccu CLK_APB1_UART0>;
 655                         status = "disabled";
 656                 };
 657
 658                 uart1: serial@1c28400 {
 659                         compatible = "snps,dw-apb-uart";
 660                         reg = <0x01c28400 0x400>;
 661                         interrupts = <2>;
 662                         reg-shift = <2>;
 663                         reg-io-width = <4>;
 664                         clocks = <&ccu CLK_APB1_UART1>;
 665                         status = "disabled";
 666                 };
 667
 668                 uart2: serial@1c28800 {
 669                         compatible = "snps,dw-apb-uart";
 670                         reg = <0x01c28800 0x400>;
 671                         interrupts = <3>;
 672                         reg-shift = <2>;
 673                         reg-io-width = <4>;
 674                         clocks = <&ccu CLK_APB1_UART2>;
 675                         status = "disabled";
 676                 };
 677
 678                 uart3: serial@1c28c00 {
 679                         compatible = "snps,dw-apb-uart";
 680                         reg = <0x01c28c00 0x400>;
 681                         interrupts = <4>;
 682                         reg-shift = <2>;
 683                         reg-io-width = <4>;
 684                         clocks = <&ccu CLK_APB1_UART3>;
 685                         status = "disabled";
 686                 };
 687
 688                 i2c0: i2c@1c2ac00 {
 689                         compatible = "allwinner,sun4i-a10-i2c";
 690                         reg = <0x01c2ac00 0x400>;
 691                         interrupts = <7>;
 692                         clocks = <&ccu CLK_APB1_I2C0>;
 693                         pinctrl-names = "default";
 694                         pinctrl-0 = <&i2c0_pins>;
 695                         status = "disabled";
 696                         #address-cells = <1>;
 697                         #size-cells = <0>;
 698                 };
 699
 700                 i2c1: i2c@1c2b000 {
 701                         compatible = "allwinner,sun4i-a10-i2c";
 702                         reg = <0x01c2b000 0x400>;
 703                         interrupts = <8>;
 704                         clocks = <&ccu CLK_APB1_I2C1>;
 705                         pinctrl-names = "default";
 706                         pinctrl-0 = <&i2c1_pins>;
 707                         status = "disabled";
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                 };
 711
 712                 i2c2: i2c@1c2b400 {
 713                         compatible = "allwinner,sun4i-a10-i2c";
 714                         reg = <0x01c2b400 0x400>;
 715                         interrupts = <9>;
 716                         clocks = <&ccu CLK_APB1_I2C2>;
 717                         pinctrl-names = "default";
 718                         pinctrl-0 = <&i2c2_pins>;
 719                         status = "disabled";
 720                         #address-cells = <1>;
 721                         #size-cells = <0>;
 722                 };
 723
 724                 timer@1c60000 {
 725                         compatible = "allwinner,sun5i-a13-hstimer";
 726                         reg = <0x01c60000 0x1000>;
 727                         interrupts = <82>, <83>;
 728                         clocks = <&ccu CLK_AHB_HSTIMER>;
 729                 };
 730
 731                 fe0: display-frontend@1e00000 {
 732                         compatible = "allwinner,sun5i-a13-display-frontend";
 733                         reg = <0x01e00000 0x20000>;
 734                         interrupts = <47>;
 735                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
 736                                  <&ccu CLK_DRAM_DE_FE>;
 737                         clock-names = "ahb", "mod",
 738                                       "ram";
 739                         resets = <&ccu RST_DE_FE>;
 740                         interconnects = <&mbus 19>;
 741                         interconnect-names = "dma-mem";
 742                         status = "disabled";
 743
 744                         ports {
 745                                 #address-cells = <1>;
 746                                 #size-cells = <0>;
 747
 748                                 fe0_out: port@1 {
 749                                         reg = <1>;
 750
 751                                         fe0_out_be0: endpoint {
 752                                                 remote-endpoint = <&be0_in_fe0>;
 753                                         };
 754                                 };
 755                         };
 756                 };
 757
 758                 be0: display-backend@1e60000 {
 759                         compatible = "allwinner,sun5i-a13-display-backend";
 760                         reg = <0x01e60000 0x10000>;
 761                         interrupts = <47>;
 762                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
 763                                  <&ccu CLK_DRAM_DE_BE>;
 764                         clock-names = "ahb", "mod",
 765                                       "ram";
 766                         resets = <&ccu RST_DE_BE>;
 767                         interconnects = <&mbus 18>;
 768                         interconnect-names = "dma-mem";
 769                         status = "disabled";
 770
 771                         assigned-clocks = <&ccu CLK_DE_BE>;
 772                         assigned-clock-rates = <300000000>;
 773
 774                         ports {
 775                                 #address-cells = <1>;
 776                                 #size-cells = <0>;
 777
 778                                 be0_in: port@0 {
 779                                         reg = <0>;
 780
 781                                         be0_in_fe0: endpoint {
 782                                                 remote-endpoint = <&fe0_out_be0>;
 783                                         };
 784                                 };
 785
 786                                 be0_out: port@1 {
 787                                         reg = <1>;
 788
 789                                         be0_out_tcon0: endpoint {
 790                                                 remote-endpoint = <&tcon0_in_be0>;
 791                                         };
 792                                 };
 793                         };
 794                 };
 795         };
 796 };