arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/clock/sun5i-ccu.h>
  48 #include <dt-bindings/dma/sun4i-a10.h>
  49 #include <dt-bindings/reset/sun5i-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&intc>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a8";
  61                         reg = <0x0>;
  62                         clocks = <&ccu CLK_CPU>;
  63                 };
  64         };
  65
  66         chosen {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 framebuffer@0 {
  72                         compatible = "allwinner,simple-framebuffer",
  73                                      "simple-framebuffer";
  74                         allwinner,pipeline = "de_be0-lcd0";
  75                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  76                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  77                         status = "disabled";
  78                 };
  79
  80                 framebuffer@1 {
  81                         compatible = "allwinner,simple-framebuffer",
  82                                      "simple-framebuffer";
  83                         allwinner,pipeline = "de_be0-lcd0-tve0";
  84                         clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
  85                                  <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  86                                  <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
  87                         status = "disabled";
  88                 };
  89         };
  90
  91         clocks {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 osc24M: clk@1c20050 {
  97                         #clock-cells = <0>;
  98                         compatible = "fixed-clock";
  99                         clock-frequency = <24000000>;
 100                         clock-output-names = "osc24M";
 101                 };
 102
 103                 osc32k: clk@0 {
 104                         #clock-cells = <0>;
 105                         compatible = "fixed-clock";
 106                         clock-frequency = <32768>;
 107                         clock-output-names = "osc32k";
 108                 };
 109         };
 110
 111         reserved-memory {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 ranges;
 115
 116                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 117                 cma_pool: cma@4a000000 {
 118                         compatible = "shared-dma-pool";
 119                         size = <0x6000000>;
 120                         alloc-ranges = <0x4a000000 0x6000000>;
 121                         reusable;
 122                         linux,cma-default;
 123                 };
 124         };
 125
 126         soc@1c00000 {
 127                 compatible = "simple-bus";
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 ranges;
 131
 132                 system-control@1c00000 {
 133                         compatible = "allwinner,sun5i-a13-system-control";
 134                         reg = <0x01c00000 0x30>;
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         ranges;
 138
 139                         sram_a: sram@0 {
 140                                 compatible = "mmio-sram";
 141                                 reg = <0x00000000 0xc000>;
 142                                 #address-cells = <1>;
 143                                 #size-cells = <1>;
 144                                 ranges = <0 0x00000000 0xc000>;
 145
 146                                 emac_sram: sram-section@8000 {
 147                                         compatible = "allwinner,sun5i-a13-sram-a3-a4",
 148                                                      "allwinner,sun4i-a10-sram-a3-a4";
 149                                         reg = <0x8000 0x4000>;
 150                                         status = "disabled";
 151                                 };
 152                         };
 153
 154                         sram_d: sram@10000 {
 155                                 compatible = "mmio-sram";
 156                                 reg = <0x00010000 0x1000>;
 157                                 #address-cells = <1>;
 158                                 #size-cells = <1>;
 159                                 ranges = <0 0x00010000 0x1000>;
 160
 161                                 otg_sram: sram-section@0 {
 162                                         compatible = "allwinner,sun5i-a13-sram-d",
 163                                                      "allwinner,sun4i-a10-sram-d";
 164                                         reg = <0x0000 0x1000>;
 165                                         status = "disabled";
 166                                 };
 167                         };
 168
 169                         sram_c: sram@1d00000 {
 170                                 compatible = "mmio-sram";
 171                                 reg = <0x01d00000 0xd0000>;
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 ranges = <0 0x01d00000 0xd0000>;
 175
 176                                 ve_sram: sram-section@0 {
 177                                         compatible = "allwinner,sun5i-a13-sram-c1",
 178                                                      "allwinner,sun4i-a10-sram-c1";
 179                                         reg = <0x000000 0x80000>;
 180                                 };
 181                         };
 182                 };
 183
 184                 dma: dma-controller@1c02000 {
 185                         compatible = "allwinner,sun4i-a10-dma";
 186                         reg = <0x01c02000 0x1000>;
 187                         interrupts = <27>;
 188                         clocks = <&ccu CLK_AHB_DMA>;
 189                         #dma-cells = <2>;
 190                 };
 191
 192                 nfc: nand@1c03000 {
 193                         compatible = "allwinner,sun4i-a10-nand";
 194                         reg = <0x01c03000 0x1000>;
 195                         interrupts = <37>;
 196                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 197                         clock-names = "ahb", "mod";
 198                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 199                         dma-names = "rxtx";
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                 };
 204
 205                 spi0: spi@1c05000 {
 206                         compatible = "allwinner,sun4i-a10-spi";
 207                         reg = <0x01c05000 0x1000>;
 208                         interrupts = <10>;
 209                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 210                         clock-names = "ahb", "mod";
 211                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 212                                <&dma SUN4I_DMA_DEDICATED 26>;
 213                         dma-names = "rx", "tx";
 214                         status = "disabled";
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                 };
 218
 219                 spi1: spi@1c06000 {
 220                         compatible = "allwinner,sun4i-a10-spi";
 221                         reg = <0x01c06000 0x1000>;
 222                         interrupts = <11>;
 223                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 224                         clock-names = "ahb", "mod";
 225                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 226                                <&dma SUN4I_DMA_DEDICATED 8>;
 227                         dma-names = "rx", "tx";
 228                         status = "disabled";
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                 };
 232
 233                 tve0: tv-encoder@1c0a000 {
 234                         compatible = "allwinner,sun4i-a10-tv-encoder";
 235                         reg = <0x01c0a000 0x1000>;
 236                         clocks = <&ccu CLK_AHB_TVE>;
 237                         resets = <&ccu RST_TVE>;
 238                         status = "disabled";
 239
 240                         port {
 241                                 #address-cells = <1>;
 242                                 #size-cells = <0>;
 243
 244                                 tve0_in_tcon0: endpoint@0 {
 245                                         reg = <0>;
 246                                         remote-endpoint = <&tcon0_out_tve0>;
 247                                 };
 248                         };
 249                 };
 250
 251                 emac: ethernet@1c0b000 {
 252                         compatible = "allwinner,sun4i-a10-emac";
 253                         reg = <0x01c0b000 0x1000>;
 254                         interrupts = <55>;
 255                         clocks = <&ccu CLK_AHB_EMAC>;
 256                         allwinner,sram = <&emac_sram 1>;
 257                         status = "disabled";
 258                 };
 259
 260                 mdio: mdio@1c0b080 {
 261                         compatible = "allwinner,sun4i-a10-mdio";
 262                         reg = <0x01c0b080 0x14>;
 263                         status = "disabled";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                 };
 267
 268                 tcon0: lcd-controller@1c0c000 {
 269                         compatible = "allwinner,sun5i-a13-tcon";
 270                         reg = <0x01c0c000 0x1000>;
 271                         interrupts = <44>;
 272                         resets = <&ccu RST_LCD>;
 273                         reset-names = "lcd";
 274                         clocks = <&ccu CLK_AHB_LCD>,
 275                                  <&ccu CLK_TCON_CH0>,
 276                                  <&ccu CLK_TCON_CH1>;
 277                         clock-names = "ahb",
 278                                       "tcon-ch0",
 279                                       "tcon-ch1";
 280                         clock-output-names = "tcon-pixel-clock";
 281                         status = "disabled";
 282
 283                         ports {
 284                                 #address-cells = <1>;
 285                                 #size-cells = <0>;
 286
 287                                 tcon0_in: port@0 {
 288                                         #address-cells = <1>;
 289                                         #size-cells = <0>;
 290                                         reg = <0>;
 291
 292                                         tcon0_in_be0: endpoint@0 {
 293                                                 reg = <0>;
 294                                                 remote-endpoint = <&be0_out_tcon0>;
 295                                         };
 296                                 };
 297
 298                                 tcon0_out: port@1 {
 299                                         #address-cells = <1>;
 300                                         #size-cells = <0>;
 301                                         reg = <1>;
 302
 303                                         tcon0_out_tve0: endpoint@1 {
 304                                                 reg = <1>;
 305                                                 remote-endpoint = <&tve0_in_tcon0>;
 306                                                 allwinner,tcon-channel = <1>;
 307                                         };
 308                                 };
 309                         };
 310                 };
 311
 312                 video-codec@1c0e000 {
 313                         compatible = "allwinner,sun5i-a13-video-engine";
 314                         reg = <0x01c0e000 0x1000>;
 315                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 316                                  <&ccu CLK_DRAM_VE>;
 317                         clock-names = "ahb", "mod", "ram";
 318                         resets = <&ccu RST_VE>;
 319                         interrupts = <53>;
 320                         allwinner,sram = <&ve_sram 1>;
 321                 };
 322
 323                 mmc0: mmc@1c0f000 {
 324                         compatible = "allwinner,sun5i-a13-mmc";
 325                         reg = <0x01c0f000 0x1000>;
 326                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 327                         clock-names = "ahb", "mmc";
 328                         interrupts = <32>;
 329                         status = "disabled";
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                 };
 333
 334                 mmc1: mmc@1c10000 {
 335                         compatible = "allwinner,sun5i-a13-mmc";
 336                         reg = <0x01c10000 0x1000>;
 337                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 338                         clock-names = "ahb", "mmc";
 339                         interrupts = <33>;
 340                         status = "disabled";
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                 };
 344
 345                 mmc2: mmc@1c11000 {
 346                         compatible = "allwinner,sun5i-a13-mmc";
 347                         reg = <0x01c11000 0x1000>;
 348                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 349                         clock-names = "ahb", "mmc";
 350                         interrupts = <34>;
 351                         status = "disabled";
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                 };
 355
 356                 usb_otg: usb@1c13000 {
 357                         compatible = "allwinner,sun4i-a10-musb";
 358                         reg = <0x01c13000 0x0400>;
 359                         clocks = <&ccu CLK_AHB_OTG>;
 360                         interrupts = <38>;
 361                         interrupt-names = "mc";
 362                         phys = <&usbphy 0>;
 363                         phy-names = "usb";
 364                         extcon = <&usbphy 0>;
 365                         allwinner,sram = <&otg_sram 1>;
 366                         status = "disabled";
 367                 };
 368
 369                 usbphy: phy@1c13400 {
 370                         #phy-cells = <1>;
 371                         compatible = "allwinner,sun5i-a13-usb-phy";
 372                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 373                         reg-names = "phy_ctrl", "pmu1";
 374                         clocks = <&ccu CLK_USB_PHY0>;
 375                         clock-names = "usb_phy";
 376                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
 377                         reset-names = "usb0_reset", "usb1_reset";
 378                         status = "disabled";
 379                 };
 380
 381                 ehci0: usb@1c14000 {
 382                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 383                         reg = <0x01c14000 0x100>;
 384                         interrupts = <39>;
 385                         clocks = <&ccu CLK_AHB_EHCI>;
 386                         phys = <&usbphy 1>;
 387                         phy-names = "usb";
 388                         status = "disabled";
 389                 };
 390
 391                 ohci0: usb@1c14400 {
 392                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 393                         reg = <0x01c14400 0x100>;
 394                         interrupts = <40>;
 395                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
 396                         phys = <&usbphy 1>;
 397                         phy-names = "usb";
 398                         status = "disabled";
 399                 };
 400
 401                 crypto: crypto-engine@1c15000 {
 402                         compatible = "allwinner,sun5i-a13-crypto",
 403                                      "allwinner,sun4i-a10-crypto";
 404                         reg = <0x01c15000 0x1000>;
 405                         interrupts = <54>;
 406                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 407                         clock-names = "ahb", "mod";
 408                 };
 409
 410                 spi2: spi@1c17000 {
 411                         compatible = "allwinner,sun4i-a10-spi";
 412                         reg = <0x01c17000 0x1000>;
 413                         interrupts = <12>;
 414                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 415                         clock-names = "ahb", "mod";
 416                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 417                                <&dma SUN4I_DMA_DEDICATED 28>;
 418                         dma-names = "rx", "tx";
 419                         status = "disabled";
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                 };
 423
 424                 ccu: clock@1c20000 {
 425                         reg = <0x01c20000 0x400>;
 426                         clocks = <&osc24M>, <&osc32k>;
 427                         clock-names = "hosc", "losc";
 428                         #clock-cells = <1>;
 429                         #reset-cells = <1>;
 430                 };
 431
 432                 intc: interrupt-controller@1c20400 {
 433                         compatible = "allwinner,sun4i-a10-ic";
 434                         reg = <0x01c20400 0x400>;
 435                         interrupt-controller;
 436                         #interrupt-cells = <1>;
 437                 };
 438
 439                 pio: pinctrl@1c20800 {
 440                         reg = <0x01c20800 0x400>;
 441                         interrupts = <28>;
 442                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 443                         clock-names = "apb", "hosc", "losc";
 444                         gpio-controller;
 445                         interrupt-controller;
 446                         #interrupt-cells = <3>;
 447                         #gpio-cells = <3>;
 448
 449                         emac_pins_a: emac0@0 {
 450                                 pins = "PD6", "PD7", "PD10",
 451                                        "PD11", "PD12", "PD13", "PD14",
 452                                        "PD15", "PD18", "PD19", "PD20",
 453                                        "PD21", "PD22", "PD23", "PD24",
 454                                        "PD25", "PD26", "PD27";
 455                                 function = "emac";
 456                         };
 457
 458                         i2c0_pins_a: i2c0@0 {
 459                                 pins = "PB0", "PB1";
 460                                 function = "i2c0";
 461                         };
 462
 463                         i2c1_pins_a: i2c1@0 {
 464                                 pins = "PB15", "PB16";
 465                                 function = "i2c1";
 466                         };
 467
 468                         i2c2_pins_a: i2c2@0 {
 469                                 pins = "PB17", "PB18";
 470                                 function = "i2c2";
 471                         };
 472
 473                         ir0_rx_pins_a: ir0@0 {
 474                                 pins = "PB4";
 475                                 function = "ir0";
 476                         };
 477
 478                         lcd_rgb565_pins: lcd_rgb565@0 {
 479                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 480                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 481                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 482                                                  "PD24", "PD25", "PD26", "PD27";
 483                                 function = "lcd0";
 484                         };
 485
 486                         lcd_rgb666_pins: lcd_rgb666@0 {
 487                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 488                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 489                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 490                                        "PD24", "PD25", "PD26", "PD27";
 491                                 function = "lcd0";
 492                         };
 493
 494                         mmc0_pins_a: mmc0@0 {
 495                                 pins = "PF0", "PF1", "PF2", "PF3",
 496                                        "PF4", "PF5";
 497                                 function = "mmc0";
 498                                 drive-strength = <30>;
 499                                 bias-pull-up;
 500                         };
 501
 502                         mmc2_pins_a: mmc2@0 {
 503                                 pins = "PC6", "PC7", "PC8", "PC9",
 504                                        "PC10", "PC11", "PC12", "PC13",
 505                                        "PC14", "PC15";
 506                                 function = "mmc2";
 507                                 drive-strength = <30>;
 508                                 bias-pull-up;
 509                         };
 510
 511                         mmc2_4bit_pins_a: mmc2-4bit@0 {
 512                                 pins = "PC6", "PC7", "PC8", "PC9",
 513                                        "PC10", "PC11";
 514                                 function = "mmc2";
 515                                 drive-strength = <30>;
 516                                 bias-pull-up;
 517                         };
 518
 519                         nand_pins_a: nand-base0@0 {
 520                                 pins = "PC0", "PC1", "PC2",
 521                                        "PC5", "PC8", "PC9", "PC10",
 522                                        "PC11", "PC12", "PC13", "PC14",
 523                                        "PC15";
 524                                 function = "nand0";
 525                         };
 526
 527                         nand_cs0_pins_a: nand-cs@0 {
 528                                 pins = "PC4";
 529                                 function = "nand0";
 530                         };
 531
 532                         nand_rb0_pins_a: nand-rb@0 {
 533                                 pins = "PC6";
 534                                 function = "nand0";
 535                         };
 536
 537                         spi2_pins_a: spi2@0 {
 538                                 pins = "PE1", "PE2", "PE3";
 539                                 function = "spi2";
 540                         };
 541
 542                         spi2_cs0_pins_a: spi2-cs0@0 {
 543                                 pins = "PE0";
 544                                 function = "spi2";
 545                         };
 546
 547                         uart1_pins_a: uart1@0 {
 548                                 pins = "PE10", "PE11";
 549                                 function = "uart1";
 550                         };
 551
 552                         uart1_pins_b: uart1@1 {
 553                                 pins = "PG3", "PG4";
 554                                 function = "uart1";
 555                         };
 556
 557                         uart2_pins_a: uart2@0 {
 558                                 pins = "PD2", "PD3";
 559                                 function = "uart2";
 560                         };
 561
 562                         uart2_cts_rts_pins_a: uart2-cts-rts@0 {
 563                                 pins = "PD4", "PD5";
 564                                 function = "uart2";
 565                         };
 566
 567                         uart3_pins_a: uart3@0 {
 568                                 pins = "PG9", "PG10";
 569                                 function = "uart3";
 570                         };
 571
 572                         uart3_cts_rts_pins_a: uart3-cts-rts@0 {
 573                                 pins = "PG11", "PG12";
 574                                 function = "uart3";
 575                         };
 576
 577                         pwm0_pins: pwm0 {
 578                                 pins = "PB2";
 579                                 function = "pwm";
 580                         };
 581                 };
 582
 583                 timer@1c20c00 {
 584                         compatible = "allwinner,sun4i-a10-timer";
 585                         reg = <0x01c20c00 0x90>;
 586                         interrupts = <22>;
 587                         clocks = <&ccu CLK_HOSC>;
 588                 };
 589
 590                 wdt: watchdog@1c20c90 {
 591                         compatible = "allwinner,sun4i-a10-wdt";
 592                         reg = <0x01c20c90 0x10>;
 593                 };
 594
 595                 ir0: ir@1c21800 {
 596                         compatible = "allwinner,sun4i-a10-ir";
 597                         clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
 598                         clock-names = "apb", "ir";
 599                         interrupts = <5>;
 600                         reg = <0x01c21800 0x40>;
 601                         status = "disabled";
 602                 };
 603
 604                 lradc: lradc@1c22800 {
 605                         compatible = "allwinner,sun4i-a10-lradc-keys";
 606                         reg = <0x01c22800 0x100>;
 607                         interrupts = <31>;
 608                         status = "disabled";
 609                 };
 610
 611                 codec: codec@1c22c00 {
 612                         #sound-dai-cells = <0>;
 613                         compatible = "allwinner,sun4i-a10-codec";
 614                         reg = <0x01c22c00 0x40>;
 615                         interrupts = <30>;
 616                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 617                         clock-names = "apb", "codec";
 618                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 619                                <&dma SUN4I_DMA_NORMAL 19>;
 620                         dma-names = "rx", "tx";
 621                         status = "disabled";
 622                 };
 623
 624                 sid: eeprom@1c23800 {
 625                         compatible = "allwinner,sun4i-a10-sid";
 626                         reg = <0x01c23800 0x10>;
 627                 };
 628
 629                 rtp: rtp@1c25000 {
 630                         compatible = "allwinner,sun5i-a13-ts";
 631                         reg = <0x01c25000 0x100>;
 632                         interrupts = <29>;
 633                         #thermal-sensor-cells = <0>;
 634                 };
 635
 636                 uart0: serial@1c28000 {
 637                         compatible = "snps,dw-apb-uart";
 638                         reg = <0x01c28000 0x400>;
 639                         interrupts = <1>;
 640                         reg-shift = <2>;
 641                         reg-io-width = <4>;
 642                         clocks = <&ccu CLK_APB1_UART0>;
 643                         status = "disabled";
 644                 };
 645
 646                 uart1: serial@1c28400 {
 647                         compatible = "snps,dw-apb-uart";
 648                         reg = <0x01c28400 0x400>;
 649                         interrupts = <2>;
 650                         reg-shift = <2>;
 651                         reg-io-width = <4>;
 652                         clocks = <&ccu CLK_APB1_UART1>;
 653                         status = "disabled";
 654                 };
 655
 656                 uart2: serial@1c28800 {
 657                         compatible = "snps,dw-apb-uart";
 658                         reg = <0x01c28800 0x400>;
 659                         interrupts = <3>;
 660                         reg-shift = <2>;
 661                         reg-io-width = <4>;
 662                         clocks = <&ccu CLK_APB1_UART2>;
 663                         status = "disabled";
 664                 };
 665
 666                 uart3: serial@1c28c00 {
 667                         compatible = "snps,dw-apb-uart";
 668                         reg = <0x01c28c00 0x400>;
 669                         interrupts = <4>;
 670                         reg-shift = <2>;
 671                         reg-io-width = <4>;
 672                         clocks = <&ccu CLK_APB1_UART3>;
 673                         status = "disabled";
 674                 };
 675
 676                 i2c0: i2c@1c2ac00 {
 677                         compatible = "allwinner,sun4i-a10-i2c";
 678                         reg = <0x01c2ac00 0x400>;
 679                         interrupts = <7>;
 680                         clocks = <&ccu CLK_APB1_I2C0>;
 681                         status = "disabled";
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684                 };
 685
 686                 i2c1: i2c@1c2b000 {
 687                         compatible = "allwinner,sun4i-a10-i2c";
 688                         reg = <0x01c2b000 0x400>;
 689                         interrupts = <8>;
 690                         clocks = <&ccu CLK_APB1_I2C1>;
 691                         status = "disabled";
 692                         #address-cells = <1>;
 693                         #size-cells = <0>;
 694                 };
 695
 696                 i2c2: i2c@1c2b400 {
 697                         compatible = "allwinner,sun4i-a10-i2c";
 698                         reg = <0x01c2b400 0x400>;
 699                         interrupts = <9>;
 700                         clocks = <&ccu CLK_APB1_I2C2>;
 701                         status = "disabled";
 702                         #address-cells = <1>;
 703                         #size-cells = <0>;
 704                 };
 705
 706                 timer@1c60000 {
 707                         compatible = "allwinner,sun5i-a13-hstimer";
 708                         reg = <0x01c60000 0x1000>;
 709                         interrupts = <82>, <83>;
 710                         clocks = <&ccu CLK_AHB_HSTIMER>;
 711                 };
 712
 713                 fe0: display-frontend@1e00000 {
 714                         compatible = "allwinner,sun5i-a13-display-frontend";
 715                         reg = <0x01e00000 0x20000>;
 716                         interrupts = <47>;
 717                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
 718                                  <&ccu CLK_DRAM_DE_FE>;
 719                         clock-names = "ahb", "mod",
 720                                       "ram";
 721                         resets = <&ccu RST_DE_FE>;
 722                         status = "disabled";
 723
 724                         ports {
 725                                 #address-cells = <1>;
 726                                 #size-cells = <0>;
 727
 728                                 fe0_out: port@1 {
 729                                         #address-cells = <1>;
 730                                         #size-cells = <0>;
 731                                         reg = <1>;
 732
 733                                         fe0_out_be0: endpoint@0 {
 734                                                 reg = <0>;
 735                                                 remote-endpoint = <&be0_in_fe0>;
 736                                         };
 737                                 };
 738                         };
 739                 };
 740
 741                 be0: display-backend@1e60000 {
 742                         compatible = "allwinner,sun5i-a13-display-backend";
 743                         reg = <0x01e60000 0x10000>;
 744                         interrupts = <47>;
 745                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
 746                                  <&ccu CLK_DRAM_DE_BE>;
 747                         clock-names = "ahb", "mod",
 748                                       "ram";
 749                         resets = <&ccu RST_DE_BE>;
 750                         status = "disabled";
 751
 752                         assigned-clocks = <&ccu CLK_DE_BE>;
 753                         assigned-clock-rates = <300000000>;
 754
 755                         ports {
 756                                 #address-cells = <1>;
 757                                 #size-cells = <0>;
 758
 759                                 be0_in: port@0 {
 760                                         #address-cells = <1>;
 761                                         #size-cells = <0>;
 762                                         reg = <0>;
 763
 764                                         be0_in_fe0: endpoint@0 {
 765                                                 reg = <0>;
 766                                                 remote-endpoint = <&fe0_out_be0>;
 767                                         };
 768                                 };
 769
 770                                 be0_out: port@1 {
 771                                         #address-cells = <1>;
 772                                         #size-cells = <0>;
 773                                         reg = <1>;
 774
 775                                         be0_out_tcon0: endpoint@0 {
 776                                                 reg = <0>;
 777                                                 remote-endpoint = <&tcon0_in_be0>;
 778                                         };
 779                                 };
 780                         };
 781                 };
 782         };
 783 };