arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/sun5i-ccu.h>
  46 #include <dt-bindings/dma/sun4i-a10.h>
  47 #include <dt-bindings/reset/sun5i-ccu.h>
  48
  49 / {
  50         interrupt-parent = <&intc>;
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a8";
  61                         reg = <0x0>;
  62                         clocks = <&ccu CLK_CPU>;
  63                 };
  64         };
  65
  66         chosen {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 framebuffer-lcd0 {
  72                         compatible = "allwinner,simple-framebuffer",
  73                                      "simple-framebuffer";
  74                         allwinner,pipeline = "de_be0-lcd0";
  75                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  76                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  77                         status = "disabled";
  78                 };
  79
  80                 framebuffer-lcd0-tve0 {
  81                         compatible = "allwinner,simple-framebuffer",
  82                                      "simple-framebuffer";
  83                         allwinner,pipeline = "de_be0-lcd0-tve0";
  84                         clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
  85                                  <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  86                                  <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
  87                         status = "disabled";
  88                 };
  89         };
  90
  91         clocks {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 osc24M: clk-24M {
  97                         #clock-cells = <0>;
  98                         compatible = "fixed-clock";
  99                         clock-frequency = <24000000>;
 100                         clock-output-names = "osc24M";
 101                 };
 102
 103                 osc32k: clk-32k {
 104                         #clock-cells = <0>;
 105                         compatible = "fixed-clock";
 106                         clock-frequency = <32768>;
 107                         clock-output-names = "osc32k";
 108                 };
 109         };
 110
 111         reserved-memory {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 ranges;
 115
 116                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 117                 default-pool {
 118                         compatible = "shared-dma-pool";
 119                         size = <0x6000000>;
 120                         alloc-ranges = <0x4a000000 0x6000000>;
 121                         reusable;
 122                         linux,cma-default;
 123                 };
 124         };
 125
 126         soc {
 127                 compatible = "simple-bus";
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 dma-ranges;
 131                 ranges;
 132
 133                 system-control@1c00000 {
 134                         compatible = "allwinner,sun5i-a13-system-control";
 135                         reg = <0x01c00000 0x30>;
 136                         #address-cells = <1>;
 137                         #size-cells = <1>;
 138                         ranges;
 139
 140                         sram_a: sram@0 {
 141                                 compatible = "mmio-sram";
 142                                 reg = <0x00000000 0xc000>;
 143                                 #address-cells = <1>;
 144                                 #size-cells = <1>;
 145                                 ranges = <0 0x00000000 0xc000>;
 146
 147                                 emac_sram: sram-section@8000 {
 148                                         compatible = "allwinner,sun5i-a13-sram-a3-a4",
 149                                                      "allwinner,sun4i-a10-sram-a3-a4";
 150                                         reg = <0x8000 0x4000>;
 151                                         status = "disabled";
 152                                 };
 153                         };
 154
 155                         sram_d: sram@10000 {
 156                                 compatible = "mmio-sram";
 157                                 reg = <0x00010000 0x1000>;
 158                                 #address-cells = <1>;
 159                                 #size-cells = <1>;
 160                                 ranges = <0 0x00010000 0x1000>;
 161
 162                                 otg_sram: sram-section@0 {
 163                                         compatible = "allwinner,sun5i-a13-sram-d",
 164                                                      "allwinner,sun4i-a10-sram-d";
 165                                         reg = <0x0000 0x1000>;
 166                                         status = "disabled";
 167                                 };
 168                         };
 169
 170                         sram_c: sram@1d00000 {
 171                                 compatible = "mmio-sram";
 172                                 reg = <0x01d00000 0xd0000>;
 173                                 #address-cells = <1>;
 174                                 #size-cells = <1>;
 175                                 ranges = <0 0x01d00000 0xd0000>;
 176
 177                                 ve_sram: sram-section@0 {
 178                                         compatible = "allwinner,sun5i-a13-sram-c1",
 179                                                      "allwinner,sun4i-a10-sram-c1";
 180                                         reg = <0x000000 0x80000>;
 181                                 };
 182                         };
 183                 };
 184
 185                 mbus: dram-controller@1c01000 {
 186                         compatible = "allwinner,sun5i-a13-mbus";
 187                         reg = <0x01c01000 0x1000>;
 188                         clocks = <&ccu CLK_MBUS>;
 189                         dma-ranges = <0x00000000 0x40000000 0x20000000>;
 190                         #interconnect-cells = <1>;
 191                 };
 192
 193                 dma: dma-controller@1c02000 {
 194                         compatible = "allwinner,sun4i-a10-dma";
 195                         reg = <0x01c02000 0x1000>;
 196                         interrupts = <27>;
 197                         clocks = <&ccu CLK_AHB_DMA>;
 198                         #dma-cells = <2>;
 199                 };
 200
 201                 nfc: nand-controller@1c03000 {
 202                         compatible = "allwinner,sun4i-a10-nand";
 203                         reg = <0x01c03000 0x1000>;
 204                         interrupts = <37>;
 205                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 206                         clock-names = "ahb", "mod";
 207                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 208                         dma-names = "rxtx";
 209                         status = "disabled";
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                 };
 213
 214                 spi0: spi@1c05000 {
 215                         compatible = "allwinner,sun4i-a10-spi";
 216                         reg = <0x01c05000 0x1000>;
 217                         interrupts = <10>;
 218                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 219                         clock-names = "ahb", "mod";
 220                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 221                                <&dma SUN4I_DMA_DEDICATED 26>;
 222                         dma-names = "rx", "tx";
 223                         status = "disabled";
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                 };
 227
 228                 spi1: spi@1c06000 {
 229                         compatible = "allwinner,sun4i-a10-spi";
 230                         reg = <0x01c06000 0x1000>;
 231                         interrupts = <11>;
 232                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 233                         clock-names = "ahb", "mod";
 234                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 235                                <&dma SUN4I_DMA_DEDICATED 8>;
 236                         dma-names = "rx", "tx";
 237                         status = "disabled";
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                 };
 241
 242                 tve0: tv-encoder@1c0a000 {
 243                         compatible = "allwinner,sun4i-a10-tv-encoder";
 244                         reg = <0x01c0a000 0x1000>;
 245                         clocks = <&ccu CLK_AHB_TVE>;
 246                         resets = <&ccu RST_TVE>;
 247                         status = "disabled";
 248
 249                         port {
 250
 251                                 tve0_in_tcon0: endpoint {
 252                                         remote-endpoint = <&tcon0_out_tve0>;
 253                                 };
 254                         };
 255                 };
 256
 257                 emac: ethernet@1c0b000 {
 258                         compatible = "allwinner,sun4i-a10-emac";
 259                         reg = <0x01c0b000 0x1000>;
 260                         interrupts = <55>;
 261                         clocks = <&ccu CLK_AHB_EMAC>;
 262                         allwinner,sram = <&emac_sram 1>;
 263                         status = "disabled";
 264                 };
 265
 266                 mdio: mdio@1c0b080 {
 267                         compatible = "allwinner,sun4i-a10-mdio";
 268                         reg = <0x01c0b080 0x14>;
 269                         status = "disabled";
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                 };
 273
 274                 tcon0: lcd-controller@1c0c000 {
 275                         compatible = "allwinner,sun5i-a13-tcon";
 276                         reg = <0x01c0c000 0x1000>;
 277                         interrupts = <44>;
 278                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 279                         resets = <&ccu RST_LCD>;
 280                         reset-names = "lcd";
 281                         clocks = <&ccu CLK_AHB_LCD>,
 282                                  <&ccu CLK_TCON_CH0>,
 283                                  <&ccu CLK_TCON_CH1>;
 284                         clock-names = "ahb",
 285                                       "tcon-ch0",
 286                                       "tcon-ch1";
 287                         clock-output-names = "tcon-pixel-clock";
 288                         #clock-cells = <0>;
 289                         status = "disabled";
 290
 291                         ports {
 292                                 #address-cells = <1>;
 293                                 #size-cells = <0>;
 294
 295                                 tcon0_in: port@0 {
 296                                         reg = <0>;
 297
 298                                         tcon0_in_be0: endpoint {
 299                                                 remote-endpoint = <&be0_out_tcon0>;
 300                                         };
 301                                 };
 302
 303                                 tcon0_out: port@1 {
 304                                         #address-cells = <1>;
 305                                         #size-cells = <0>;
 306                                         reg = <1>;
 307
 308                                         tcon0_out_tve0: endpoint@1 {
 309                                                 reg = <1>;
 310                                                 remote-endpoint = <&tve0_in_tcon0>;
 311                                                 allwinner,tcon-channel = <1>;
 312                                         };
 313                                 };
 314                         };
 315                 };
 316
 317                 video-codec@1c0e000 {
 318                         compatible = "allwinner,sun5i-a13-video-engine";
 319                         reg = <0x01c0e000 0x1000>;
 320                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 321                                  <&ccu CLK_DRAM_VE>;
 322                         clock-names = "ahb", "mod", "ram";
 323                         resets = <&ccu RST_VE>;
 324                         interrupts = <53>;
 325                         allwinner,sram = <&ve_sram 1>;
 326                 };
 327
 328                 mmc0: mmc@1c0f000 {
 329                         compatible = "allwinner,sun5i-a13-mmc";
 330                         reg = <0x01c0f000 0x1000>;
 331                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 332                         clock-names = "ahb", "mmc";
 333                         interrupts = <32>;
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&mmc0_pins>;
 336                         status = "disabled";
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                 };
 340
 341                 mmc1: mmc@1c10000 {
 342                         compatible = "allwinner,sun5i-a13-mmc";
 343                         reg = <0x01c10000 0x1000>;
 344                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 345                         clock-names = "ahb", "mmc";
 346                         interrupts = <33>;
 347                         status = "disabled";
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                 };
 351
 352                 mmc2: mmc@1c11000 {
 353                         compatible = "allwinner,sun5i-a13-mmc";
 354                         reg = <0x01c11000 0x1000>;
 355                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 356                         clock-names = "ahb", "mmc";
 357                         interrupts = <34>;
 358                         status = "disabled";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                 };
 362
 363                 usb_otg: usb@1c13000 {
 364                         compatible = "allwinner,sun4i-a10-musb";
 365                         reg = <0x01c13000 0x0400>;
 366                         clocks = <&ccu CLK_AHB_OTG>;
 367                         interrupts = <38>;
 368                         interrupt-names = "mc";
 369                         phys = <&usbphy 0>;
 370                         phy-names = "usb";
 371                         extcon = <&usbphy 0>;
 372                         allwinner,sram = <&otg_sram 1>;
 373                         dr_mode = "otg";
 374                         status = "disabled";
 375                 };
 376
 377                 usbphy: phy@1c13400 {
 378                         #phy-cells = <1>;
 379                         compatible = "allwinner,sun5i-a13-usb-phy";
 380                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
 381                         reg-names = "phy_ctrl", "pmu1";
 382                         clocks = <&ccu CLK_USB_PHY0>;
 383                         clock-names = "usb_phy";
 384                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
 385                         reset-names = "usb0_reset", "usb1_reset";
 386                         status = "disabled";
 387                 };
 388
 389                 ehci0: usb@1c14000 {
 390                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 391                         reg = <0x01c14000 0x100>;
 392                         interrupts = <39>;
 393                         clocks = <&ccu CLK_AHB_EHCI>;
 394                         phys = <&usbphy 1>;
 395                         phy-names = "usb";
 396                         status = "disabled";
 397                 };
 398
 399                 ohci0: usb@1c14400 {
 400                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 401                         reg = <0x01c14400 0x100>;
 402                         interrupts = <40>;
 403                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
 404                         phys = <&usbphy 1>;
 405                         phy-names = "usb";
 406                         status = "disabled";
 407                 };
 408
 409                 crypto: crypto-engine@1c15000 {
 410                         compatible = "allwinner,sun5i-a13-crypto",
 411                                      "allwinner,sun4i-a10-crypto";
 412                         reg = <0x01c15000 0x1000>;
 413                         interrupts = <54>;
 414                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 415                         clock-names = "ahb", "mod";
 416                 };
 417
 418                 spi2: spi@1c17000 {
 419                         compatible = "allwinner,sun4i-a10-spi";
 420                         reg = <0x01c17000 0x1000>;
 421                         interrupts = <12>;
 422                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 423                         clock-names = "ahb", "mod";
 424                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 425                                <&dma SUN4I_DMA_DEDICATED 28>;
 426                         dma-names = "rx", "tx";
 427                         status = "disabled";
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                 };
 431
 432                 ccu: clock@1c20000 {
 433                         reg = <0x01c20000 0x400>;
 434                         clocks = <&osc24M>, <&osc32k>;
 435                         clock-names = "hosc", "losc";
 436                         #clock-cells = <1>;
 437                         #reset-cells = <1>;
 438                 };
 439
 440                 intc: interrupt-controller@1c20400 {
 441                         compatible = "allwinner,sun4i-a10-ic";
 442                         reg = <0x01c20400 0x400>;
 443                         interrupt-controller;
 444                         #interrupt-cells = <1>;
 445                 };
 446
 447                 pio: pinctrl@1c20800 {
 448                         reg = <0x01c20800 0x400>;
 449                         interrupts = <28>;
 450                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 451                         clock-names = "apb", "hosc", "losc";
 452                         gpio-controller;
 453                         interrupt-controller;
 454                         #interrupt-cells = <3>;
 455                         #gpio-cells = <3>;
 456
 457                         emac_pd_pins: emac-pd-pins {
 458                                 pins = "PD6", "PD7", "PD10",
 459                                        "PD11", "PD12", "PD13", "PD14",
 460                                        "PD15", "PD18", "PD19", "PD20",
 461                                        "PD21", "PD22", "PD23", "PD24",
 462                                        "PD25", "PD26", "PD27";
 463                                 function = "emac";
 464                         };
 465
 466                         i2c0_pins: i2c0-pins {
 467                                 pins = "PB0", "PB1";
 468                                 function = "i2c0";
 469                         };
 470
 471                         i2c1_pins: i2c1-pins {
 472                                 pins = "PB15", "PB16";
 473                                 function = "i2c1";
 474                         };
 475
 476                         i2c2_pins: i2c2-pins {
 477                                 pins = "PB17", "PB18";
 478                                 function = "i2c2";
 479                         };
 480
 481                         ir0_rx_pin: ir0-rx-pin {
 482                                 pins = "PB4";
 483                                 function = "ir0";
 484                         };
 485
 486                         lcd_rgb565_pins: lcd-rgb565-pins {
 487                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 488                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 489                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 490                                                  "PD24", "PD25", "PD26", "PD27";
 491                                 function = "lcd0";
 492                         };
 493
 494                         lcd_rgb666_pins: lcd-rgb666-pins {
 495                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 496                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 497                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 498                                        "PD24", "PD25", "PD26", "PD27";
 499                                 function = "lcd0";
 500                         };
 501
 502                         mmc0_pins: mmc0-pins {
 503                                 pins = "PF0", "PF1", "PF2", "PF3",
 504                                        "PF4", "PF5";
 505                                 function = "mmc0";
 506                                 drive-strength = <30>;
 507                                 bias-pull-up;
 508                         };
 509
 510                         mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
 511                                 pins = "PC6", "PC7", "PC8", "PC9",
 512                                        "PC10", "PC11";
 513                                 function = "mmc2";
 514                                 drive-strength = <30>;
 515                                 bias-pull-up;
 516                         };
 517
 518                         mmc2_8bit_pins: mmc2-8bit-pins {
 519                                 pins = "PC6", "PC7", "PC8", "PC9",
 520                                        "PC10", "PC11", "PC12", "PC13",
 521                                        "PC14", "PC15";
 522                                 function = "mmc2";
 523                                 drive-strength = <30>;
 524                                 bias-pull-up;
 525                         };
 526
 527                         nand_pins: nand-pins {
 528                                 pins = "PC0", "PC1", "PC2",
 529                                        "PC5", "PC8", "PC9", "PC10",
 530                                        "PC11", "PC12", "PC13", "PC14",
 531                                        "PC15";
 532                                 function = "nand0";
 533                         };
 534
 535                         nand_cs0_pin: nand-cs0-pin {
 536                                 pins = "PC4";
 537                                 function = "nand0";
 538                         };
 539
 540                         nand_rb0_pin: nand-rb0-pin {
 541                                 pins = "PC6";
 542                                 function = "nand0";
 543                         };
 544
 545                         pwm0_pin: pwm0-pin {
 546                                 pins = "PB2";
 547                                 function = "pwm";
 548                         };
 549
 550                         spi2_pe_pins: spi2-pe-pins {
 551                                 pins = "PE1", "PE2", "PE3";
 552                                 function = "spi2";
 553                         };
 554
 555                         spi2_cs0_pe_pin: spi2-cs0-pe-pin {
 556                                 pins = "PE0";
 557                                 function = "spi2";
 558                         };
 559
 560                         uart1_pe_pins: uart1-pe-pins {
 561                                 pins = "PE10", "PE11";
 562                                 function = "uart1";
 563                         };
 564
 565                         uart1_pg_pins: uart1-pg-pins {
 566                                 pins = "PG3", "PG4";
 567                                 function = "uart1";
 568                         };
 569
 570                         uart2_pd_pins: uart2-pd-pins {
 571                                 pins = "PD2", "PD3";
 572                                 function = "uart2";
 573                         };
 574
 575                         uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
 576                                 pins = "PD4", "PD5";
 577                                 function = "uart2";
 578                         };
 579
 580                         uart3_pg_pins: uart3-pg-pins {
 581                                 pins = "PG9", "PG10";
 582                                 function = "uart3";
 583                         };
 584
 585                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
 586                                 pins = "PG11", "PG12";
 587                                 function = "uart3";
 588                         };
 589                 };
 590
 591                 timer@1c20c00 {
 592                         compatible = "allwinner,sun4i-a10-timer";
 593                         reg = <0x01c20c00 0x90>;
 594                         interrupts = <22>,
 595                                      <23>,
 596                                      <24>,
 597                                      <25>,
 598                                      <67>,
 599                                      <68>;
 600                         clocks = <&ccu CLK_HOSC>;
 601                 };
 602
 603                 wdt: watchdog@1c20c90 {
 604                         compatible = "allwinner,sun4i-a10-wdt";
 605                         reg = <0x01c20c90 0x10>;
 606                         interrupts = <24>;
 607                         clocks = <&osc24M>;
 608                 };
 609
 610                 ir0: ir@1c21800 {
 611                         compatible = "allwinner,sun4i-a10-ir";
 612                         clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
 613                         clock-names = "apb", "ir";
 614                         interrupts = <5>;
 615                         reg = <0x01c21800 0x40>;
 616                         status = "disabled";
 617                 };
 618
 619                 lradc: lradc@1c22800 {
 620                         compatible = "allwinner,sun4i-a10-lradc-keys";
 621                         reg = <0x01c22800 0x100>;
 622                         interrupts = <31>;
 623                         status = "disabled";
 624                 };
 625
 626                 codec: codec@1c22c00 {
 627                         #sound-dai-cells = <0>;
 628                         compatible = "allwinner,sun4i-a10-codec";
 629                         reg = <0x01c22c00 0x40>;
 630                         interrupts = <30>;
 631                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 632                         clock-names = "apb", "codec";
 633                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 634                                <&dma SUN4I_DMA_NORMAL 19>;
 635                         dma-names = "rx", "tx";
 636                         status = "disabled";
 637                 };
 638
 639                 sid: eeprom@1c23800 {
 640                         compatible = "allwinner,sun4i-a10-sid";
 641                         reg = <0x01c23800 0x10>;
 642                 };
 643
 644                 rtp: rtp@1c25000 {
 645                         compatible = "allwinner,sun5i-a13-ts";
 646                         reg = <0x01c25000 0x100>;
 647                         interrupts = <29>;
 648                         #thermal-sensor-cells = <0>;
 649                 };
 650
 651                 uart0: serial@1c28000 {
 652                         compatible = "snps,dw-apb-uart";
 653                         reg = <0x01c28000 0x400>;
 654                         interrupts = <1>;
 655                         reg-shift = <2>;
 656                         reg-io-width = <4>;
 657                         clocks = <&ccu CLK_APB1_UART0>;
 658                         status = "disabled";
 659                 };
 660
 661                 uart1: serial@1c28400 {
 662                         compatible = "snps,dw-apb-uart";
 663                         reg = <0x01c28400 0x400>;
 664                         interrupts = <2>;
 665                         reg-shift = <2>;
 666                         reg-io-width = <4>;
 667                         clocks = <&ccu CLK_APB1_UART1>;
 668                         status = "disabled";
 669                 };
 670
 671                 uart2: serial@1c28800 {
 672                         compatible = "snps,dw-apb-uart";
 673                         reg = <0x01c28800 0x400>;
 674                         interrupts = <3>;
 675                         reg-shift = <2>;
 676                         reg-io-width = <4>;
 677                         clocks = <&ccu CLK_APB1_UART2>;
 678                         status = "disabled";
 679                 };
 680
 681                 uart3: serial@1c28c00 {
 682                         compatible = "snps,dw-apb-uart";
 683                         reg = <0x01c28c00 0x400>;
 684                         interrupts = <4>;
 685                         reg-shift = <2>;
 686                         reg-io-width = <4>;
 687                         clocks = <&ccu CLK_APB1_UART3>;
 688                         status = "disabled";
 689                 };
 690
 691                 i2c0: i2c@1c2ac00 {
 692                         compatible = "allwinner,sun4i-a10-i2c";
 693                         reg = <0x01c2ac00 0x400>;
 694                         interrupts = <7>;
 695                         clocks = <&ccu CLK_APB1_I2C0>;
 696                         pinctrl-names = "default";
 697                         pinctrl-0 = <&i2c0_pins>;
 698                         status = "disabled";
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                 };
 702
 703                 i2c1: i2c@1c2b000 {
 704                         compatible = "allwinner,sun4i-a10-i2c";
 705                         reg = <0x01c2b000 0x400>;
 706                         interrupts = <8>;
 707                         clocks = <&ccu CLK_APB1_I2C1>;
 708                         pinctrl-names = "default";
 709                         pinctrl-0 = <&i2c1_pins>;
 710                         status = "disabled";
 711                         #address-cells = <1>;
 712                         #size-cells = <0>;
 713                 };
 714
 715                 i2c2: i2c@1c2b400 {
 716                         compatible = "allwinner,sun4i-a10-i2c";
 717                         reg = <0x01c2b400 0x400>;
 718                         interrupts = <9>;
 719                         clocks = <&ccu CLK_APB1_I2C2>;
 720                         pinctrl-names = "default";
 721                         pinctrl-0 = <&i2c2_pins>;
 722                         status = "disabled";
 723                         #address-cells = <1>;
 724                         #size-cells = <0>;
 725                 };
 726
 727                 timer@1c60000 {
 728                         compatible = "allwinner,sun5i-a13-hstimer";
 729                         reg = <0x01c60000 0x1000>;
 730                         interrupts = <82>, <83>;
 731                         clocks = <&ccu CLK_AHB_HSTIMER>;
 732                 };
 733
 734                 fe0: display-frontend@1e00000 {
 735                         compatible = "allwinner,sun5i-a13-display-frontend";
 736                         reg = <0x01e00000 0x20000>;
 737                         interrupts = <47>;
 738                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
 739                                  <&ccu CLK_DRAM_DE_FE>;
 740                         clock-names = "ahb", "mod",
 741                                       "ram";
 742                         resets = <&ccu RST_DE_FE>;
 743                         interconnects = <&mbus 19>;
 744                         interconnect-names = "dma-mem";
 745                         status = "disabled";
 746
 747                         ports {
 748                                 #address-cells = <1>;
 749                                 #size-cells = <0>;
 750
 751                                 fe0_out: port@1 {
 752                                         reg = <1>;
 753
 754                                         fe0_out_be0: endpoint {
 755                                                 remote-endpoint = <&be0_in_fe0>;
 756                                         };
 757                                 };
 758                         };
 759                 };
 760
 761                 be0: display-backend@1e60000 {
 762                         compatible = "allwinner,sun5i-a13-display-backend";
 763                         reg = <0x01e60000 0x10000>;
 764                         interrupts = <47>;
 765                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
 766                                  <&ccu CLK_DRAM_DE_BE>;
 767                         clock-names = "ahb", "mod",
 768                                       "ram";
 769                         resets = <&ccu RST_DE_BE>;
 770                         interconnects = <&mbus 18>;
 771                         interconnect-names = "dma-mem";
 772                         status = "disabled";
 773
 774                         assigned-clocks = <&ccu CLK_DE_BE>;
 775                         assigned-clock-rates = <300000000>;
 776
 777                         ports {
 778                                 #address-cells = <1>;
 779                                 #size-cells = <0>;
 780
 781                                 be0_in: port@0 {
 782                                         reg = <0>;
 783
 784                                         be0_in_fe0: endpoint {
 785                                                 remote-endpoint = <&fe0_out_be0>;
 786                                         };
 787                                 };
 788
 789                                 be0_out: port@1 {
 790                                         reg = <1>;
 791
 792                                         be0_out_tcon0: endpoint {
 793                                                 remote-endpoint = <&tcon0_in_be0>;
 794                                         };
 795                                 };
 796                         };
 797                 };
 798         };
 799 };