Merge tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregk...
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun5i-a13.dtsi
1 /*
2  * Copyright 2012 Maxime Ripard
3  *
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
5  *
6  * The code contained herein is licensed under the GNU General Public
7  * License. You may obtain a copy of the GNU General Public License
8  * Version 2 or later at the following locations:
9  *
10  * http://www.opensource.org/licenses/gpl-license.html
11  * http://www.gnu.org/copyleft/gpl.html
12  */
13
14 /include/ "skeleton.dtsi"
15
16 / {
17         interrupt-parent = <&intc>;
18
19         cpus {
20                 #address-cells = <1>;
21                 #size-cells = <0>;
22                 cpu@0 {
23                         device_type = "cpu";
24                         compatible = "arm,cortex-a8";
25                         reg = <0x0>;
26                 };
27         };
28
29         memory {
30                 reg = <0x40000000 0x20000000>;
31         };
32
33         clocks {
34                 #address-cells = <1>;
35                 #size-cells = <1>;
36                 ranges;
37
38                 /*
39                  * This is a dummy clock, to be used as placeholder on
40                  * other mux clocks when a specific parent clock is not
41                  * yet implemented. It should be dropped when the driver
42                  * is complete.
43                  */
44                 dummy: dummy {
45                         #clock-cells = <0>;
46                         compatible = "fixed-clock";
47                         clock-frequency = <0>;
48                 };
49
50                 osc24M: osc24M@01c20050 {
51                         #clock-cells = <0>;
52                         compatible = "allwinner,sun4i-osc-clk";
53                         reg = <0x01c20050 0x4>;
54                         clock-frequency = <24000000>;
55                 };
56
57                 osc32k: osc32k {
58                         #clock-cells = <0>;
59                         compatible = "fixed-clock";
60                         clock-frequency = <32768>;
61                 };
62
63                 pll1: pll1@01c20000 {
64                         #clock-cells = <0>;
65                         compatible = "allwinner,sun4i-pll1-clk";
66                         reg = <0x01c20000 0x4>;
67                         clocks = <&osc24M>;
68                 };
69
70                 pll4: pll4@01c20018 {
71                         #clock-cells = <0>;
72                         compatible = "allwinner,sun4i-pll1-clk";
73                         reg = <0x01c20018 0x4>;
74                         clocks = <&osc24M>;
75                 };
76
77                 pll5: pll5@01c20020 {
78                         #clock-cells = <1>;
79                         compatible = "allwinner,sun4i-pll5-clk";
80                         reg = <0x01c20020 0x4>;
81                         clocks = <&osc24M>;
82                         clock-output-names = "pll5_ddr", "pll5_other";
83                 };
84
85                 pll6: pll6@01c20028 {
86                         #clock-cells = <1>;
87                         compatible = "allwinner,sun4i-pll6-clk";
88                         reg = <0x01c20028 0x4>;
89                         clocks = <&osc24M>;
90                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
91                 };
92
93                 /* dummy is 200M */
94                 cpu: cpu@01c20054 {
95                         #clock-cells = <0>;
96                         compatible = "allwinner,sun4i-cpu-clk";
97                         reg = <0x01c20054 0x4>;
98                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
99                 };
100
101                 axi: axi@01c20054 {
102                         #clock-cells = <0>;
103                         compatible = "allwinner,sun4i-axi-clk";
104                         reg = <0x01c20054 0x4>;
105                         clocks = <&cpu>;
106                 };
107
108                 axi_gates: axi_gates@01c2005c {
109                         #clock-cells = <1>;
110                         compatible = "allwinner,sun4i-axi-gates-clk";
111                         reg = <0x01c2005c 0x4>;
112                         clocks = <&axi>;
113                         clock-output-names = "axi_dram";
114                 };
115
116                 ahb: ahb@01c20054 {
117                         #clock-cells = <0>;
118                         compatible = "allwinner,sun4i-ahb-clk";
119                         reg = <0x01c20054 0x4>;
120                         clocks = <&axi>;
121                 };
122
123                 ahb_gates: ahb_gates@01c20060 {
124                         #clock-cells = <1>;
125                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
126                         reg = <0x01c20060 0x8>;
127                         clocks = <&ahb>;
128                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
129                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
130                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
131                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
132                                 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
133                                 "ahb_de_fe", "ahb_iep", "ahb_mali400";
134                 };
135
136                 apb0: apb0@01c20054 {
137                         #clock-cells = <0>;
138                         compatible = "allwinner,sun4i-apb0-clk";
139                         reg = <0x01c20054 0x4>;
140                         clocks = <&ahb>;
141                 };
142
143                 apb0_gates: apb0_gates@01c20068 {
144                         #clock-cells = <1>;
145                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
146                         reg = <0x01c20068 0x4>;
147                         clocks = <&apb0>;
148                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
149                 };
150
151                 apb1_mux: apb1_mux@01c20058 {
152                         #clock-cells = <0>;
153                         compatible = "allwinner,sun4i-apb1-mux-clk";
154                         reg = <0x01c20058 0x4>;
155                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
156                 };
157
158                 apb1: apb1@01c20058 {
159                         #clock-cells = <0>;
160                         compatible = "allwinner,sun4i-apb1-clk";
161                         reg = <0x01c20058 0x4>;
162                         clocks = <&apb1_mux>;
163                 };
164
165                 apb1_gates: apb1_gates@01c2006c {
166                         #clock-cells = <1>;
167                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
168                         reg = <0x01c2006c 0x4>;
169                         clocks = <&apb1>;
170                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
171                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
172                 };
173
174                 nand_clk: clk@01c20080 {
175                         #clock-cells = <0>;
176                         compatible = "allwinner,sun4i-mod0-clk";
177                         reg = <0x01c20080 0x4>;
178                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
179                         clock-output-names = "nand";
180                 };
181
182                 ms_clk: clk@01c20084 {
183                         #clock-cells = <0>;
184                         compatible = "allwinner,sun4i-mod0-clk";
185                         reg = <0x01c20084 0x4>;
186                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187                         clock-output-names = "ms";
188                 };
189
190                 mmc0_clk: clk@01c20088 {
191                         #clock-cells = <0>;
192                         compatible = "allwinner,sun4i-mod0-clk";
193                         reg = <0x01c20088 0x4>;
194                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195                         clock-output-names = "mmc0";
196                 };
197
198                 mmc1_clk: clk@01c2008c {
199                         #clock-cells = <0>;
200                         compatible = "allwinner,sun4i-mod0-clk";
201                         reg = <0x01c2008c 0x4>;
202                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203                         clock-output-names = "mmc1";
204                 };
205
206                 mmc2_clk: clk@01c20090 {
207                         #clock-cells = <0>;
208                         compatible = "allwinner,sun4i-mod0-clk";
209                         reg = <0x01c20090 0x4>;
210                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211                         clock-output-names = "mmc2";
212                 };
213
214                 ts_clk: clk@01c20098 {
215                         #clock-cells = <0>;
216                         compatible = "allwinner,sun4i-mod0-clk";
217                         reg = <0x01c20098 0x4>;
218                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219                         clock-output-names = "ts";
220                 };
221
222                 ss_clk: clk@01c2009c {
223                         #clock-cells = <0>;
224                         compatible = "allwinner,sun4i-mod0-clk";
225                         reg = <0x01c2009c 0x4>;
226                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227                         clock-output-names = "ss";
228                 };
229
230                 spi0_clk: clk@01c200a0 {
231                         #clock-cells = <0>;
232                         compatible = "allwinner,sun4i-mod0-clk";
233                         reg = <0x01c200a0 0x4>;
234                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235                         clock-output-names = "spi0";
236                 };
237
238                 spi1_clk: clk@01c200a4 {
239                         #clock-cells = <0>;
240                         compatible = "allwinner,sun4i-mod0-clk";
241                         reg = <0x01c200a4 0x4>;
242                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243                         clock-output-names = "spi1";
244                 };
245
246                 spi2_clk: clk@01c200a8 {
247                         #clock-cells = <0>;
248                         compatible = "allwinner,sun4i-mod0-clk";
249                         reg = <0x01c200a8 0x4>;
250                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251                         clock-output-names = "spi2";
252                 };
253
254                 ir0_clk: clk@01c200b0 {
255                         #clock-cells = <0>;
256                         compatible = "allwinner,sun4i-mod0-clk";
257                         reg = <0x01c200b0 0x4>;
258                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259                         clock-output-names = "ir0";
260                 };
261
262                 mbus_clk: clk@01c2015c {
263                         #clock-cells = <0>;
264                         compatible = "allwinner,sun4i-mod0-clk";
265                         reg = <0x01c2015c 0x4>;
266                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267                         clock-output-names = "mbus";
268                 };
269         };
270
271         soc@01c00000 {
272                 compatible = "simple-bus";
273                 #address-cells = <1>;
274                 #size-cells = <1>;
275                 ranges;
276
277                 intc: interrupt-controller@01c20400 {
278                         compatible = "allwinner,sun4i-a10-ic";
279                         reg = <0x01c20400 0x400>;
280                         interrupt-controller;
281                         #interrupt-cells = <1>;
282                 };
283
284                 pio: pinctrl@01c20800 {
285                         compatible = "allwinner,sun5i-a13-pinctrl";
286                         reg = <0x01c20800 0x400>;
287                         interrupts = <28>;
288                         clocks = <&apb0_gates 5>;
289                         gpio-controller;
290                         interrupt-controller;
291                         #address-cells = <1>;
292                         #size-cells = <0>;
293                         #gpio-cells = <3>;
294
295                         uart1_pins_a: uart1@0 {
296                                 allwinner,pins = "PE10", "PE11";
297                                 allwinner,function = "uart1";
298                                 allwinner,drive = <0>;
299                                 allwinner,pull = <0>;
300                         };
301
302                         uart1_pins_b: uart1@1 {
303                                 allwinner,pins = "PG3", "PG4";
304                                 allwinner,function = "uart1";
305                                 allwinner,drive = <0>;
306                                 allwinner,pull = <0>;
307                         };
308
309                         i2c0_pins_a: i2c0@0 {
310                                 allwinner,pins = "PB0", "PB1";
311                                 allwinner,function = "i2c0";
312                                 allwinner,drive = <0>;
313                                 allwinner,pull = <0>;
314                         };
315
316                         i2c1_pins_a: i2c1@0 {
317                                 allwinner,pins = "PB15", "PB16";
318                                 allwinner,function = "i2c1";
319                                 allwinner,drive = <0>;
320                                 allwinner,pull = <0>;
321                         };
322
323                         i2c2_pins_a: i2c2@0 {
324                                 allwinner,pins = "PB17", "PB18";
325                                 allwinner,function = "i2c2";
326                                 allwinner,drive = <0>;
327                                 allwinner,pull = <0>;
328                         };
329                 };
330
331                 timer@01c20c00 {
332                         compatible = "allwinner,sun4i-a10-timer";
333                         reg = <0x01c20c00 0x90>;
334                         interrupts = <22>;
335                         clocks = <&osc24M>;
336                 };
337
338                 wdt: watchdog@01c20c90 {
339                         compatible = "allwinner,sun4i-wdt";
340                         reg = <0x01c20c90 0x10>;
341                 };
342
343                 sid: eeprom@01c23800 {
344                         compatible = "allwinner,sun4i-a10-sid";
345                         reg = <0x01c23800 0x10>;
346                 };
347
348                 rtp: rtp@01c25000 {
349                         compatible = "allwinner,sun4i-a10-ts";
350                         reg = <0x01c25000 0x100>;
351                         interrupts = <29>;
352                 };
353
354                 uart1: serial@01c28400 {
355                         compatible = "snps,dw-apb-uart";
356                         reg = <0x01c28400 0x400>;
357                         interrupts = <2>;
358                         reg-shift = <2>;
359                         reg-io-width = <4>;
360                         clocks = <&apb1_gates 17>;
361                         status = "disabled";
362                 };
363
364                 uart3: serial@01c28c00 {
365                         compatible = "snps,dw-apb-uart";
366                         reg = <0x01c28c00 0x400>;
367                         interrupts = <4>;
368                         reg-shift = <2>;
369                         reg-io-width = <4>;
370                         clocks = <&apb1_gates 19>;
371                         status = "disabled";
372                 };
373
374                 i2c0: i2c@01c2ac00 {
375                         compatible = "allwinner,sun4i-i2c";
376                         reg = <0x01c2ac00 0x400>;
377                         interrupts = <7>;
378                         clocks = <&apb1_gates 0>;
379                         clock-frequency = <100000>;
380                         status = "disabled";
381                 };
382
383                 i2c1: i2c@01c2b000 {
384                         compatible = "allwinner,sun4i-i2c";
385                         reg = <0x01c2b000 0x400>;
386                         interrupts = <8>;
387                         clocks = <&apb1_gates 1>;
388                         clock-frequency = <100000>;
389                         status = "disabled";
390                 };
391
392                 i2c2: i2c@01c2b400 {
393                         compatible = "allwinner,sun4i-i2c";
394                         reg = <0x01c2b400 0x400>;
395                         interrupts = <9>;
396                         clocks = <&apb1_gates 2>;
397                         clock-frequency = <100000>;
398                         status = "disabled";
399                 };
400
401                 timer@01c60000 {
402                         compatible = "allwinner,sun5i-a13-hstimer";
403                         reg = <0x01c60000 0x1000>;
404                         interrupts = <82>, <83>;
405                         clocks = <&ahb_gates 28>;
406                 };
407         };
408 };