arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/thermal/thermal.h>
  45 #include <dt-bindings/dma/sun4i-a10.h>
  46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
  47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  48
  49 / {
  50         #address-cells = <1>;
  51         #size-cells = <1>;
  52         interrupt-parent = <&intc>;
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56         };
  57
  58         chosen {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 framebuffer-lcd0-hdmi {
  64                         compatible = "allwinner,simple-framebuffer",
  65                                      "simple-framebuffer";
  66                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  67                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  68                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  69                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
  70                         status = "disabled";
  71                 };
  72
  73                 framebuffer-fe0-lcd0-hdmi {
  74                         compatible = "allwinner,simple-framebuffer",
  75                                      "simple-framebuffer";
  76                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  77                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  78                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
  79                                  <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
  80                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
  81                                  <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
  82                         status = "disabled";
  83                 };
  84
  85                 framebuffer-fe0-lcd0 {
  86                         compatible = "allwinner,simple-framebuffer",
  87                                      "simple-framebuffer";
  88                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  89                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  90                                  <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
  91                                  <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
  92                                  <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
  93                         status = "disabled";
  94                 };
  95
  96                 framebuffer-fe0-lcd0-tve0 {
  97                         compatible = "allwinner,simple-framebuffer",
  98                                      "simple-framebuffer";
  99                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
 100                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
 101                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
 102                                  <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
 103                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
 104                                  <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
 105                         status = "disabled";
 106                 };
 107         };
 108
 109         cpus {
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112                 cpu0: cpu@0 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a8";
 115                         reg = <0x0>;
 116                         clocks = <&ccu CLK_CPU>;
 117                         clock-latency = <244144>; /* 8 32k periods */
 118                         operating-points = <
 119                                 /* kHz    uV */
 120                                 1008000 1400000
 121                                 912000  1350000
 122                                 864000  1300000
 123                                 624000  1250000
 124                                 >;
 125                         #cooling-cells = <2>;
 126                 };
 127         };
 128
 129         thermal-zones {
 130                 cpu-thermal {
 131                         /* milliseconds */
 132                         polling-delay-passive = <250>;
 133                         polling-delay = <1000>;
 134                         thermal-sensors = <&rtp>;
 135
 136                         cooling-maps {
 137                                 map0 {
 138                                         trip = <&cpu_alert0>;
 139                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 140                                 };
 141                         };
 142
 143                         trips {
 144                                 cpu_alert0: cpu-alert0 {
 145                                         /* milliCelsius */
 146                                         temperature = <850000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150
 151                                 cpu_crit: cpu-crit {
 152                                         /* milliCelsius */
 153                                         temperature = <100000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical";
 156                                 };
 157                         };
 158                 };
 159         };
 160
 161         clocks {
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges;
 165
 166                 osc24M: clk-24M {
 167                         #clock-cells = <0>;
 168                         compatible = "fixed-clock";
 169                         clock-frequency = <24000000>;
 170                         clock-output-names = "osc24M";
 171                 };
 172
 173                 osc32k: clk-32k {
 174                         #clock-cells = <0>;
 175                         compatible = "fixed-clock";
 176                         clock-frequency = <32768>;
 177                         clock-output-names = "osc32k";
 178                 };
 179         };
 180
 181         de: display-engine {
 182                 compatible = "allwinner,sun4i-a10-display-engine";
 183                 allwinner,pipelines = <&fe0>, <&fe1>;
 184                 status = "disabled";
 185         };
 186
 187         pmu {
 188                 compatible = "arm,cortex-a8-pmu";
 189                 interrupts = <3>;
 190         };
 191
 192         reserved-memory {
 193                 #address-cells = <1>;
 194                 #size-cells = <1>;
 195                 ranges;
 196
 197                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 198                 default-pool {
 199                         compatible = "shared-dma-pool";
 200                         size = <0x6000000>;
 201                         alloc-ranges = <0x4a000000 0x6000000>;
 202                         reusable;
 203                         linux,cma-default;
 204                 };
 205         };
 206
 207         soc {
 208                 compatible = "simple-bus";
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 ranges;
 212
 213                 system-control@1c00000 {
 214                         compatible = "allwinner,sun4i-a10-system-control";
 215                         reg = <0x01c00000 0x30>;
 216                         #address-cells = <1>;
 217                         #size-cells = <1>;
 218                         ranges;
 219
 220                         sram_a: sram@0 {
 221                                 compatible = "mmio-sram";
 222                                 reg = <0x00000000 0xc000>;
 223                                 #address-cells = <1>;
 224                                 #size-cells = <1>;
 225                                 ranges = <0 0x00000000 0xc000>;
 226
 227                                 emac_sram: sram-section@8000 {
 228                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 229                                         reg = <0x8000 0x4000>;
 230                                         status = "disabled";
 231                                 };
 232                         };
 233
 234                         sram_d: sram@10000 {
 235                                 compatible = "mmio-sram";
 236                                 reg = <0x00010000 0x1000>;
 237                                 #address-cells = <1>;
 238                                 #size-cells = <1>;
 239                                 ranges = <0 0x00010000 0x1000>;
 240
 241                                 otg_sram: sram-section@0 {
 242                                         compatible = "allwinner,sun4i-a10-sram-d";
 243                                         reg = <0x0000 0x1000>;
 244                                         status = "disabled";
 245                                 };
 246                         };
 247
 248                         sram_c: sram@1d00000 {
 249                                 compatible = "mmio-sram";
 250                                 reg = <0x01d00000 0xd0000>;
 251                                 #address-cells = <1>;
 252                                 #size-cells = <1>;
 253                                 ranges = <0 0x01d00000 0xd0000>;
 254
 255                                 ve_sram: sram-section@0 {
 256                                         compatible = "allwinner,sun4i-a10-sram-c1";
 257                                         reg = <0x000000 0x80000>;
 258                                 };
 259                         };
 260                 };
 261
 262                 dma: dma-controller@1c02000 {
 263                         compatible = "allwinner,sun4i-a10-dma";
 264                         reg = <0x01c02000 0x1000>;
 265                         interrupts = <27>;
 266                         clocks = <&ccu CLK_AHB_DMA>;
 267                         #dma-cells = <2>;
 268                 };
 269
 270                 nfc: nand-controller@1c03000 {
 271                         compatible = "allwinner,sun4i-a10-nand";
 272                         reg = <0x01c03000 0x1000>;
 273                         interrupts = <37>;
 274                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 275                         clock-names = "ahb", "mod";
 276                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 277                         dma-names = "rxtx";
 278                         status = "disabled";
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                 };
 282
 283                 spi0: spi@1c05000 {
 284                         compatible = "allwinner,sun4i-a10-spi";
 285                         reg = <0x01c05000 0x1000>;
 286                         interrupts = <10>;
 287                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 288                         clock-names = "ahb", "mod";
 289                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 290                                <&dma SUN4I_DMA_DEDICATED 26>;
 291                         dma-names = "rx", "tx";
 292                         status = "disabled";
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                 };
 296
 297                 spi1: spi@1c06000 {
 298                         compatible = "allwinner,sun4i-a10-spi";
 299                         reg = <0x01c06000 0x1000>;
 300                         interrupts = <11>;
 301                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 302                         clock-names = "ahb", "mod";
 303                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 304                                <&dma SUN4I_DMA_DEDICATED 8>;
 305                         dma-names = "rx", "tx";
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
 308                         status = "disabled";
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                 };
 312
 313                 emac: ethernet@1c0b000 {
 314                         compatible = "allwinner,sun4i-a10-emac";
 315                         reg = <0x01c0b000 0x1000>;
 316                         interrupts = <55>;
 317                         clocks = <&ccu CLK_AHB_EMAC>;
 318                         allwinner,sram = <&emac_sram 1>;
 319                         pinctrl-names = "default";
 320                         pinctrl-0 = <&emac_pins>;
 321                         status = "disabled";
 322                 };
 323
 324                 mdio: mdio@1c0b080 {
 325                         compatible = "allwinner,sun4i-a10-mdio";
 326                         reg = <0x01c0b080 0x14>;
 327                         status = "disabled";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                 };
 331
 332                 tcon0: lcd-controller@1c0c000 {
 333                         compatible = "allwinner,sun4i-a10-tcon";
 334                         reg = <0x01c0c000 0x1000>;
 335                         interrupts = <44>;
 336                         resets = <&ccu RST_TCON0>;
 337                         reset-names = "lcd";
 338                         clocks = <&ccu CLK_AHB_LCD0>,
 339                                  <&ccu CLK_TCON0_CH0>,
 340                                  <&ccu CLK_TCON0_CH1>;
 341                         clock-names = "ahb",
 342                                       "tcon-ch0",
 343                                       "tcon-ch1";
 344                         clock-output-names = "tcon0-pixel-clock";
 345                         #clock-cells = <0>;
 346                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 347
 348                         ports {
 349                                 #address-cells = <1>;
 350                                 #size-cells = <0>;
 351
 352                                 tcon0_in: port@0 {
 353                                         #address-cells = <1>;
 354                                         #size-cells = <0>;
 355                                         reg = <0>;
 356
 357                                         tcon0_in_be0: endpoint@0 {
 358                                                 reg = <0>;
 359                                                 remote-endpoint = <&be0_out_tcon0>;
 360                                         };
 361
 362                                         tcon0_in_be1: endpoint@1 {
 363                                                 reg = <1>;
 364                                                 remote-endpoint = <&be1_out_tcon0>;
 365                                         };
 366                                 };
 367
 368                                 tcon0_out: port@1 {
 369                                         #address-cells = <1>;
 370                                         #size-cells = <0>;
 371                                         reg = <1>;
 372
 373                                         tcon0_out_hdmi: endpoint@1 {
 374                                                 reg = <1>;
 375                                                 remote-endpoint = <&hdmi_in_tcon0>;
 376                                                 allwinner,tcon-channel = <1>;
 377                                         };
 378                                 };
 379                         };
 380                 };
 381
 382                 tcon1: lcd-controller@1c0d000 {
 383                         compatible = "allwinner,sun4i-a10-tcon";
 384                         reg = <0x01c0d000 0x1000>;
 385                         interrupts = <45>;
 386                         resets = <&ccu RST_TCON1>;
 387                         reset-names = "lcd";
 388                         clocks = <&ccu CLK_AHB_LCD1>,
 389                                  <&ccu CLK_TCON1_CH0>,
 390                                  <&ccu CLK_TCON1_CH1>;
 391                         clock-names = "ahb",
 392                                       "tcon-ch0",
 393                                       "tcon-ch1";
 394                         clock-output-names = "tcon1-pixel-clock";
 395                         #clock-cells = <0>;
 396                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 397
 398                         ports {
 399                                 #address-cells = <1>;
 400                                 #size-cells = <0>;
 401
 402                                 tcon1_in: port@0 {
 403                                         #address-cells = <1>;
 404                                         #size-cells = <0>;
 405                                         reg = <0>;
 406
 407                                         tcon1_in_be0: endpoint@0 {
 408                                                 reg = <0>;
 409                                                 remote-endpoint = <&be0_out_tcon1>;
 410                                         };
 411
 412                                         tcon1_in_be1: endpoint@1 {
 413                                                 reg = <1>;
 414                                                 remote-endpoint = <&be1_out_tcon1>;
 415                                         };
 416                                 };
 417
 418                                 tcon1_out: port@1 {
 419                                         #address-cells = <1>;
 420                                         #size-cells = <0>;
 421                                         reg = <1>;
 422
 423                                         tcon1_out_hdmi: endpoint@1 {
 424                                                 reg = <1>;
 425                                                 remote-endpoint = <&hdmi_in_tcon1>;
 426                                                 allwinner,tcon-channel = <1>;
 427                                         };
 428                                 };
 429                         };
 430                 };
 431
 432                 video-codec@1c0e000 {
 433                         compatible = "allwinner,sun4i-a10-video-engine";
 434                         reg = <0x01c0e000 0x1000>;
 435                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 436                                  <&ccu CLK_DRAM_VE>;
 437                         clock-names = "ahb", "mod", "ram";
 438                         resets = <&ccu RST_VE>;
 439                         interrupts = <53>;
 440                         allwinner,sram = <&ve_sram 1>;
 441                 };
 442
 443                 mmc0: mmc@1c0f000 {
 444                         compatible = "allwinner,sun4i-a10-mmc";
 445                         reg = <0x01c0f000 0x1000>;
 446                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 447                         clock-names = "ahb", "mmc";
 448                         interrupts = <32>;
 449                         pinctrl-names = "default";
 450                         pinctrl-0 = <&mmc0_pins>;
 451                         status = "disabled";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                 };
 455
 456                 mmc1: mmc@1c10000 {
 457                         compatible = "allwinner,sun4i-a10-mmc";
 458                         reg = <0x01c10000 0x1000>;
 459                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 460                         clock-names = "ahb", "mmc";
 461                         interrupts = <33>;
 462                         status = "disabled";
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                 };
 466
 467                 mmc2: mmc@1c11000 {
 468                         compatible = "allwinner,sun4i-a10-mmc";
 469                         reg = <0x01c11000 0x1000>;
 470                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 471                         clock-names = "ahb", "mmc";
 472                         interrupts = <34>;
 473                         status = "disabled";
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                 };
 477
 478                 mmc3: mmc@1c12000 {
 479                         compatible = "allwinner,sun4i-a10-mmc";
 480                         reg = <0x01c12000 0x1000>;
 481                         clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
 482                         clock-names = "ahb", "mmc";
 483                         interrupts = <35>;
 484                         status = "disabled";
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                 };
 488
 489                 usb_otg: usb@1c13000 {
 490                         compatible = "allwinner,sun4i-a10-musb";
 491                         reg = <0x01c13000 0x0400>;
 492                         clocks = <&ccu CLK_AHB_OTG>;
 493                         interrupts = <38>;
 494                         interrupt-names = "mc";
 495                         phys = <&usbphy 0>;
 496                         phy-names = "usb";
 497                         extcon = <&usbphy 0>;
 498                         allwinner,sram = <&otg_sram 1>;
 499                         dr_mode = "otg";
 500                         status = "disabled";
 501                 };
 502
 503                 usbphy: phy@1c13400 {
 504                         #phy-cells = <1>;
 505                         compatible = "allwinner,sun4i-a10-usb-phy";
 506                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 507                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 508                         clocks = <&ccu CLK_USB_PHY>;
 509                         clock-names = "usb_phy";
 510                         resets = <&ccu RST_USB_PHY0>,
 511                                  <&ccu RST_USB_PHY1>,
 512                                  <&ccu RST_USB_PHY2>;
 513                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 514                         status = "disabled";
 515                 };
 516
 517                 ehci0: usb@1c14000 {
 518                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 519                         reg = <0x01c14000 0x100>;
 520                         interrupts = <39>;
 521                         clocks = <&ccu CLK_AHB_EHCI0>;
 522                         phys = <&usbphy 1>;
 523                         status = "disabled";
 524                 };
 525
 526                 ohci0: usb@1c14400 {
 527                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 528                         reg = <0x01c14400 0x100>;
 529                         interrupts = <64>;
 530                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 531                         phys = <&usbphy 1>;
 532                         status = "disabled";
 533                 };
 534
 535                 crypto: crypto-engine@1c15000 {
 536                         compatible = "allwinner,sun4i-a10-crypto";
 537                         reg = <0x01c15000 0x1000>;
 538                         interrupts = <86>;
 539                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 540                         clock-names = "ahb", "mod";
 541                 };
 542
 543                 hdmi: hdmi@1c16000 {
 544                         compatible = "allwinner,sun4i-a10-hdmi";
 545                         reg = <0x01c16000 0x1000>;
 546                         interrupts = <58>;
 547                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 548                                  <&ccu CLK_PLL_VIDEO0_2X>,
 549                                  <&ccu CLK_PLL_VIDEO1_2X>;
 550                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 551                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 552                                <&dma SUN4I_DMA_NORMAL 16>,
 553                                <&dma SUN4I_DMA_DEDICATED 24>;
 554                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 555                         status = "disabled";
 556
 557                         ports {
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560
 561                                 hdmi_in: port@0 {
 562                                         #address-cells = <1>;
 563                                         #size-cells = <0>;
 564                                         reg = <0>;
 565
 566                                         hdmi_in_tcon0: endpoint@0 {
 567                                                 reg = <0>;
 568                                                 remote-endpoint = <&tcon0_out_hdmi>;
 569                                         };
 570
 571                                         hdmi_in_tcon1: endpoint@1 {
 572                                                 reg = <1>;
 573                                                 remote-endpoint = <&tcon1_out_hdmi>;
 574                                         };
 575                                 };
 576
 577                                 hdmi_out: port@1 {
 578                                         reg = <1>;
 579                                 };
 580                         };
 581                 };
 582
 583                 spi2: spi@1c17000 {
 584                         compatible = "allwinner,sun4i-a10-spi";
 585                         reg = <0x01c17000 0x1000>;
 586                         interrupts = <12>;
 587                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 588                         clock-names = "ahb", "mod";
 589                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 590                                <&dma SUN4I_DMA_DEDICATED 28>;
 591                         dma-names = "rx", "tx";
 592                         status = "disabled";
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                 };
 596
 597                 ahci: sata@1c18000 {
 598                         compatible = "allwinner,sun4i-a10-ahci";
 599                         reg = <0x01c18000 0x1000>;
 600                         interrupts = <56>;
 601                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 602                         status = "disabled";
 603                 };
 604
 605                 ehci1: usb@1c1c000 {
 606                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 607                         reg = <0x01c1c000 0x100>;
 608                         interrupts = <40>;
 609                         clocks = <&ccu CLK_AHB_EHCI1>;
 610                         phys = <&usbphy 2>;
 611                         status = "disabled";
 612                 };
 613
 614                 ohci1: usb@1c1c400 {
 615                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 616                         reg = <0x01c1c400 0x100>;
 617                         interrupts = <65>;
 618                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 619                         phys = <&usbphy 2>;
 620                         status = "disabled";
 621                 };
 622
 623                 spi3: spi@1c1f000 {
 624                         compatible = "allwinner,sun4i-a10-spi";
 625                         reg = <0x01c1f000 0x1000>;
 626                         interrupts = <50>;
 627                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 628                         clock-names = "ahb", "mod";
 629                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 630                                <&dma SUN4I_DMA_DEDICATED 30>;
 631                         dma-names = "rx", "tx";
 632                         status = "disabled";
 633                         #address-cells = <1>;
 634                         #size-cells = <0>;
 635                 };
 636
 637                 ccu: clock@1c20000 {
 638                         compatible = "allwinner,sun4i-a10-ccu";
 639                         reg = <0x01c20000 0x400>;
 640                         clocks = <&osc24M>, <&osc32k>;
 641                         clock-names = "hosc", "losc";
 642                         #clock-cells = <1>;
 643                         #reset-cells = <1>;
 644                 };
 645
 646                 intc: interrupt-controller@1c20400 {
 647                         compatible = "allwinner,sun4i-a10-ic";
 648                         reg = <0x01c20400 0x400>;
 649                         interrupt-controller;
 650                         #interrupt-cells = <1>;
 651                 };
 652
 653                 pio: pinctrl@1c20800 {
 654                         compatible = "allwinner,sun4i-a10-pinctrl";
 655                         reg = <0x01c20800 0x400>;
 656                         interrupts = <28>;
 657                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 658                         clock-names = "apb", "hosc", "losc";
 659                         gpio-controller;
 660                         interrupt-controller;
 661                         #interrupt-cells = <3>;
 662                         #gpio-cells = <3>;
 663
 664                         can0_ph_pins: can0-ph-pins {
 665                                 pins = "PH20", "PH21";
 666                                 function = "can";
 667                         };
 668
 669                         emac_pins: emac0-pins {
 670                                 pins = "PA0", "PA1", "PA2",
 671                                        "PA3", "PA4", "PA5", "PA6",
 672                                        "PA7", "PA8", "PA9", "PA10",
 673                                        "PA11", "PA12", "PA13", "PA14",
 674                                        "PA15", "PA16";
 675                                 function = "emac";
 676                         };
 677
 678                         i2c0_pins: i2c0-pins {
 679                                 pins = "PB0", "PB1";
 680                                 function = "i2c0";
 681                         };
 682
 683                         i2c1_pins: i2c1-pins {
 684                                 pins = "PB18", "PB19";
 685                                 function = "i2c1";
 686                         };
 687
 688                         i2c2_pins: i2c2-pins {
 689                                 pins = "PB20", "PB21";
 690                                 function = "i2c2";
 691                         };
 692
 693                         ir0_rx_pins: ir0-rx-pin {
 694                                 pins = "PB4";
 695                                 function = "ir0";
 696                         };
 697
 698                         ir0_tx_pins: ir0-tx-pin {
 699                                 pins = "PB3";
 700                                 function = "ir0";
 701                         };
 702
 703                         ir1_rx_pins: ir1-rx-pin {
 704                                 pins = "PB23";
 705                                 function = "ir1";
 706                         };
 707
 708                         ir1_tx_pins: ir1-tx-pin {
 709                                 pins = "PB22";
 710                                 function = "ir1";
 711                         };
 712
 713                         mmc0_pins: mmc0-pins {
 714                                 pins = "PF0", "PF1", "PF2",
 715                                        "PF3", "PF4", "PF5";
 716                                 function = "mmc0";
 717                                 drive-strength = <30>;
 718                                 bias-pull-up;
 719                         };
 720
 721                         ps2_ch0_pins: ps2-ch0-pins {
 722                                 pins = "PI20", "PI21";
 723                                 function = "ps2";
 724                         };
 725
 726                         ps2_ch1_ph_pins: ps2-ch1-ph-pins {
 727                                 pins = "PH12", "PH13";
 728                                 function = "ps2";
 729                         };
 730
 731                         pwm0_pin: pwm0-pin {
 732                                 pins = "PB2";
 733                                 function = "pwm";
 734                         };
 735
 736                         pwm1_pin: pwm1-pin {
 737                                 pins = "PI3";
 738                                 function = "pwm";
 739                         };
 740
 741                         spdif_tx_pin: spdif-tx-pin {
 742                                 pins = "PB13";
 743                                 function = "spdif";
 744                                 bias-pull-up;
 745                         };
 746
 747                         spi0_pi_pins: spi0-pi-pins {
 748                                 pins = "PI11", "PI12", "PI13";
 749                                 function = "spi0";
 750                         };
 751
 752                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 753                                 pins = "PI10";
 754                                 function = "spi0";
 755                         };
 756
 757                         spi1_pins: spi1-pins {
 758                                 pins = "PI17", "PI18", "PI19";
 759                                 function = "spi1";
 760                         };
 761
 762                         spi1_cs0_pin: spi1-cs0-pin {
 763                                 pins = "PI16";
 764                                 function = "spi1";
 765                         };
 766
 767                         spi2_pb_pins: spi2-pb-pins {
 768                                 pins = "PB15", "PB16", "PB17";
 769                                 function = "spi2";
 770                         };
 771
 772                         spi2_pc_pins: spi2-pc-pins {
 773                                 pins = "PC20", "PC21", "PC22";
 774                                 function = "spi2";
 775                         };
 776
 777                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 778                                 pins = "PB14";
 779                                 function = "spi2";
 780                         };
 781
 782                         spi2_cs0_pc_pins: spi2-cs0-pc-pin {
 783                                 pins = "PC19";
 784                                 function = "spi2";
 785                         };
 786
 787                         uart0_pb_pins: uart0-pb-pins {
 788                                 pins = "PB22", "PB23";
 789                                 function = "uart0";
 790                         };
 791
 792                         uart0_pf_pins: uart0-pf-pins {
 793                                 pins = "PF2", "PF4";
 794                                 function = "uart0";
 795                         };
 796
 797                         uart1_pins: uart1-pins {
 798                                 pins = "PA10", "PA11";
 799                                 function = "uart1";
 800                         };
 801                 };
 802
 803                 timer@1c20c00 {
 804                         compatible = "allwinner,sun4i-a10-timer";
 805                         reg = <0x01c20c00 0x90>;
 806                         interrupts = <22>,
 807                                      <23>,
 808                                      <24>,
 809                                      <25>,
 810                                      <67>,
 811                                      <68>;
 812                         clocks = <&osc24M>;
 813                 };
 814
 815                 wdt: watchdog@1c20c90 {
 816                         compatible = "allwinner,sun4i-a10-wdt";
 817                         reg = <0x01c20c90 0x10>;
 818                         interrupts = <24>;
 819                         clocks = <&osc24M>;
 820                 };
 821
 822                 rtc: rtc@1c20d00 {
 823                         compatible = "allwinner,sun4i-a10-rtc";
 824                         reg = <0x01c20d00 0x20>;
 825                         interrupts = <24>;
 826                 };
 827
 828                 pwm: pwm@1c20e00 {
 829                         compatible = "allwinner,sun4i-a10-pwm";
 830                         reg = <0x01c20e00 0xc>;
 831                         clocks = <&osc24M>;
 832                         #pwm-cells = <3>;
 833                         status = "disabled";
 834                 };
 835
 836                 spdif: spdif@1c21000 {
 837                         #sound-dai-cells = <0>;
 838                         compatible = "allwinner,sun4i-a10-spdif";
 839                         reg = <0x01c21000 0x400>;
 840                         interrupts = <13>;
 841                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
 842                         clock-names = "apb", "spdif";
 843                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
 844                                <&dma SUN4I_DMA_NORMAL 2>;
 845                         dma-names = "rx", "tx";
 846                         status = "disabled";
 847                 };
 848
 849                 ir0: ir@1c21800 {
 850                         compatible = "allwinner,sun4i-a10-ir";
 851                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
 852                         clock-names = "apb", "ir";
 853                         interrupts = <5>;
 854                         reg = <0x01c21800 0x40>;
 855                         status = "disabled";
 856                 };
 857
 858                 ir1: ir@1c21c00 {
 859                         compatible = "allwinner,sun4i-a10-ir";
 860                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
 861                         clock-names = "apb", "ir";
 862                         interrupts = <6>;
 863                         reg = <0x01c21c00 0x40>;
 864                         status = "disabled";
 865                 };
 866
 867                 i2s0: i2s@1c22400 {
 868                         #sound-dai-cells = <0>;
 869                         compatible = "allwinner,sun4i-a10-i2s";
 870                         reg = <0x01c22400 0x400>;
 871                         interrupts = <16>;
 872                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
 873                         clock-names = "apb", "mod";
 874                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
 875                                <&dma SUN4I_DMA_NORMAL 3>;
 876                         dma-names = "rx", "tx";
 877                         status = "disabled";
 878                 };
 879
 880                 lradc: lradc@1c22800 {
 881                         compatible = "allwinner,sun4i-a10-lradc-keys";
 882                         reg = <0x01c22800 0x100>;
 883                         interrupts = <31>;
 884                         status = "disabled";
 885                 };
 886
 887                 codec: codec@1c22c00 {
 888                         #sound-dai-cells = <0>;
 889                         compatible = "allwinner,sun4i-a10-codec";
 890                         reg = <0x01c22c00 0x40>;
 891                         interrupts = <30>;
 892                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 893                         clock-names = "apb", "codec";
 894                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 895                                <&dma SUN4I_DMA_NORMAL 19>;
 896                         dma-names = "rx", "tx";
 897                         status = "disabled";
 898                 };
 899
 900                 sid: eeprom@1c23800 {
 901                         compatible = "allwinner,sun4i-a10-sid";
 902                         reg = <0x01c23800 0x10>;
 903                 };
 904
 905                 rtp: rtp@1c25000 {
 906                         compatible = "allwinner,sun4i-a10-ts";
 907                         reg = <0x01c25000 0x100>;
 908                         interrupts = <29>;
 909                         #thermal-sensor-cells = <0>;
 910                 };
 911
 912                 uart0: serial@1c28000 {
 913                         compatible = "snps,dw-apb-uart";
 914                         reg = <0x01c28000 0x400>;
 915                         interrupts = <1>;
 916                         reg-shift = <2>;
 917                         reg-io-width = <4>;
 918                         clocks = <&ccu CLK_APB1_UART0>;
 919                         status = "disabled";
 920                 };
 921
 922                 uart1: serial@1c28400 {
 923                         compatible = "snps,dw-apb-uart";
 924                         reg = <0x01c28400 0x400>;
 925                         interrupts = <2>;
 926                         reg-shift = <2>;
 927                         reg-io-width = <4>;
 928                         clocks = <&ccu CLK_APB1_UART1>;
 929                         status = "disabled";
 930                 };
 931
 932                 uart2: serial@1c28800 {
 933                         compatible = "snps,dw-apb-uart";
 934                         reg = <0x01c28800 0x400>;
 935                         interrupts = <3>;
 936                         reg-shift = <2>;
 937                         reg-io-width = <4>;
 938                         clocks = <&ccu CLK_APB1_UART2>;
 939                         status = "disabled";
 940                 };
 941
 942                 uart3: serial@1c28c00 {
 943                         compatible = "snps,dw-apb-uart";
 944                         reg = <0x01c28c00 0x400>;
 945                         interrupts = <4>;
 946                         reg-shift = <2>;
 947                         reg-io-width = <4>;
 948                         clocks = <&ccu CLK_APB1_UART3>;
 949                         status = "disabled";
 950                 };
 951
 952                 uart4: serial@1c29000 {
 953                         compatible = "snps,dw-apb-uart";
 954                         reg = <0x01c29000 0x400>;
 955                         interrupts = <17>;
 956                         reg-shift = <2>;
 957                         reg-io-width = <4>;
 958                         clocks = <&ccu CLK_APB1_UART4>;
 959                         status = "disabled";
 960                 };
 961
 962                 uart5: serial@1c29400 {
 963                         compatible = "snps,dw-apb-uart";
 964                         reg = <0x01c29400 0x400>;
 965                         interrupts = <18>;
 966                         reg-shift = <2>;
 967                         reg-io-width = <4>;
 968                         clocks = <&ccu CLK_APB1_UART5>;
 969                         status = "disabled";
 970                 };
 971
 972                 uart6: serial@1c29800 {
 973                         compatible = "snps,dw-apb-uart";
 974                         reg = <0x01c29800 0x400>;
 975                         interrupts = <19>;
 976                         reg-shift = <2>;
 977                         reg-io-width = <4>;
 978                         clocks = <&ccu CLK_APB1_UART6>;
 979                         status = "disabled";
 980                 };
 981
 982                 uart7: serial@1c29c00 {
 983                         compatible = "snps,dw-apb-uart";
 984                         reg = <0x01c29c00 0x400>;
 985                         interrupts = <20>;
 986                         reg-shift = <2>;
 987                         reg-io-width = <4>;
 988                         clocks = <&ccu CLK_APB1_UART7>;
 989                         status = "disabled";
 990                 };
 991
 992                 ps20: ps2@1c2a000 {
 993                         compatible = "allwinner,sun4i-a10-ps2";
 994                         reg = <0x01c2a000 0x400>;
 995                         interrupts = <62>;
 996                         clocks = <&ccu CLK_APB1_PS20>;
 997                         status = "disabled";
 998                 };
 999
1000                 ps21: ps2@1c2a400 {
1001                         compatible = "allwinner,sun4i-a10-ps2";
1002                         reg = <0x01c2a400 0x400>;
1003                         interrupts = <63>;
1004                         clocks = <&ccu CLK_APB1_PS21>;
1005                         status = "disabled";
1006                 };
1007
1008                 i2c0: i2c@1c2ac00 {
1009                         compatible = "allwinner,sun4i-a10-i2c";
1010                         reg = <0x01c2ac00 0x400>;
1011                         interrupts = <7>;
1012                         clocks = <&ccu CLK_APB1_I2C0>;
1013                         pinctrl-names = "default";
1014                         pinctrl-0 = <&i2c0_pins>;
1015                         status = "disabled";
1016                         #address-cells = <1>;
1017                         #size-cells = <0>;
1018                 };
1019
1020                 i2c1: i2c@1c2b000 {
1021                         compatible = "allwinner,sun4i-a10-i2c";
1022                         reg = <0x01c2b000 0x400>;
1023                         interrupts = <8>;
1024                         clocks = <&ccu CLK_APB1_I2C1>;
1025                         pinctrl-names = "default";
1026                         pinctrl-0 = <&i2c1_pins>;
1027                         status = "disabled";
1028                         #address-cells = <1>;
1029                         #size-cells = <0>;
1030                 };
1031
1032                 i2c2: i2c@1c2b400 {
1033                         compatible = "allwinner,sun4i-a10-i2c";
1034                         reg = <0x01c2b400 0x400>;
1035                         interrupts = <9>;
1036                         clocks = <&ccu CLK_APB1_I2C2>;
1037                         pinctrl-names = "default";
1038                         pinctrl-0 = <&i2c2_pins>;
1039                         status = "disabled";
1040                         #address-cells = <1>;
1041                         #size-cells = <0>;
1042                 };
1043
1044                 can0: can@1c2bc00 {
1045                         compatible = "allwinner,sun4i-a10-can";
1046                         reg = <0x01c2bc00 0x400>;
1047                         interrupts = <26>;
1048                         clocks = <&ccu CLK_APB1_CAN>;
1049                         status = "disabled";
1050                 };
1051
1052                 mali: gpu@1c40000 {
1053                         compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1054                         reg = <0x01c40000 0x10000>;
1055                         interrupts = <69>,
1056                                      <70>,
1057                                      <71>,
1058                                      <72>,
1059                                      <73>;
1060                         interrupt-names = "gp",
1061                                           "gpmmu",
1062                                           "pp0",
1063                                           "ppmmu0",
1064                                           "pmu";
1065                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1066                         clock-names = "bus", "core";
1067                         resets = <&ccu RST_GPU>;
1068
1069                         assigned-clocks = <&ccu CLK_GPU>;
1070                         assigned-clock-rates = <384000000>;
1071                 };
1072
1073                 fe0: display-frontend@1e00000 {
1074                         compatible = "allwinner,sun4i-a10-display-frontend";
1075                         reg = <0x01e00000 0x20000>;
1076                         interrupts = <47>;
1077                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1078                                  <&ccu CLK_DRAM_DE_FE0>;
1079                         clock-names = "ahb", "mod",
1080                                       "ram";
1081                         resets = <&ccu RST_DE_FE0>;
1082
1083                         ports {
1084                                 #address-cells = <1>;
1085                                 #size-cells = <0>;
1086
1087                                 fe0_out: port@1 {
1088                                         #address-cells = <1>;
1089                                         #size-cells = <0>;
1090                                         reg = <1>;
1091
1092                                         fe0_out_be0: endpoint@0 {
1093                                                 reg = <0>;
1094                                                 remote-endpoint = <&be0_in_fe0>;
1095                                         };
1096
1097                                         fe0_out_be1: endpoint@1 {
1098                                                 reg = <1>;
1099                                                 remote-endpoint = <&be1_in_fe0>;
1100                                         };
1101                                 };
1102                         };
1103                 };
1104
1105                 fe1: display-frontend@1e20000 {
1106                         compatible = "allwinner,sun4i-a10-display-frontend";
1107                         reg = <0x01e20000 0x20000>;
1108                         interrupts = <48>;
1109                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1110                                  <&ccu CLK_DRAM_DE_FE1>;
1111                         clock-names = "ahb", "mod",
1112                                       "ram";
1113                         resets = <&ccu RST_DE_FE1>;
1114
1115                         ports {
1116                                 #address-cells = <1>;
1117                                 #size-cells = <0>;
1118
1119                                 fe1_out: port@1 {
1120                                         #address-cells = <1>;
1121                                         #size-cells = <0>;
1122                                         reg = <1>;
1123
1124                                         fe1_out_be0: endpoint@0 {
1125                                                 reg = <0>;
1126                                                 remote-endpoint = <&be0_in_fe1>;
1127                                         };
1128
1129                                         fe1_out_be1: endpoint@1 {
1130                                                 reg = <1>;
1131                                                 remote-endpoint = <&be1_in_fe1>;
1132                                         };
1133                                 };
1134                         };
1135                 };
1136
1137                 be1: display-backend@1e40000 {
1138                         compatible = "allwinner,sun4i-a10-display-backend";
1139                         reg = <0x01e40000 0x10000>;
1140                         interrupts = <48>;
1141                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1142                                  <&ccu CLK_DRAM_DE_BE1>;
1143                         clock-names = "ahb", "mod",
1144                                       "ram";
1145                         resets = <&ccu RST_DE_BE1>;
1146
1147                         ports {
1148                                 #address-cells = <1>;
1149                                 #size-cells = <0>;
1150
1151                                 be1_in: port@0 {
1152                                         #address-cells = <1>;
1153                                         #size-cells = <0>;
1154                                         reg = <0>;
1155
1156                                         be1_in_fe0: endpoint@0 {
1157                                                 reg = <0>;
1158                                                 remote-endpoint = <&fe0_out_be1>;
1159                                         };
1160
1161                                         be1_in_fe1: endpoint@1 {
1162                                                 reg = <1>;
1163                                                 remote-endpoint = <&fe1_out_be1>;
1164                                         };
1165                                 };
1166
1167                                 be1_out: port@1 {
1168                                         #address-cells = <1>;
1169                                         #size-cells = <0>;
1170                                         reg = <1>;
1171
1172                                         be1_out_tcon0: endpoint@0 {
1173                                                 reg = <0>;
1174                                                 remote-endpoint = <&tcon0_in_be1>;
1175                                         };
1176
1177                                         be1_out_tcon1: endpoint@1 {
1178                                                 reg = <1>;
1179                                                 remote-endpoint = <&tcon1_in_be1>;
1180                                         };
1181                                 };
1182                         };
1183                 };
1184
1185                 be0: display-backend@1e60000 {
1186                         compatible = "allwinner,sun4i-a10-display-backend";
1187                         reg = <0x01e60000 0x10000>;
1188                         interrupts = <47>;
1189                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1190                                  <&ccu CLK_DRAM_DE_BE0>;
1191                         clock-names = "ahb", "mod",
1192                                       "ram";
1193                         resets = <&ccu RST_DE_BE0>;
1194
1195                         ports {
1196                                 #address-cells = <1>;
1197                                 #size-cells = <0>;
1198
1199                                 be0_in: port@0 {
1200                                         #address-cells = <1>;
1201                                         #size-cells = <0>;
1202                                         reg = <0>;
1203
1204                                         be0_in_fe0: endpoint@0 {
1205                                                 reg = <0>;
1206                                                 remote-endpoint = <&fe0_out_be0>;
1207                                         };
1208
1209                                         be0_in_fe1: endpoint@1 {
1210                                                 reg = <1>;
1211                                                 remote-endpoint = <&fe1_out_be0>;
1212                                         };
1213                                 };
1214
1215                                 be0_out: port@1 {
1216                                         #address-cells = <1>;
1217                                         #size-cells = <0>;
1218                                         reg = <1>;
1219
1220                                         be0_out_tcon0: endpoint@0 {
1221                                                 reg = <0>;
1222                                                 remote-endpoint = <&tcon0_in_be0>;
1223                                         };
1224
1225                                         be0_out_tcon1: endpoint@1 {
1226                                                 reg = <1>;
1227                                                 remote-endpoint = <&tcon1_in_be0>;
1228                                         };
1229                                 };
1230                         };
1231                 };
1232         };
1233 };