2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
16 interrupt-parent = <&intc>;
20 compatible = "arm,cortex-a8";
25 reg = <0x40000000 0x80000000>;
34 * This is a dummy clock, to be used as placeholder on
35 * other mux clocks when a specific parent clock is not
36 * yet implemented. It should be dropped when the driver
41 compatible = "fixed-clock";
42 clock-frequency = <0>;
45 osc24M: osc24M@01c20050 {
47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
49 clock-frequency = <24000000>;
54 compatible = "fixed-clock";
55 clock-frequency = <32768>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
68 compatible = "allwinner,sun4i-cpu-clk";
69 reg = <0x01c20054 0x4>;
70 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
75 compatible = "allwinner,sun4i-axi-clk";
76 reg = <0x01c20054 0x4>;
80 axi_gates: axi_gates@01c2005c {
82 compatible = "allwinner,sun4i-axi-gates-clk";
83 reg = <0x01c2005c 0x4>;
85 clock-output-names = "axi_dram";
90 compatible = "allwinner,sun4i-ahb-clk";
91 reg = <0x01c20054 0x4>;
95 ahb_gates: ahb_gates@01c20060 {
97 compatible = "allwinner,sun4i-ahb-gates-clk";
98 reg = <0x01c20060 0x8>;
100 clock-output-names = "ahb_usb0", "ahb_ehci0",
101 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
102 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
103 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
104 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
105 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
106 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
107 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
108 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
109 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
110 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
113 apb0: apb0@01c20054 {
115 compatible = "allwinner,sun4i-apb0-clk";
116 reg = <0x01c20054 0x4>;
120 apb0_gates: apb0_gates@01c20068 {
122 compatible = "allwinner,sun4i-apb0-gates-clk";
123 reg = <0x01c20068 0x4>;
125 clock-output-names = "apb0_codec", "apb0_spdif",
126 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
127 "apb0_ir1", "apb0_keypad";
131 apb1_mux: apb1_mux@01c20058 {
133 compatible = "allwinner,sun4i-apb1-mux-clk";
134 reg = <0x01c20058 0x4>;
135 clocks = <&osc24M>, <&dummy>, <&osc32k>;
138 apb1: apb1@01c20058 {
140 compatible = "allwinner,sun4i-apb1-clk";
141 reg = <0x01c20058 0x4>;
142 clocks = <&apb1_mux>;
145 apb1_gates: apb1_gates@01c2006c {
147 compatible = "allwinner,sun4i-apb1-gates-clk";
148 reg = <0x01c2006c 0x4>;
150 clock-output-names = "apb1_i2c0", "apb1_i2c1",
151 "apb1_i2c2", "apb1_can", "apb1_scr",
152 "apb1_ps20", "apb1_ps21", "apb1_uart0",
153 "apb1_uart1", "apb1_uart2", "apb1_uart3",
154 "apb1_uart4", "apb1_uart5", "apb1_uart6",
160 compatible = "simple-bus";
161 #address-cells = <1>;
163 reg = <0x01c20000 0x300000>;
166 intc: interrupt-controller@01c20400 {
167 compatible = "allwinner,sun4i-ic";
168 reg = <0x01c20400 0x400>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
173 pio: pinctrl@01c20800 {
174 compatible = "allwinner,sun4i-a10-pinctrl";
175 reg = <0x01c20800 0x400>;
177 clocks = <&apb0_gates 5>;
179 interrupt-controller;
180 #address-cells = <1>;
184 uart0_pins_a: uart0@0 {
185 allwinner,pins = "PB22", "PB23";
186 allwinner,function = "uart0";
187 allwinner,drive = <0>;
188 allwinner,pull = <0>;
191 uart0_pins_b: uart0@1 {
192 allwinner,pins = "PF2", "PF4";
193 allwinner,function = "uart0";
194 allwinner,drive = <0>;
195 allwinner,pull = <0>;
198 uart1_pins_a: uart1@0 {
199 allwinner,pins = "PA10", "PA11";
200 allwinner,function = "uart1";
201 allwinner,drive = <0>;
202 allwinner,pull = <0>;
205 i2c0_pins_a: i2c0@0 {
206 allwinner,pins = "PB0", "PB1";
207 allwinner,function = "i2c0";
208 allwinner,drive = <0>;
209 allwinner,pull = <0>;
212 i2c1_pins_a: i2c1@0 {
213 allwinner,pins = "PB18", "PB19";
214 allwinner,function = "i2c1";
215 allwinner,drive = <0>;
216 allwinner,pull = <0>;
219 i2c2_pins_a: i2c2@0 {
220 allwinner,pins = "PB20", "PB21";
221 allwinner,function = "i2c2";
222 allwinner,drive = <0>;
223 allwinner,pull = <0>;
228 compatible = "allwinner,sun4i-timer";
229 reg = <0x01c20c00 0x90>;
234 wdt: watchdog@01c20c90 {
235 compatible = "allwinner,sun4i-wdt";
236 reg = <0x01c20c90 0x10>;
239 uart0: serial@01c28000 {
240 compatible = "snps,dw-apb-uart";
241 reg = <0x01c28000 0x400>;
245 clocks = <&apb1_gates 16>;
249 uart1: serial@01c28400 {
250 compatible = "snps,dw-apb-uart";
251 reg = <0x01c28400 0x400>;
255 clocks = <&apb1_gates 17>;
259 uart2: serial@01c28800 {
260 compatible = "snps,dw-apb-uart";
261 reg = <0x01c28800 0x400>;
265 clocks = <&apb1_gates 18>;
269 uart3: serial@01c28c00 {
270 compatible = "snps,dw-apb-uart";
271 reg = <0x01c28c00 0x400>;
275 clocks = <&apb1_gates 19>;
279 uart4: serial@01c29000 {
280 compatible = "snps,dw-apb-uart";
281 reg = <0x01c29000 0x400>;
285 clocks = <&apb1_gates 20>;
289 uart5: serial@01c29400 {
290 compatible = "snps,dw-apb-uart";
291 reg = <0x01c29400 0x400>;
295 clocks = <&apb1_gates 21>;
299 uart6: serial@01c29800 {
300 compatible = "snps,dw-apb-uart";
301 reg = <0x01c29800 0x400>;
305 clocks = <&apb1_gates 22>;
309 uart7: serial@01c29c00 {
310 compatible = "snps,dw-apb-uart";
311 reg = <0x01c29c00 0x400>;
315 clocks = <&apb1_gates 23>;
320 compatible = "allwinner,sun4i-i2c";
321 reg = <0x01c2ac00 0x400>;
323 clocks = <&apb1_gates 0>;
324 clock-frequency = <100000>;
329 compatible = "allwinner,sun4i-i2c";
330 reg = <0x01c2b000 0x400>;
332 clocks = <&apb1_gates 1>;
333 clock-frequency = <100000>;
338 compatible = "allwinner,sun4i-i2c";
339 reg = <0x01c2b400 0x400>;
341 clocks = <&apb1_gates 2>;
342 clock-frequency = <100000>;