arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/thermal/thermal.h>
  45 #include <dt-bindings/dma/sun4i-a10.h>
  46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
  47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  48
  49 / {
  50         #address-cells = <1>;
  51         #size-cells = <1>;
  52         interrupt-parent = <&intc>;
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56         };
  57
  58         chosen {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 framebuffer-lcd0-hdmi {
  64                         compatible = "allwinner,simple-framebuffer",
  65                                      "simple-framebuffer";
  66                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  67                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  68                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  69                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
  70                         status = "disabled";
  71                 };
  72
  73                 framebuffer-fe0-lcd0-hdmi {
  74                         compatible = "allwinner,simple-framebuffer",
  75                                      "simple-framebuffer";
  76                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  77                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  78                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
  79                                  <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
  80                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
  81                                  <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
  82                         status = "disabled";
  83                 };
  84
  85                 framebuffer-fe0-lcd0 {
  86                         compatible = "allwinner,simple-framebuffer",
  87                                      "simple-framebuffer";
  88                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  89                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  90                                  <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
  91                                  <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
  92                                  <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
  93                         status = "disabled";
  94                 };
  95
  96                 framebuffer-fe0-lcd0-tve0 {
  97                         compatible = "allwinner,simple-framebuffer",
  98                                      "simple-framebuffer";
  99                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
 100                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
 101                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
 102                                  <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
 103                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
 104                                  <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
 105                         status = "disabled";
 106                 };
 107         };
 108
 109         cpus {
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112                 cpu0: cpu@0 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a8";
 115                         reg = <0x0>;
 116                         clocks = <&ccu CLK_CPU>;
 117                         clock-latency = <244144>; /* 8 32k periods */
 118                         operating-points = <
 119                                 /* kHz    uV */
 120                                 1008000 1400000
 121                                 912000  1350000
 122                                 864000  1300000
 123                                 624000  1250000
 124                                 >;
 125                         #cooling-cells = <2>;
 126                 };
 127         };
 128
 129         thermal-zones {
 130                 cpu-thermal {
 131                         /* milliseconds */
 132                         polling-delay-passive = <250>;
 133                         polling-delay = <1000>;
 134                         thermal-sensors = <&rtp>;
 135
 136                         cooling-maps {
 137                                 map0 {
 138                                         trip = <&cpu_alert0>;
 139                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 140                                 };
 141                         };
 142
 143                         trips {
 144                                 cpu_alert0: cpu-alert0 {
 145                                         /* milliCelsius */
 146                                         temperature = <850000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150
 151                                 cpu_crit: cpu-crit {
 152                                         /* milliCelsius */
 153                                         temperature = <100000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical";
 156                                 };
 157                         };
 158                 };
 159         };
 160
 161         clocks {
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges;
 165
 166                 osc24M: clk-24M {
 167                         #clock-cells = <0>;
 168                         compatible = "fixed-clock";
 169                         clock-frequency = <24000000>;
 170                         clock-output-names = "osc24M";
 171                 };
 172
 173                 osc32k: clk-32k {
 174                         #clock-cells = <0>;
 175                         compatible = "fixed-clock";
 176                         clock-frequency = <32768>;
 177                         clock-output-names = "osc32k";
 178                 };
 179         };
 180
 181         de: display-engine {
 182                 compatible = "allwinner,sun4i-a10-display-engine";
 183                 allwinner,pipelines = <&fe0>, <&fe1>;
 184                 status = "disabled";
 185         };
 186
 187         pmu {
 188                 compatible = "arm,cortex-a8-pmu";
 189                 interrupts = <3>;
 190         };
 191
 192         reserved-memory {
 193                 #address-cells = <1>;
 194                 #size-cells = <1>;
 195                 ranges;
 196
 197                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 198                 default-pool {
 199                         compatible = "shared-dma-pool";
 200                         size = <0x6000000>;
 201                         alloc-ranges = <0x4a000000 0x6000000>;
 202                         reusable;
 203                         linux,cma-default;
 204                 };
 205         };
 206
 207         soc {
 208                 compatible = "simple-bus";
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 ranges;
 212
 213                 system-control@1c00000 {
 214                         compatible = "allwinner,sun4i-a10-system-control";
 215                         reg = <0x01c00000 0x30>;
 216                         #address-cells = <1>;
 217                         #size-cells = <1>;
 218                         ranges;
 219
 220                         sram_a: sram@0 {
 221                                 compatible = "mmio-sram";
 222                                 reg = <0x00000000 0xc000>;
 223                                 #address-cells = <1>;
 224                                 #size-cells = <1>;
 225                                 ranges = <0 0x00000000 0xc000>;
 226
 227                                 emac_sram: sram-section@8000 {
 228                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 229                                         reg = <0x8000 0x4000>;
 230                                         status = "disabled";
 231                                 };
 232                         };
 233
 234                         sram_d: sram@10000 {
 235                                 compatible = "mmio-sram";
 236                                 reg = <0x00010000 0x1000>;
 237                                 #address-cells = <1>;
 238                                 #size-cells = <1>;
 239                                 ranges = <0 0x00010000 0x1000>;
 240
 241                                 otg_sram: sram-section@0 {
 242                                         compatible = "allwinner,sun4i-a10-sram-d";
 243                                         reg = <0x0000 0x1000>;
 244                                         status = "disabled";
 245                                 };
 246                         };
 247
 248                         sram_c: sram@1d00000 {
 249                                 compatible = "mmio-sram";
 250                                 reg = <0x01d00000 0xd0000>;
 251                                 #address-cells = <1>;
 252                                 #size-cells = <1>;
 253                                 ranges = <0 0x01d00000 0xd0000>;
 254
 255                                 ve_sram: sram-section@0 {
 256                                         compatible = "allwinner,sun4i-a10-sram-c1";
 257                                         reg = <0x000000 0x80000>;
 258                                 };
 259                         };
 260                 };
 261
 262                 dma: dma-controller@1c02000 {
 263                         compatible = "allwinner,sun4i-a10-dma";
 264                         reg = <0x01c02000 0x1000>;
 265                         interrupts = <27>;
 266                         clocks = <&ccu CLK_AHB_DMA>;
 267                         #dma-cells = <2>;
 268                 };
 269
 270                 nfc: nand@1c03000 {
 271                         compatible = "allwinner,sun4i-a10-nand";
 272                         reg = <0x01c03000 0x1000>;
 273                         interrupts = <37>;
 274                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 275                         clock-names = "ahb", "mod";
 276                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 277                         dma-names = "rxtx";
 278                         status = "disabled";
 279                         #address-cells = <1>;
 280                         #size-cells = <0>;
 281                 };
 282
 283                 spi0: spi@1c05000 {
 284                         compatible = "allwinner,sun4i-a10-spi";
 285                         reg = <0x01c05000 0x1000>;
 286                         interrupts = <10>;
 287                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 288                         clock-names = "ahb", "mod";
 289                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 290                                <&dma SUN4I_DMA_DEDICATED 26>;
 291                         dma-names = "rx", "tx";
 292                         status = "disabled";
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                 };
 296
 297                 spi1: spi@1c06000 {
 298                         compatible = "allwinner,sun4i-a10-spi";
 299                         reg = <0x01c06000 0x1000>;
 300                         interrupts = <11>;
 301                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 302                         clock-names = "ahb", "mod";
 303                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 304                                <&dma SUN4I_DMA_DEDICATED 8>;
 305                         dma-names = "rx", "tx";
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
 308                         status = "disabled";
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                 };
 312
 313                 emac: ethernet@1c0b000 {
 314                         compatible = "allwinner,sun4i-a10-emac";
 315                         reg = <0x01c0b000 0x1000>;
 316                         interrupts = <55>;
 317                         clocks = <&ccu CLK_AHB_EMAC>;
 318                         allwinner,sram = <&emac_sram 1>;
 319                         pinctrl-names = "default";
 320                         pinctrl-0 = <&emac_pins>;
 321                         status = "disabled";
 322                 };
 323
 324                 mdio: mdio@1c0b080 {
 325                         compatible = "allwinner,sun4i-a10-mdio";
 326                         reg = <0x01c0b080 0x14>;
 327                         status = "disabled";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                 };
 331
 332                 tcon0: lcd-controller@1c0c000 {
 333                         compatible = "allwinner,sun4i-a10-tcon";
 334                         reg = <0x01c0c000 0x1000>;
 335                         interrupts = <44>;
 336                         resets = <&ccu RST_TCON0>;
 337                         reset-names = "lcd";
 338                         clocks = <&ccu CLK_AHB_LCD0>,
 339                                  <&ccu CLK_TCON0_CH0>,
 340                                  <&ccu CLK_TCON0_CH1>;
 341                         clock-names = "ahb",
 342                                       "tcon-ch0",
 343                                       "tcon-ch1";
 344                         clock-output-names = "tcon0-pixel-clock";
 345                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 346
 347                         ports {
 348                                 #address-cells = <1>;
 349                                 #size-cells = <0>;
 350
 351                                 tcon0_in: port@0 {
 352                                         #address-cells = <1>;
 353                                         #size-cells = <0>;
 354                                         reg = <0>;
 355
 356                                         tcon0_in_be0: endpoint@0 {
 357                                                 reg = <0>;
 358                                                 remote-endpoint = <&be0_out_tcon0>;
 359                                         };
 360
 361                                         tcon0_in_be1: endpoint@1 {
 362                                                 reg = <1>;
 363                                                 remote-endpoint = <&be1_out_tcon0>;
 364                                         };
 365                                 };
 366
 367                                 tcon0_out: port@1 {
 368                                         #address-cells = <1>;
 369                                         #size-cells = <0>;
 370                                         reg = <1>;
 371
 372                                         tcon0_out_hdmi: endpoint@1 {
 373                                                 reg = <1>;
 374                                                 remote-endpoint = <&hdmi_in_tcon0>;
 375                                                 allwinner,tcon-channel = <1>;
 376                                         };
 377                                 };
 378                         };
 379                 };
 380
 381                 tcon1: lcd-controller@1c0d000 {
 382                         compatible = "allwinner,sun4i-a10-tcon";
 383                         reg = <0x01c0d000 0x1000>;
 384                         interrupts = <45>;
 385                         resets = <&ccu RST_TCON1>;
 386                         reset-names = "lcd";
 387                         clocks = <&ccu CLK_AHB_LCD1>,
 388                                  <&ccu CLK_TCON1_CH0>,
 389                                  <&ccu CLK_TCON1_CH1>;
 390                         clock-names = "ahb",
 391                                       "tcon-ch0",
 392                                       "tcon-ch1";
 393                         clock-output-names = "tcon1-pixel-clock";
 394                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 395
 396                         ports {
 397                                 #address-cells = <1>;
 398                                 #size-cells = <0>;
 399
 400                                 tcon1_in: port@0 {
 401                                         #address-cells = <1>;
 402                                         #size-cells = <0>;
 403                                         reg = <0>;
 404
 405                                         tcon1_in_be0: endpoint@0 {
 406                                                 reg = <0>;
 407                                                 remote-endpoint = <&be0_out_tcon1>;
 408                                         };
 409
 410                                         tcon1_in_be1: endpoint@1 {
 411                                                 reg = <1>;
 412                                                 remote-endpoint = <&be1_out_tcon1>;
 413                                         };
 414                                 };
 415
 416                                 tcon1_out: port@1 {
 417                                         #address-cells = <1>;
 418                                         #size-cells = <0>;
 419                                         reg = <1>;
 420
 421                                         tcon1_out_hdmi: endpoint@1 {
 422                                                 reg = <1>;
 423                                                 remote-endpoint = <&hdmi_in_tcon1>;
 424                                                 allwinner,tcon-channel = <1>;
 425                                         };
 426                                 };
 427                         };
 428                 };
 429
 430                 video-codec@1c0e000 {
 431                         compatible = "allwinner,sun4i-a10-video-engine";
 432                         reg = <0x01c0e000 0x1000>;
 433                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 434                                  <&ccu CLK_DRAM_VE>;
 435                         clock-names = "ahb", "mod", "ram";
 436                         resets = <&ccu RST_VE>;
 437                         interrupts = <53>;
 438                         allwinner,sram = <&ve_sram 1>;
 439                 };
 440
 441                 mmc0: mmc@1c0f000 {
 442                         compatible = "allwinner,sun4i-a10-mmc";
 443                         reg = <0x01c0f000 0x1000>;
 444                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 445                         clock-names = "ahb", "mmc";
 446                         interrupts = <32>;
 447                         pinctrl-names = "default";
 448                         pinctrl-0 = <&mmc0_pins>;
 449                         status = "disabled";
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                 };
 453
 454                 mmc1: mmc@1c10000 {
 455                         compatible = "allwinner,sun4i-a10-mmc";
 456                         reg = <0x01c10000 0x1000>;
 457                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 458                         clock-names = "ahb", "mmc";
 459                         interrupts = <33>;
 460                         status = "disabled";
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                 };
 464
 465                 mmc2: mmc@1c11000 {
 466                         compatible = "allwinner,sun4i-a10-mmc";
 467                         reg = <0x01c11000 0x1000>;
 468                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 469                         clock-names = "ahb", "mmc";
 470                         interrupts = <34>;
 471                         status = "disabled";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 mmc3: mmc@1c12000 {
 477                         compatible = "allwinner,sun4i-a10-mmc";
 478                         reg = <0x01c12000 0x1000>;
 479                         clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
 480                         clock-names = "ahb", "mmc";
 481                         interrupts = <35>;
 482                         status = "disabled";
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                 };
 486
 487                 usb_otg: usb@1c13000 {
 488                         compatible = "allwinner,sun4i-a10-musb";
 489                         reg = <0x01c13000 0x0400>;
 490                         clocks = <&ccu CLK_AHB_OTG>;
 491                         interrupts = <38>;
 492                         interrupt-names = "mc";
 493                         phys = <&usbphy 0>;
 494                         phy-names = "usb";
 495                         extcon = <&usbphy 0>;
 496                         allwinner,sram = <&otg_sram 1>;
 497                         status = "disabled";
 498                 };
 499
 500                 usbphy: phy@1c13400 {
 501                         #phy-cells = <1>;
 502                         compatible = "allwinner,sun4i-a10-usb-phy";
 503                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 504                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 505                         clocks = <&ccu CLK_USB_PHY>;
 506                         clock-names = "usb_phy";
 507                         resets = <&ccu RST_USB_PHY0>,
 508                                  <&ccu RST_USB_PHY1>,
 509                                  <&ccu RST_USB_PHY2>;
 510                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 511                         status = "disabled";
 512                 };
 513
 514                 ehci0: usb@1c14000 {
 515                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 516                         reg = <0x01c14000 0x100>;
 517                         interrupts = <39>;
 518                         clocks = <&ccu CLK_AHB_EHCI0>;
 519                         phys = <&usbphy 1>;
 520                         phy-names = "usb";
 521                         status = "disabled";
 522                 };
 523
 524                 ohci0: usb@1c14400 {
 525                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 526                         reg = <0x01c14400 0x100>;
 527                         interrupts = <64>;
 528                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 529                         phys = <&usbphy 1>;
 530                         phy-names = "usb";
 531                         status = "disabled";
 532                 };
 533
 534                 crypto: crypto-engine@1c15000 {
 535                         compatible = "allwinner,sun4i-a10-crypto";
 536                         reg = <0x01c15000 0x1000>;
 537                         interrupts = <86>;
 538                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 539                         clock-names = "ahb", "mod";
 540                 };
 541
 542                 hdmi: hdmi@1c16000 {
 543                         compatible = "allwinner,sun4i-a10-hdmi";
 544                         reg = <0x01c16000 0x1000>;
 545                         interrupts = <58>;
 546                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 547                                  <&ccu CLK_PLL_VIDEO0_2X>,
 548                                  <&ccu CLK_PLL_VIDEO1_2X>;
 549                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 550                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 551                                <&dma SUN4I_DMA_NORMAL 16>,
 552                                <&dma SUN4I_DMA_DEDICATED 24>;
 553                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 554                         status = "disabled";
 555
 556                         ports {
 557                                 #address-cells = <1>;
 558                                 #size-cells = <0>;
 559
 560                                 hdmi_in: port@0 {
 561                                         #address-cells = <1>;
 562                                         #size-cells = <0>;
 563                                         reg = <0>;
 564
 565                                         hdmi_in_tcon0: endpoint@0 {
 566                                                 reg = <0>;
 567                                                 remote-endpoint = <&tcon0_out_hdmi>;
 568                                         };
 569
 570                                         hdmi_in_tcon1: endpoint@1 {
 571                                                 reg = <1>;
 572                                                 remote-endpoint = <&tcon1_out_hdmi>;
 573                                         };
 574                                 };
 575
 576                                 hdmi_out: port@1 {
 577                                         reg = <1>;
 578                                 };
 579                         };
 580                 };
 581
 582                 spi2: spi@1c17000 {
 583                         compatible = "allwinner,sun4i-a10-spi";
 584                         reg = <0x01c17000 0x1000>;
 585                         interrupts = <12>;
 586                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 587                         clock-names = "ahb", "mod";
 588                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 589                                <&dma SUN4I_DMA_DEDICATED 28>;
 590                         dma-names = "rx", "tx";
 591                         status = "disabled";
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                 };
 595
 596                 ahci: sata@1c18000 {
 597                         compatible = "allwinner,sun4i-a10-ahci";
 598                         reg = <0x01c18000 0x1000>;
 599                         interrupts = <56>;
 600                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 601                         status = "disabled";
 602                 };
 603
 604                 ehci1: usb@1c1c000 {
 605                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 606                         reg = <0x01c1c000 0x100>;
 607                         interrupts = <40>;
 608                         clocks = <&ccu CLK_AHB_EHCI1>;
 609                         phys = <&usbphy 2>;
 610                         phy-names = "usb";
 611                         status = "disabled";
 612                 };
 613
 614                 ohci1: usb@1c1c400 {
 615                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 616                         reg = <0x01c1c400 0x100>;
 617                         interrupts = <65>;
 618                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 619                         phys = <&usbphy 2>;
 620                         phy-names = "usb";
 621                         status = "disabled";
 622                 };
 623
 624                 spi3: spi@1c1f000 {
 625                         compatible = "allwinner,sun4i-a10-spi";
 626                         reg = <0x01c1f000 0x1000>;
 627                         interrupts = <50>;
 628                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 629                         clock-names = "ahb", "mod";
 630                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 631                                <&dma SUN4I_DMA_DEDICATED 30>;
 632                         dma-names = "rx", "tx";
 633                         status = "disabled";
 634                         #address-cells = <1>;
 635                         #size-cells = <0>;
 636                 };
 637
 638                 ccu: clock@1c20000 {
 639                         compatible = "allwinner,sun4i-a10-ccu";
 640                         reg = <0x01c20000 0x400>;
 641                         clocks = <&osc24M>, <&osc32k>;
 642                         clock-names = "hosc", "losc";
 643                         #clock-cells = <1>;
 644                         #reset-cells = <1>;
 645                 };
 646
 647                 intc: interrupt-controller@1c20400 {
 648                         compatible = "allwinner,sun4i-a10-ic";
 649                         reg = <0x01c20400 0x400>;
 650                         interrupt-controller;
 651                         #interrupt-cells = <1>;
 652                 };
 653
 654                 pio: pinctrl@1c20800 {
 655                         compatible = "allwinner,sun4i-a10-pinctrl";
 656                         reg = <0x01c20800 0x400>;
 657                         interrupts = <28>;
 658                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 659                         clock-names = "apb", "hosc", "losc";
 660                         gpio-controller;
 661                         interrupt-controller;
 662                         #interrupt-cells = <3>;
 663                         #gpio-cells = <3>;
 664
 665                         can0_ph_pins: can0-ph-pins {
 666                                 pins = "PH20", "PH21";
 667                                 function = "can";
 668                         };
 669
 670                         emac_pins: emac0-pins {
 671                                 pins = "PA0", "PA1", "PA2",
 672                                        "PA3", "PA4", "PA5", "PA6",
 673                                        "PA7", "PA8", "PA9", "PA10",
 674                                        "PA11", "PA12", "PA13", "PA14",
 675                                        "PA15", "PA16";
 676                                 function = "emac";
 677                         };
 678
 679                         i2c0_pins: i2c0-pins {
 680                                 pins = "PB0", "PB1";
 681                                 function = "i2c0";
 682                         };
 683
 684                         i2c1_pins: i2c1-pins {
 685                                 pins = "PB18", "PB19";
 686                                 function = "i2c1";
 687                         };
 688
 689                         i2c2_pins: i2c2-pins {
 690                                 pins = "PB20", "PB21";
 691                                 function = "i2c2";
 692                         };
 693
 694                         ir0_rx_pins: ir0-rx-pin {
 695                                 pins = "PB4";
 696                                 function = "ir0";
 697                         };
 698
 699                         ir0_tx_pins: ir0-tx-pin {
 700                                 pins = "PB3";
 701                                 function = "ir0";
 702                         };
 703
 704                         ir1_rx_pins: ir1-rx-pin {
 705                                 pins = "PB23";
 706                                 function = "ir1";
 707                         };
 708
 709                         ir1_tx_pins: ir1-tx-pin {
 710                                 pins = "PB22";
 711                                 function = "ir1";
 712                         };
 713
 714                         mmc0_pins: mmc0-pins {
 715                                 pins = "PF0", "PF1", "PF2",
 716                                        "PF3", "PF4", "PF5";
 717                                 function = "mmc0";
 718                                 drive-strength = <30>;
 719                                 bias-pull-up;
 720                         };
 721
 722                         ps2_ch0_pins: ps2-ch0-pins {
 723                                 pins = "PI20", "PI21";
 724                                 function = "ps2";
 725                         };
 726
 727                         ps2_ch1_ph_pins: ps2-ch1-ph-pins {
 728                                 pins = "PH12", "PH13";
 729                                 function = "ps2";
 730                         };
 731
 732                         pwm0_pin: pwm0-pin {
 733                                 pins = "PB2";
 734                                 function = "pwm";
 735                         };
 736
 737                         pwm1_pin: pwm1-pin {
 738                                 pins = "PI3";
 739                                 function = "pwm";
 740                         };
 741
 742                         spdif_tx_pin: spdif-tx-pin {
 743                                 pins = "PB13";
 744                                 function = "spdif";
 745                                 bias-pull-up;
 746                         };
 747
 748                         spi0_pi_pins: spi0-pi-pins {
 749                                 pins = "PI11", "PI12", "PI13";
 750                                 function = "spi0";
 751                         };
 752
 753                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 754                                 pins = "PI10";
 755                                 function = "spi0";
 756                         };
 757
 758                         spi1_pins: spi1-pins {
 759                                 pins = "PI17", "PI18", "PI19";
 760                                 function = "spi1";
 761                         };
 762
 763                         spi1_cs0_pin: spi1-cs0-pin {
 764                                 pins = "PI16";
 765                                 function = "spi1";
 766                         };
 767
 768                         spi2_pb_pins: spi2-pb-pins {
 769                                 pins = "PB15", "PB16", "PB17";
 770                                 function = "spi2";
 771                         };
 772
 773                         spi2_pc_pins: spi2-pc-pins {
 774                                 pins = "PC20", "PC21", "PC22";
 775                                 function = "spi2";
 776                         };
 777
 778                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 779                                 pins = "PB14";
 780                                 function = "spi2";
 781                         };
 782
 783                         spi2_cs0_pc_pins: spi2-cs0-pc-pin {
 784                                 pins = "PC19";
 785                                 function = "spi2";
 786                         };
 787
 788                         uart0_pb_pins: uart0-pb-pins {
 789                                 pins = "PB22", "PB23";
 790                                 function = "uart0";
 791                         };
 792
 793                         uart0_pf_pins: uart0-pf-pins {
 794                                 pins = "PF2", "PF4";
 795                                 function = "uart0";
 796                         };
 797
 798                         uart1_pins: uart1-pins {
 799                                 pins = "PA10", "PA11";
 800                                 function = "uart1";
 801                         };
 802                 };
 803
 804                 timer@1c20c00 {
 805                         compatible = "allwinner,sun4i-a10-timer";
 806                         reg = <0x01c20c00 0x90>;
 807                         interrupts = <22>;
 808                         clocks = <&osc24M>;
 809                 };
 810
 811                 wdt: watchdog@1c20c90 {
 812                         compatible = "allwinner,sun4i-a10-wdt";
 813                         reg = <0x01c20c90 0x10>;
 814                 };
 815
 816                 rtc: rtc@1c20d00 {
 817                         compatible = "allwinner,sun4i-a10-rtc";
 818                         reg = <0x01c20d00 0x20>;
 819                         interrupts = <24>;
 820                 };
 821
 822                 pwm: pwm@1c20e00 {
 823                         compatible = "allwinner,sun4i-a10-pwm";
 824                         reg = <0x01c20e00 0xc>;
 825                         clocks = <&osc24M>;
 826                         #pwm-cells = <3>;
 827                         status = "disabled";
 828                 };
 829
 830                 spdif: spdif@1c21000 {
 831                         #sound-dai-cells = <0>;
 832                         compatible = "allwinner,sun4i-a10-spdif";
 833                         reg = <0x01c21000 0x400>;
 834                         interrupts = <13>;
 835                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
 836                         clock-names = "apb", "spdif";
 837                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
 838                                <&dma SUN4I_DMA_NORMAL 2>;
 839                         dma-names = "rx", "tx";
 840                         status = "disabled";
 841                 };
 842
 843                 ir0: ir@1c21800 {
 844                         compatible = "allwinner,sun4i-a10-ir";
 845                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
 846                         clock-names = "apb", "ir";
 847                         interrupts = <5>;
 848                         reg = <0x01c21800 0x40>;
 849                         status = "disabled";
 850                 };
 851
 852                 ir1: ir@1c21c00 {
 853                         compatible = "allwinner,sun4i-a10-ir";
 854                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
 855                         clock-names = "apb", "ir";
 856                         interrupts = <6>;
 857                         reg = <0x01c21c00 0x40>;
 858                         status = "disabled";
 859                 };
 860
 861                 i2s0: i2s@1c22400 {
 862                         #sound-dai-cells = <0>;
 863                         compatible = "allwinner,sun4i-a10-i2s";
 864                         reg = <0x01c22400 0x400>;
 865                         interrupts = <16>;
 866                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
 867                         clock-names = "apb", "mod";
 868                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
 869                                <&dma SUN4I_DMA_NORMAL 3>;
 870                         dma-names = "rx", "tx";
 871                         status = "disabled";
 872                 };
 873
 874                 lradc: lradc@1c22800 {
 875                         compatible = "allwinner,sun4i-a10-lradc-keys";
 876                         reg = <0x01c22800 0x100>;
 877                         interrupts = <31>;
 878                         status = "disabled";
 879                 };
 880
 881                 codec: codec@1c22c00 {
 882                         #sound-dai-cells = <0>;
 883                         compatible = "allwinner,sun4i-a10-codec";
 884                         reg = <0x01c22c00 0x40>;
 885                         interrupts = <30>;
 886                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 887                         clock-names = "apb", "codec";
 888                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 889                                <&dma SUN4I_DMA_NORMAL 19>;
 890                         dma-names = "rx", "tx";
 891                         status = "disabled";
 892                 };
 893
 894                 sid: eeprom@1c23800 {
 895                         compatible = "allwinner,sun4i-a10-sid";
 896                         reg = <0x01c23800 0x10>;
 897                 };
 898
 899                 rtp: rtp@1c25000 {
 900                         compatible = "allwinner,sun4i-a10-ts";
 901                         reg = <0x01c25000 0x100>;
 902                         interrupts = <29>;
 903                         #thermal-sensor-cells = <0>;
 904                 };
 905
 906                 uart0: serial@1c28000 {
 907                         compatible = "snps,dw-apb-uart";
 908                         reg = <0x01c28000 0x400>;
 909                         interrupts = <1>;
 910                         reg-shift = <2>;
 911                         reg-io-width = <4>;
 912                         clocks = <&ccu CLK_APB1_UART0>;
 913                         status = "disabled";
 914                 };
 915
 916                 uart1: serial@1c28400 {
 917                         compatible = "snps,dw-apb-uart";
 918                         reg = <0x01c28400 0x400>;
 919                         interrupts = <2>;
 920                         reg-shift = <2>;
 921                         reg-io-width = <4>;
 922                         clocks = <&ccu CLK_APB1_UART1>;
 923                         status = "disabled";
 924                 };
 925
 926                 uart2: serial@1c28800 {
 927                         compatible = "snps,dw-apb-uart";
 928                         reg = <0x01c28800 0x400>;
 929                         interrupts = <3>;
 930                         reg-shift = <2>;
 931                         reg-io-width = <4>;
 932                         clocks = <&ccu CLK_APB1_UART2>;
 933                         status = "disabled";
 934                 };
 935
 936                 uart3: serial@1c28c00 {
 937                         compatible = "snps,dw-apb-uart";
 938                         reg = <0x01c28c00 0x400>;
 939                         interrupts = <4>;
 940                         reg-shift = <2>;
 941                         reg-io-width = <4>;
 942                         clocks = <&ccu CLK_APB1_UART3>;
 943                         status = "disabled";
 944                 };
 945
 946                 uart4: serial@1c29000 {
 947                         compatible = "snps,dw-apb-uart";
 948                         reg = <0x01c29000 0x400>;
 949                         interrupts = <17>;
 950                         reg-shift = <2>;
 951                         reg-io-width = <4>;
 952                         clocks = <&ccu CLK_APB1_UART4>;
 953                         status = "disabled";
 954                 };
 955
 956                 uart5: serial@1c29400 {
 957                         compatible = "snps,dw-apb-uart";
 958                         reg = <0x01c29400 0x400>;
 959                         interrupts = <18>;
 960                         reg-shift = <2>;
 961                         reg-io-width = <4>;
 962                         clocks = <&ccu CLK_APB1_UART5>;
 963                         status = "disabled";
 964                 };
 965
 966                 uart6: serial@1c29800 {
 967                         compatible = "snps,dw-apb-uart";
 968                         reg = <0x01c29800 0x400>;
 969                         interrupts = <19>;
 970                         reg-shift = <2>;
 971                         reg-io-width = <4>;
 972                         clocks = <&ccu CLK_APB1_UART6>;
 973                         status = "disabled";
 974                 };
 975
 976                 uart7: serial@1c29c00 {
 977                         compatible = "snps,dw-apb-uart";
 978                         reg = <0x01c29c00 0x400>;
 979                         interrupts = <20>;
 980                         reg-shift = <2>;
 981                         reg-io-width = <4>;
 982                         clocks = <&ccu CLK_APB1_UART7>;
 983                         status = "disabled";
 984                 };
 985
 986                 ps20: ps2@1c2a000 {
 987                         compatible = "allwinner,sun4i-a10-ps2";
 988                         reg = <0x01c2a000 0x400>;
 989                         interrupts = <62>;
 990                         clocks = <&ccu CLK_APB1_PS20>;
 991                         status = "disabled";
 992                 };
 993
 994                 ps21: ps2@1c2a400 {
 995                         compatible = "allwinner,sun4i-a10-ps2";
 996                         reg = <0x01c2a400 0x400>;
 997                         interrupts = <63>;
 998                         clocks = <&ccu CLK_APB1_PS21>;
 999                         status = "disabled";
1000                 };
1001
1002                 i2c0: i2c@1c2ac00 {
1003                         compatible = "allwinner,sun4i-a10-i2c";
1004                         reg = <0x01c2ac00 0x400>;
1005                         interrupts = <7>;
1006                         clocks = <&ccu CLK_APB1_I2C0>;
1007                         pinctrl-names = "default";
1008                         pinctrl-0 = <&i2c0_pins>;
1009                         status = "disabled";
1010                         #address-cells = <1>;
1011                         #size-cells = <0>;
1012                 };
1013
1014                 i2c1: i2c@1c2b000 {
1015                         compatible = "allwinner,sun4i-a10-i2c";
1016                         reg = <0x01c2b000 0x400>;
1017                         interrupts = <8>;
1018                         clocks = <&ccu CLK_APB1_I2C1>;
1019                         pinctrl-names = "default";
1020                         pinctrl-0 = <&i2c1_pins>;
1021                         status = "disabled";
1022                         #address-cells = <1>;
1023                         #size-cells = <0>;
1024                 };
1025
1026                 i2c2: i2c@1c2b400 {
1027                         compatible = "allwinner,sun4i-a10-i2c";
1028                         reg = <0x01c2b400 0x400>;
1029                         interrupts = <9>;
1030                         clocks = <&ccu CLK_APB1_I2C2>;
1031                         pinctrl-names = "default";
1032                         pinctrl-0 = <&i2c2_pins>;
1033                         status = "disabled";
1034                         #address-cells = <1>;
1035                         #size-cells = <0>;
1036                 };
1037
1038                 can0: can@1c2bc00 {
1039                         compatible = "allwinner,sun4i-a10-can";
1040                         reg = <0x01c2bc00 0x400>;
1041                         interrupts = <26>;
1042                         clocks = <&ccu CLK_APB1_CAN>;
1043                         status = "disabled";
1044                 };
1045
1046                 mali: gpu@1c40000 {
1047                         compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1048                         reg = <0x01c40000 0x10000>;
1049                         interrupts = <69>,
1050                                      <70>,
1051                                      <71>,
1052                                      <72>,
1053                                      <73>;
1054                         interrupt-names = "gp",
1055                                           "gpmmu",
1056                                           "pp0",
1057                                           "ppmmu0",
1058                                           "pmu";
1059                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1060                         clock-names = "bus", "core";
1061                         resets = <&ccu RST_GPU>;
1062
1063                         assigned-clocks = <&ccu CLK_GPU>;
1064                         assigned-clock-rates = <384000000>;
1065                 };
1066
1067                 fe0: display-frontend@1e00000 {
1068                         compatible = "allwinner,sun4i-a10-display-frontend";
1069                         reg = <0x01e00000 0x20000>;
1070                         interrupts = <47>;
1071                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1072                                  <&ccu CLK_DRAM_DE_FE0>;
1073                         clock-names = "ahb", "mod",
1074                                       "ram";
1075                         resets = <&ccu RST_DE_FE0>;
1076
1077                         ports {
1078                                 #address-cells = <1>;
1079                                 #size-cells = <0>;
1080
1081                                 fe0_out: port@1 {
1082                                         #address-cells = <1>;
1083                                         #size-cells = <0>;
1084                                         reg = <1>;
1085
1086                                         fe0_out_be0: endpoint@0 {
1087                                                 reg = <0>;
1088                                                 remote-endpoint = <&be0_in_fe0>;
1089                                         };
1090
1091                                         fe0_out_be1: endpoint@1 {
1092                                                 reg = <1>;
1093                                                 remote-endpoint = <&be1_in_fe0>;
1094                                         };
1095                                 };
1096                         };
1097                 };
1098
1099                 fe1: display-frontend@1e20000 {
1100                         compatible = "allwinner,sun4i-a10-display-frontend";
1101                         reg = <0x01e20000 0x20000>;
1102                         interrupts = <48>;
1103                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1104                                  <&ccu CLK_DRAM_DE_FE1>;
1105                         clock-names = "ahb", "mod",
1106                                       "ram";
1107                         resets = <&ccu RST_DE_FE1>;
1108
1109                         ports {
1110                                 #address-cells = <1>;
1111                                 #size-cells = <0>;
1112
1113                                 fe1_out: port@1 {
1114                                         #address-cells = <1>;
1115                                         #size-cells = <0>;
1116                                         reg = <1>;
1117
1118                                         fe1_out_be0: endpoint@0 {
1119                                                 reg = <0>;
1120                                                 remote-endpoint = <&be0_in_fe1>;
1121                                         };
1122
1123                                         fe1_out_be1: endpoint@1 {
1124                                                 reg = <1>;
1125                                                 remote-endpoint = <&be1_in_fe1>;
1126                                         };
1127                                 };
1128                         };
1129                 };
1130
1131                 be1: display-backend@1e40000 {
1132                         compatible = "allwinner,sun4i-a10-display-backend";
1133                         reg = <0x01e40000 0x10000>;
1134                         interrupts = <48>;
1135                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1136                                  <&ccu CLK_DRAM_DE_BE1>;
1137                         clock-names = "ahb", "mod",
1138                                       "ram";
1139                         resets = <&ccu RST_DE_BE1>;
1140
1141                         ports {
1142                                 #address-cells = <1>;
1143                                 #size-cells = <0>;
1144
1145                                 be1_in: port@0 {
1146                                         #address-cells = <1>;
1147                                         #size-cells = <0>;
1148                                         reg = <0>;
1149
1150                                         be1_in_fe0: endpoint@0 {
1151                                                 reg = <0>;
1152                                                 remote-endpoint = <&fe0_out_be1>;
1153                                         };
1154
1155                                         be1_in_fe1: endpoint@1 {
1156                                                 reg = <1>;
1157                                                 remote-endpoint = <&fe1_out_be1>;
1158                                         };
1159                                 };
1160
1161                                 be1_out: port@1 {
1162                                         #address-cells = <1>;
1163                                         #size-cells = <0>;
1164                                         reg = <1>;
1165
1166                                         be1_out_tcon0: endpoint@0 {
1167                                                 reg = <0>;
1168                                                 remote-endpoint = <&tcon0_in_be1>;
1169                                         };
1170
1171                                         be1_out_tcon1: endpoint@1 {
1172                                                 reg = <1>;
1173                                                 remote-endpoint = <&tcon1_in_be1>;
1174                                         };
1175                                 };
1176                         };
1177                 };
1178
1179                 be0: display-backend@1e60000 {
1180                         compatible = "allwinner,sun4i-a10-display-backend";
1181                         reg = <0x01e60000 0x10000>;
1182                         interrupts = <47>;
1183                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1184                                  <&ccu CLK_DRAM_DE_BE0>;
1185                         clock-names = "ahb", "mod",
1186                                       "ram";
1187                         resets = <&ccu RST_DE_BE0>;
1188
1189                         ports {
1190                                 #address-cells = <1>;
1191                                 #size-cells = <0>;
1192
1193                                 be0_in: port@0 {
1194                                         #address-cells = <1>;
1195                                         #size-cells = <0>;
1196                                         reg = <0>;
1197
1198                                         be0_in_fe0: endpoint@0 {
1199                                                 reg = <0>;
1200                                                 remote-endpoint = <&fe0_out_be0>;
1201                                         };
1202
1203                                         be0_in_fe1: endpoint@1 {
1204                                                 reg = <1>;
1205                                                 remote-endpoint = <&fe1_out_be0>;
1206                                         };
1207                                 };
1208
1209                                 be0_out: port@1 {
1210                                         #address-cells = <1>;
1211                                         #size-cells = <0>;
1212                                         reg = <1>;
1213
1214                                         be0_out_tcon0: endpoint@0 {
1215                                                 reg = <0>;
1216                                                 remote-endpoint = <&tcon0_in_be0>;
1217                                         };
1218
1219                                         be0_out_tcon1: endpoint@1 {
1220                                                 reg = <1>;
1221                                                 remote-endpoint = <&tcon1_in_be0>;
1222                                         };
1223                                 };
1224                         };
1225                 };
1226         };
1227 };