arch/arm/boot/dts/stm32mp157c.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci";
  33                 method = "smc";
  34                 cpu_off = <0x84000002>;
  35                 cpu_on = <0x84000003>;
  36         };
  37
  38         intc: interrupt-controller@a0021000 {
  39                 compatible = "arm,cortex-a7-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xa0021000 0x1000>,
  43                       <0xa0022000 0x2000>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&intc>;
  53         };
  54
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61
  62                 clk_hsi: clk-hsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <64000000>;
  66                 };
  67
  68                 clk_lse: clk-lse {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 clk_lsi: clk-lsi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <32000>;
  78                 };
  79
  80                 clk_csi: clk-csi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <4000000>;
  84                 };
  85         };
  86
  87         thermal-zones {
  88                 cpu_thermal: cpu-thermal {
  89                         polling-delay-passive = <0>;
  90                         polling-delay = <0>;
  91                         thermal-sensors = <&dts>;
  92
  93                         trips {
  94                                 cpu_alert1: cpu-alert1 {
  95                                         temperature = <85000>;
  96                                         hysteresis = <0>;
  97                                         type = "passive";
  98                                 };
  99
 100                                 cpu-crit {
 101                                         temperature = <120000>;
 102                                         hysteresis = <0>;
 103                                         type = "critical";
 104                                 };
 105                         };
 106
 107                         cooling-maps {
 108                         };
 109                 };
 110         };
 111
 112         soc {
 113                 compatible = "simple-bus";
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 interrupt-parent = <&intc>;
 117                 ranges;
 118
 119                 timers2: timer@40000000 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         compatible = "st,stm32-timers";
 123                         reg = <0x40000000 0x400>;
 124                         clocks = <&rcc TIM2_K>;
 125                         clock-names = "int";
 126                         dmas = <&dmamux1 18 0x400 0x1>,
 127                                <&dmamux1 19 0x400 0x1>,
 128                                <&dmamux1 20 0x400 0x1>,
 129                                <&dmamux1 21 0x400 0x1>,
 130                                <&dmamux1 22 0x400 0x1>;
 131                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 132                         status = "disabled";
 133
 134                         pwm {
 135                                 compatible = "st,stm32-pwm";
 136                                 status = "disabled";
 137                         };
 138
 139                         timer@1 {
 140                                 compatible = "st,stm32h7-timer-trigger";
 141                                 reg = <1>;
 142                                 status = "disabled";
 143                         };
 144                 };
 145
 146                 timers3: timer@40001000 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         compatible = "st,stm32-timers";
 150                         reg = <0x40001000 0x400>;
 151                         clocks = <&rcc TIM3_K>;
 152                         clock-names = "int";
 153                         dmas = <&dmamux1 23 0x400 0x1>,
 154                                <&dmamux1 24 0x400 0x1>,
 155                                <&dmamux1 25 0x400 0x1>,
 156                                <&dmamux1 26 0x400 0x1>,
 157                                <&dmamux1 27 0x400 0x1>,
 158                                <&dmamux1 28 0x400 0x1>;
 159                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 160                         status = "disabled";
 161
 162                         pwm {
 163                                 compatible = "st,stm32-pwm";
 164                                 status = "disabled";
 165                         };
 166
 167                         timer@2 {
 168                                 compatible = "st,stm32h7-timer-trigger";
 169                                 reg = <2>;
 170                                 status = "disabled";
 171                         };
 172                 };
 173
 174                 timers4: timer@40002000 {
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         compatible = "st,stm32-timers";
 178                         reg = <0x40002000 0x400>;
 179                         clocks = <&rcc TIM4_K>;
 180                         clock-names = "int";
 181                         dmas = <&dmamux1 29 0x400 0x1>,
 182                                <&dmamux1 30 0x400 0x1>,
 183                                <&dmamux1 31 0x400 0x1>,
 184                                <&dmamux1 32 0x400 0x1>;
 185                         dma-names = "ch1", "ch2", "ch3", "ch4";
 186                         status = "disabled";
 187
 188                         pwm {
 189                                 compatible = "st,stm32-pwm";
 190                                 status = "disabled";
 191                         };
 192
 193                         timer@3 {
 194                                 compatible = "st,stm32h7-timer-trigger";
 195                                 reg = <3>;
 196                                 status = "disabled";
 197                         };
 198                 };
 199
 200                 timers5: timer@40003000 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         compatible = "st,stm32-timers";
 204                         reg = <0x40003000 0x400>;
 205                         clocks = <&rcc TIM5_K>;
 206                         clock-names = "int";
 207                         dmas = <&dmamux1 55 0x400 0x1>,
 208                                <&dmamux1 56 0x400 0x1>,
 209                                <&dmamux1 57 0x400 0x1>,
 210                                <&dmamux1 58 0x400 0x1>,
 211                                <&dmamux1 59 0x400 0x1>,
 212                                <&dmamux1 60 0x400 0x1>;
 213                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 214                         status = "disabled";
 215
 216                         pwm {
 217                                 compatible = "st,stm32-pwm";
 218                                 status = "disabled";
 219                         };
 220
 221                         timer@4 {
 222                                 compatible = "st,stm32h7-timer-trigger";
 223                                 reg = <4>;
 224                                 status = "disabled";
 225                         };
 226                 };
 227
 228                 timers6: timer@40004000 {
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         compatible = "st,stm32-timers";
 232                         reg = <0x40004000 0x400>;
 233                         clocks = <&rcc TIM6_K>;
 234                         clock-names = "int";
 235                         dmas = <&dmamux1 69 0x400 0x1>;
 236                         dma-names = "up";
 237                         status = "disabled";
 238
 239                         timer@5 {
 240                                 compatible = "st,stm32h7-timer-trigger";
 241                                 reg = <5>;
 242                                 status = "disabled";
 243                         };
 244                 };
 245
 246                 timers7: timer@40005000 {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         compatible = "st,stm32-timers";
 250                         reg = <0x40005000 0x400>;
 251                         clocks = <&rcc TIM7_K>;
 252                         clock-names = "int";
 253                         dmas = <&dmamux1 70 0x400 0x1>;
 254                         dma-names = "up";
 255                         status = "disabled";
 256
 257                         timer@6 {
 258                                 compatible = "st,stm32h7-timer-trigger";
 259                                 reg = <6>;
 260                                 status = "disabled";
 261                         };
 262                 };
 263
 264                 timers12: timer@40006000 {
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         compatible = "st,stm32-timers";
 268                         reg = <0x40006000 0x400>;
 269                         clocks = <&rcc TIM12_K>;
 270                         clock-names = "int";
 271                         status = "disabled";
 272
 273                         pwm {
 274                                 compatible = "st,stm32-pwm";
 275                                 status = "disabled";
 276                         };
 277
 278                         timer@11 {
 279                                 compatible = "st,stm32h7-timer-trigger";
 280                                 reg = <11>;
 281                                 status = "disabled";
 282                         };
 283                 };
 284
 285                 timers13: timer@40007000 {
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         compatible = "st,stm32-timers";
 289                         reg = <0x40007000 0x400>;
 290                         clocks = <&rcc TIM13_K>;
 291                         clock-names = "int";
 292                         status = "disabled";
 293
 294                         pwm {
 295                                 compatible = "st,stm32-pwm";
 296                                 status = "disabled";
 297                         };
 298
 299                         timer@12 {
 300                                 compatible = "st,stm32h7-timer-trigger";
 301                                 reg = <12>;
 302                                 status = "disabled";
 303                         };
 304                 };
 305
 306                 timers14: timer@40008000 {
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         compatible = "st,stm32-timers";
 310                         reg = <0x40008000 0x400>;
 311                         clocks = <&rcc TIM14_K>;
 312                         clock-names = "int";
 313                         status = "disabled";
 314
 315                         pwm {
 316                                 compatible = "st,stm32-pwm";
 317                                 status = "disabled";
 318                         };
 319
 320                         timer@13 {
 321                                 compatible = "st,stm32h7-timer-trigger";
 322                                 reg = <13>;
 323                                 status = "disabled";
 324                         };
 325                 };
 326
 327                 lptimer1: timer@40009000 {
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         compatible = "st,stm32-lptimer";
 331                         reg = <0x40009000 0x400>;
 332                         clocks = <&rcc LPTIM1_K>;
 333                         clock-names = "mux";
 334                         status = "disabled";
 335
 336                         pwm {
 337                                 compatible = "st,stm32-pwm-lp";
 338                                 #pwm-cells = <3>;
 339                                 status = "disabled";
 340                         };
 341
 342                         trigger@0 {
 343                                 compatible = "st,stm32-lptimer-trigger";
 344                                 reg = <0>;
 345                                 status = "disabled";
 346                         };
 347
 348                         counter {
 349                                 compatible = "st,stm32-lptimer-counter";
 350                                 status = "disabled";
 351                         };
 352                 };
 353
 354                 spi2: spi@4000b000 {
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         compatible = "st,stm32h7-spi";
 358                         reg = <0x4000b000 0x400>;
 359                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 360                         clocks = <&rcc SPI2_K>;
 361                         resets = <&rcc SPI2_R>;
 362                         dmas = <&dmamux1 39 0x400 0x05>,
 363                                <&dmamux1 40 0x400 0x05>;
 364                         dma-names = "rx", "tx";
 365                         status = "disabled";
 366                 };
 367
 368                 spi3: spi@4000c000 {
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         compatible = "st,stm32h7-spi";
 372                         reg = <0x4000c000 0x400>;
 373                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&rcc SPI3_K>;
 375                         resets = <&rcc SPI3_R>;
 376                         dmas = <&dmamux1 61 0x400 0x05>,
 377                                <&dmamux1 62 0x400 0x05>;
 378                         dma-names = "rx", "tx";
 379                         status = "disabled";
 380                 };
 381
 382                 usart2: serial@4000e000 {
 383                         compatible = "st,stm32h7-uart";
 384                         reg = <0x4000e000 0x400>;
 385                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&rcc USART2_K>;
 387                         status = "disabled";
 388                 };
 389
 390                 usart3: serial@4000f000 {
 391                         compatible = "st,stm32h7-uart";
 392                         reg = <0x4000f000 0x400>;
 393                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&rcc USART3_K>;
 395                         status = "disabled";
 396                 };
 397
 398                 uart4: serial@40010000 {
 399                         compatible = "st,stm32h7-uart";
 400                         reg = <0x40010000 0x400>;
 401                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&rcc UART4_K>;
 403                         status = "disabled";
 404                 };
 405
 406                 uart5: serial@40011000 {
 407                         compatible = "st,stm32h7-uart";
 408                         reg = <0x40011000 0x400>;
 409                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&rcc UART5_K>;
 411                         status = "disabled";
 412                 };
 413
 414                 i2c1: i2c@40012000 {
 415                         compatible = "st,stm32f7-i2c";
 416                         reg = <0x40012000 0x400>;
 417                         interrupt-names = "event", "error";
 418                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 419                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&rcc I2C1_K>;
 421                         resets = <&rcc I2C1_R>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         status = "disabled";
 425                 };
 426
 427                 i2c2: i2c@40013000 {
 428                         compatible = "st,stm32f7-i2c";
 429                         reg = <0x40013000 0x400>;
 430                         interrupt-names = "event", "error";
 431                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 432                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&rcc I2C2_K>;
 434                         resets = <&rcc I2C2_R>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 i2c3: i2c@40014000 {
 441                         compatible = "st,stm32f7-i2c";
 442                         reg = <0x40014000 0x400>;
 443                         interrupt-names = "event", "error";
 444                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 445                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&rcc I2C3_K>;
 447                         resets = <&rcc I2C3_R>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         status = "disabled";
 451                 };
 452
 453                 i2c5: i2c@40015000 {
 454                         compatible = "st,stm32f7-i2c";
 455                         reg = <0x40015000 0x400>;
 456                         interrupt-names = "event", "error";
 457                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 458                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&rcc I2C5_K>;
 460                         resets = <&rcc I2C5_R>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         status = "disabled";
 464                 };
 465
 466                 cec: cec@40016000 {
 467                         compatible = "st,stm32-cec";
 468                         reg = <0x40016000 0x400>;
 469                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&rcc CEC_K>, <&clk_lse>;
 471                         clock-names = "cec", "hdmi-cec";
 472                         status = "disabled";
 473                 };
 474
 475                 dac: dac@40017000 {
 476                         compatible = "st,stm32h7-dac-core";
 477                         reg = <0x40017000 0x400>;
 478                         clocks = <&rcc DAC12>;
 479                         clock-names = "pclk";
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         status = "disabled";
 483
 484                         dac1: dac@1 {
 485                                 compatible = "st,stm32-dac";
 486                                 #io-channels-cells = <1>;
 487                                 reg = <1>;
 488                                 status = "disabled";
 489                         };
 490
 491                         dac2: dac@2 {
 492                                 compatible = "st,stm32-dac";
 493                                 #io-channels-cells = <1>;
 494                                 reg = <2>;
 495                                 status = "disabled";
 496                         };
 497                 };
 498
 499                 uart7: serial@40018000 {
 500                         compatible = "st,stm32h7-uart";
 501                         reg = <0x40018000 0x400>;
 502                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&rcc UART7_K>;
 504                         status = "disabled";
 505                 };
 506
 507                 uart8: serial@40019000 {
 508                         compatible = "st,stm32h7-uart";
 509                         reg = <0x40019000 0x400>;
 510                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&rcc UART8_K>;
 512                         status = "disabled";
 513                 };
 514
 515                 timers1: timer@44000000 {
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         compatible = "st,stm32-timers";
 519                         reg = <0x44000000 0x400>;
 520                         clocks = <&rcc TIM1_K>;
 521                         clock-names = "int";
 522                         dmas = <&dmamux1 11 0x400 0x1>,
 523                                <&dmamux1 12 0x400 0x1>,
 524                                <&dmamux1 13 0x400 0x1>,
 525                                <&dmamux1 14 0x400 0x1>,
 526                                <&dmamux1 15 0x400 0x1>,
 527                                <&dmamux1 16 0x400 0x1>,
 528                                <&dmamux1 17 0x400 0x1>;
 529                         dma-names = "ch1", "ch2", "ch3", "ch4",
 530                                     "up", "trig", "com";
 531                         status = "disabled";
 532
 533                         pwm {
 534                                 compatible = "st,stm32-pwm";
 535                                 status = "disabled";
 536                         };
 537
 538                         timer@0 {
 539                                 compatible = "st,stm32h7-timer-trigger";
 540                                 reg = <0>;
 541                                 status = "disabled";
 542                         };
 543                 };
 544
 545                 timers8: timer@44001000 {
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         compatible = "st,stm32-timers";
 549                         reg = <0x44001000 0x400>;
 550                         clocks = <&rcc TIM8_K>;
 551                         clock-names = "int";
 552                         dmas = <&dmamux1 47 0x400 0x1>,
 553                                <&dmamux1 48 0x400 0x1>,
 554                                <&dmamux1 49 0x400 0x1>,
 555                                <&dmamux1 50 0x400 0x1>,
 556                                <&dmamux1 51 0x400 0x1>,
 557                                <&dmamux1 52 0x400 0x1>,
 558                                <&dmamux1 53 0x400 0x1>;
 559                         dma-names = "ch1", "ch2", "ch3", "ch4",
 560                                     "up", "trig", "com";
 561                         status = "disabled";
 562
 563                         pwm {
 564                                 compatible = "st,stm32-pwm";
 565                                 status = "disabled";
 566                         };
 567
 568                         timer@7 {
 569                                 compatible = "st,stm32h7-timer-trigger";
 570                                 reg = <7>;
 571                                 status = "disabled";
 572                         };
 573                 };
 574
 575                 usart6: serial@44003000 {
 576                         compatible = "st,stm32h7-uart";
 577                         reg = <0x44003000 0x400>;
 578                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 579                         clocks = <&rcc USART6_K>;
 580                         status = "disabled";
 581                 };
 582
 583                 spi1: spi@44004000 {
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         compatible = "st,stm32h7-spi";
 587                         reg = <0x44004000 0x400>;
 588                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&rcc SPI1_K>;
 590                         resets = <&rcc SPI1_R>;
 591                         dmas = <&dmamux1 37 0x400 0x05>,
 592                                <&dmamux1 38 0x400 0x05>;
 593                         dma-names = "rx", "tx";
 594                         status = "disabled";
 595                 };
 596
 597                 spi4: spi@44005000 {
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                         compatible = "st,stm32h7-spi";
 601                         reg = <0x44005000 0x400>;
 602                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 603                         clocks = <&rcc SPI4_K>;
 604                         resets = <&rcc SPI4_R>;
 605                         dmas = <&dmamux1 83 0x400 0x05>,
 606                                <&dmamux1 84 0x400 0x05>;
 607                         dma-names = "rx", "tx";
 608                         status = "disabled";
 609                 };
 610
 611                 timers15: timer@44006000 {
 612                         #address-cells = <1>;
 613                         #size-cells = <0>;
 614                         compatible = "st,stm32-timers";
 615                         reg = <0x44006000 0x400>;
 616                         clocks = <&rcc TIM15_K>;
 617                         clock-names = "int";
 618                         dmas = <&dmamux1 105 0x400 0x1>,
 619                                <&dmamux1 106 0x400 0x1>,
 620                                <&dmamux1 107 0x400 0x1>,
 621                                <&dmamux1 108 0x400 0x1>;
 622                         dma-names = "ch1", "up", "trig", "com";
 623                         status = "disabled";
 624
 625                         pwm {
 626                                 compatible = "st,stm32-pwm";
 627                                 status = "disabled";
 628                         };
 629
 630                         timer@14 {
 631                                 compatible = "st,stm32h7-timer-trigger";
 632                                 reg = <14>;
 633                                 status = "disabled";
 634                         };
 635                 };
 636
 637                 timers16: timer@44007000 {
 638                         #address-cells = <1>;
 639                         #size-cells = <0>;
 640                         compatible = "st,stm32-timers";
 641                         reg = <0x44007000 0x400>;
 642                         clocks = <&rcc TIM16_K>;
 643                         clock-names = "int";
 644                         dmas = <&dmamux1 109 0x400 0x1>,
 645                                <&dmamux1 110 0x400 0x1>;
 646                         dma-names = "ch1", "up";
 647                         status = "disabled";
 648
 649                         pwm {
 650                                 compatible = "st,stm32-pwm";
 651                                 status = "disabled";
 652                         };
 653                         timer@15 {
 654                                 compatible = "st,stm32h7-timer-trigger";
 655                                 reg = <15>;
 656                                 status = "disabled";
 657                         };
 658                 };
 659
 660                 timers17: timer@44008000 {
 661                         #address-cells = <1>;
 662                         #size-cells = <0>;
 663                         compatible = "st,stm32-timers";
 664                         reg = <0x44008000 0x400>;
 665                         clocks = <&rcc TIM17_K>;
 666                         clock-names = "int";
 667                         dmas = <&dmamux1 111 0x400 0x1>,
 668                                <&dmamux1 112 0x400 0x1>;
 669                         dma-names = "ch1", "up";
 670                         status = "disabled";
 671
 672                         pwm {
 673                                 compatible = "st,stm32-pwm";
 674                                 status = "disabled";
 675                         };
 676
 677                         timer@16 {
 678                                 compatible = "st,stm32h7-timer-trigger";
 679                                 reg = <16>;
 680                                 status = "disabled";
 681                         };
 682                 };
 683
 684                 spi5: spi@44009000 {
 685                         #address-cells = <1>;
 686                         #size-cells = <0>;
 687                         compatible = "st,stm32h7-spi";
 688                         reg = <0x44009000 0x400>;
 689                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 690                         clocks = <&rcc SPI5_K>;
 691                         resets = <&rcc SPI5_R>;
 692                         dmas = <&dmamux1 85 0x400 0x05>,
 693                                <&dmamux1 86 0x400 0x05>;
 694                         dma-names = "rx", "tx";
 695                         status = "disabled";
 696                 };
 697
 698                 dfsdm: dfsdm@4400d000 {
 699                         compatible = "st,stm32mp1-dfsdm";
 700                         reg = <0x4400d000 0x800>;
 701                         clocks = <&rcc DFSDM_K>;
 702                         clock-names = "dfsdm";
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         status = "disabled";
 706
 707                         dfsdm0: filter@0 {
 708                                 compatible = "st,stm32-dfsdm-adc";
 709                                 #io-channel-cells = <1>;
 710                                 reg = <0>;
 711                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 712                                 dmas = <&dmamux1 101 0x400 0x01>;
 713                                 dma-names = "rx";
 714                                 status = "disabled";
 715                         };
 716
 717                         dfsdm1: filter@1 {
 718                                 compatible = "st,stm32-dfsdm-adc";
 719                                 #io-channel-cells = <1>;
 720                                 reg = <1>;
 721                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 722                                 dmas = <&dmamux1 102 0x400 0x01>;
 723                                 dma-names = "rx";
 724                                 status = "disabled";
 725                         };
 726
 727                         dfsdm2: filter@2 {
 728                                 compatible = "st,stm32-dfsdm-adc";
 729                                 #io-channel-cells = <1>;
 730                                 reg = <2>;
 731                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 732                                 dmas = <&dmamux1 103 0x400 0x01>;
 733                                 dma-names = "rx";
 734                                 status = "disabled";
 735                         };
 736
 737                         dfsdm3: filter@3 {
 738                                 compatible = "st,stm32-dfsdm-adc";
 739                                 #io-channel-cells = <1>;
 740                                 reg = <3>;
 741                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 742                                 dmas = <&dmamux1 104 0x400 0x01>;
 743                                 dma-names = "rx";
 744                                 status = "disabled";
 745                         };
 746
 747                         dfsdm4: filter@4 {
 748                                 compatible = "st,stm32-dfsdm-adc";
 749                                 #io-channel-cells = <1>;
 750                                 reg = <4>;
 751                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 752                                 dmas = <&dmamux1 91 0x400 0x01>;
 753                                 dma-names = "rx";
 754                                 status = "disabled";
 755                         };
 756
 757                         dfsdm5: filter@5 {
 758                                 compatible = "st,stm32-dfsdm-adc";
 759                                 #io-channel-cells = <1>;
 760                                 reg = <5>;
 761                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 762                                 dmas = <&dmamux1 92 0x400 0x01>;
 763                                 dma-names = "rx";
 764                                 status = "disabled";
 765                         };
 766                 };
 767
 768                 m_can1: can@4400e000 {
 769                         compatible = "bosch,m_can";
 770                         reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
 771                         reg-names = "m_can", "message_ram";
 772                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 773                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 774                         interrupt-names = "int0", "int1";
 775                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 776                         clock-names = "hclk", "cclk";
 777                         bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 778                         status = "disabled";
 779                 };
 780
 781                 m_can2: can@4400f000 {
 782                         compatible = "bosch,m_can";
 783                         reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
 784                         reg-names = "m_can", "message_ram";
 785                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 787                         interrupt-names = "int0", "int1";
 788                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 789                         clock-names = "hclk", "cclk";
 790                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 791                         status = "disabled";
 792                 };
 793
 794                 dma1: dma@48000000 {
 795                         compatible = "st,stm32-dma";
 796                         reg = <0x48000000 0x400>;
 797                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 798                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 799                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 800                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 805                         clocks = <&rcc DMA1>;
 806                         #dma-cells = <4>;
 807                         st,mem2mem;
 808                         dma-requests = <8>;
 809                 };
 810
 811                 dma2: dma@48001000 {
 812                         compatible = "st,stm32-dma";
 813                         reg = <0x48001000 0x400>;
 814                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 815                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 816                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 818                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 819                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 820                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 821                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 822                         clocks = <&rcc DMA2>;
 823                         #dma-cells = <4>;
 824                         st,mem2mem;
 825                         dma-requests = <8>;
 826                 };
 827
 828                 dmamux1: dma-router@48002000 {
 829                         compatible = "st,stm32h7-dmamux";
 830                         reg = <0x48002000 0x1c>;
 831                         #dma-cells = <3>;
 832                         dma-requests = <128>;
 833                         dma-masters = <&dma1 &dma2>;
 834                         dma-channels = <16>;
 835                         clocks = <&rcc DMAMUX>;
 836                 };
 837
 838                 adc: adc@48003000 {
 839                         compatible = "st,stm32mp1-adc-core";
 840                         reg = <0x48003000 0x400>;
 841                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 842                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 843                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
 844                         clock-names = "bus", "adc";
 845                         interrupt-controller;
 846                         #interrupt-cells = <1>;
 847                         #address-cells = <1>;
 848                         #size-cells = <0>;
 849                         status = "disabled";
 850
 851                         adc1: adc@0 {
 852                                 compatible = "st,stm32mp1-adc";
 853                                 #io-channel-cells = <1>;
 854                                 reg = <0x0>;
 855                                 interrupt-parent = <&adc>;
 856                                 interrupts = <0>;
 857                                 dmas = <&dmamux1 9 0x400 0x01>;
 858                                 dma-names = "rx";
 859                                 status = "disabled";
 860                         };
 861
 862                         adc2: adc@100 {
 863                                 compatible = "st,stm32mp1-adc";
 864                                 #io-channel-cells = <1>;
 865                                 reg = <0x100>;
 866                                 interrupt-parent = <&adc>;
 867                                 interrupts = <1>;
 868                                 dmas = <&dmamux1 10 0x400 0x01>;
 869                                 dma-names = "rx";
 870                                 status = "disabled";
 871                         };
 872                 };
 873
 874                 usbotg_hs: usb-otg@49000000 {
 875                         compatible = "snps,dwc2";
 876                         reg = <0x49000000 0x10000>;
 877                         clocks = <&rcc USBO_K>;
 878                         clock-names = "otg";
 879                         resets = <&rcc USBO_R>;
 880                         reset-names = "dwc2";
 881                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 882                         g-rx-fifo-size = <256>;
 883                         g-np-tx-fifo-size = <32>;
 884                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 885                         dr_mode = "otg";
 886                         status = "disabled";
 887                 };
 888
 889                 rcc: rcc@50000000 {
 890                         compatible = "st,stm32mp1-rcc", "syscon";
 891                         reg = <0x50000000 0x1000>;
 892                         #clock-cells = <1>;
 893                         #reset-cells = <1>;
 894                 };
 895
 896                 exti: interrupt-controller@5000d000 {
 897                         compatible = "st,stm32mp1-exti", "syscon";
 898                         interrupt-controller;
 899                         #interrupt-cells = <2>;
 900                         reg = <0x5000d000 0x400>;
 901                 };
 902
 903                 syscfg: syscon@50020000 {
 904                         compatible = "st,stm32mp157-syscfg", "syscon";
 905                         reg = <0x50020000 0x400>;
 906                 };
 907
 908                 lptimer2: timer@50021000 {
 909                         #address-cells = <1>;
 910                         #size-cells = <0>;
 911                         compatible = "st,stm32-lptimer";
 912                         reg = <0x50021000 0x400>;
 913                         clocks = <&rcc LPTIM2_K>;
 914                         clock-names = "mux";
 915                         status = "disabled";
 916
 917                         pwm {
 918                                 compatible = "st,stm32-pwm-lp";
 919                                 #pwm-cells = <3>;
 920                                 status = "disabled";
 921                         };
 922
 923                         trigger@1 {
 924                                 compatible = "st,stm32-lptimer-trigger";
 925                                 reg = <1>;
 926                                 status = "disabled";
 927                         };
 928
 929                         counter {
 930                                 compatible = "st,stm32-lptimer-counter";
 931                                 status = "disabled";
 932                         };
 933                 };
 934
 935                 lptimer3: timer@50022000 {
 936                         #address-cells = <1>;
 937                         #size-cells = <0>;
 938                         compatible = "st,stm32-lptimer";
 939                         reg = <0x50022000 0x400>;
 940                         clocks = <&rcc LPTIM3_K>;
 941                         clock-names = "mux";
 942                         status = "disabled";
 943
 944                         pwm {
 945                                 compatible = "st,stm32-pwm-lp";
 946                                 #pwm-cells = <3>;
 947                                 status = "disabled";
 948                         };
 949
 950                         trigger@2 {
 951                                 compatible = "st,stm32-lptimer-trigger";
 952                                 reg = <2>;
 953                                 status = "disabled";
 954                         };
 955                 };
 956
 957                 lptimer4: timer@50023000 {
 958                         compatible = "st,stm32-lptimer";
 959                         reg = <0x50023000 0x400>;
 960                         clocks = <&rcc LPTIM4_K>;
 961                         clock-names = "mux";
 962                         status = "disabled";
 963
 964                         pwm {
 965                                 compatible = "st,stm32-pwm-lp";
 966                                 #pwm-cells = <3>;
 967                                 status = "disabled";
 968                         };
 969                 };
 970
 971                 lptimer5: timer@50024000 {
 972                         compatible = "st,stm32-lptimer";
 973                         reg = <0x50024000 0x400>;
 974                         clocks = <&rcc LPTIM5_K>;
 975                         clock-names = "mux";
 976                         status = "disabled";
 977
 978                         pwm {
 979                                 compatible = "st,stm32-pwm-lp";
 980                                 #pwm-cells = <3>;
 981                                 status = "disabled";
 982                         };
 983                 };
 984
 985                 vrefbuf: vrefbuf@50025000 {
 986                         compatible = "st,stm32-vrefbuf";
 987                         reg = <0x50025000 0x8>;
 988                         regulator-min-microvolt = <1500000>;
 989                         regulator-max-microvolt = <2500000>;
 990                         clocks = <&rcc VREF>;
 991                         status = "disabled";
 992                 };
 993
 994                 dts: thermal@50028000 {
 995                         compatible = "st,stm32-thermal";
 996                         reg = <0x50028000 0x100>;
 997                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 998                         clocks = <&rcc TMPSENS>;
 999                         clock-names = "pclk";
1000                         #thermal-sensor-cells = <0>;
1001                         status = "disabled";
1002                 };
1003
1004                 cryp1: cryp@54001000 {
1005                         compatible = "st,stm32mp1-cryp";
1006                         reg = <0x54001000 0x400>;
1007                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1008                         clocks = <&rcc CRYP1>;
1009                         resets = <&rcc CRYP1_R>;
1010                         status = "disabled";
1011                 };
1012
1013                 hash1: hash@54002000 {
1014                         compatible = "st,stm32f756-hash";
1015                         reg = <0x54002000 0x400>;
1016                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1017                         clocks = <&rcc HASH1>;
1018                         resets = <&rcc HASH1_R>;
1019                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1020                         dma-names = "in";
1021                         dma-maxburst = <2>;
1022                         status = "disabled";
1023                 };
1024
1025                 rng1: rng@54003000 {
1026                         compatible = "st,stm32-rng";
1027                         reg = <0x54003000 0x400>;
1028                         clocks = <&rcc RNG1_K>;
1029                         resets = <&rcc RNG1_R>;
1030                         status = "disabled";
1031                 };
1032
1033                 mdma1: dma@58000000 {
1034                         compatible = "st,stm32h7-mdma";
1035                         reg = <0x58000000 0x1000>;
1036                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1037                         clocks = <&rcc MDMA>;
1038                         #dma-cells = <5>;
1039                         dma-channels = <32>;
1040                         dma-requests = <48>;
1041                 };
1042
1043                 qspi: spi@58003000 {
1044                         compatible = "st,stm32f469-qspi";
1045                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1046                         reg-names = "qspi", "qspi_mm";
1047                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1048                         clocks = <&rcc QSPI_K>;
1049                         resets = <&rcc QSPI_R>;
1050                         status = "disabled";
1051                 };
1052
1053                 crc1: crc@58009000 {
1054                         compatible = "st,stm32f7-crc";
1055                         reg = <0x58009000 0x400>;
1056                         clocks = <&rcc CRC1>;
1057                         status = "disabled";
1058                 };
1059
1060                 stmmac_axi_config_0: stmmac-axi-config {
1061                         snps,wr_osr_lmt = <0x7>;
1062                         snps,rd_osr_lmt = <0x7>;
1063                         snps,blen = <0 0 0 0 16 8 4>;
1064                 };
1065
1066                 ethernet0: ethernet@5800a000 {
1067                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1068                         reg = <0x5800a000 0x2000>;
1069                         reg-names = "stmmaceth";
1070                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1071                         interrupt-names = "macirq";
1072                         clock-names = "stmmaceth",
1073                                       "mac-clk-tx",
1074                                       "mac-clk-rx",
1075                                       "ethstp",
1076                                       "syscfg-clk";
1077                         clocks = <&rcc ETHMAC>,
1078                                  <&rcc ETHTX>,
1079                                  <&rcc ETHRX>,
1080                                  <&rcc ETHSTP>,
1081                                  <&rcc SYSCFG>;
1082                         st,syscon = <&syscfg 0x4>;
1083                         snps,mixed-burst;
1084                         snps,pbl = <2>;
1085                         snps,axi-config = <&stmmac_axi_config_0>;
1086                         snps,tso;
1087                         status = "disabled";
1088                 };
1089
1090                 usbh_ohci: usbh-ohci@5800c000 {
1091                         compatible = "generic-ohci";
1092                         reg = <0x5800c000 0x1000>;
1093                         clocks = <&rcc USBH>;
1094                         resets = <&rcc USBH_R>;
1095                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1096                         status = "disabled";
1097                 };
1098
1099                 usbh_ehci: usbh-ehci@5800d000 {
1100                         compatible = "generic-ehci";
1101                         reg = <0x5800d000 0x1000>;
1102                         clocks = <&rcc USBH>;
1103                         resets = <&rcc USBH_R>;
1104                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1105                         companion = <&usbh_ohci>;
1106                         status = "disabled";
1107                 };
1108
1109                 dsi: dsi@5a000000 {
1110                         compatible = "st,stm32-dsi";
1111                         reg = <0x5a000000 0x800>;
1112                         clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1113                         clock-names = "pclk", "ref", "px_clk";
1114                         resets = <&rcc DSI_R>;
1115                         reset-names = "apb";
1116                         status = "disabled";
1117                 };
1118
1119                 ltdc: display-controller@5a001000 {
1120                         compatible = "st,stm32-ltdc";
1121                         reg = <0x5a001000 0x400>;
1122                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1123                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1124                         clocks = <&rcc LTDC_PX>;
1125                         clock-names = "lcd";
1126                         resets = <&rcc LTDC_R>;
1127                         status = "disabled";
1128                 };
1129
1130                 iwdg2: watchdog@5a002000 {
1131                         compatible = "st,stm32mp1-iwdg";
1132                         reg = <0x5a002000 0x400>;
1133                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1134                         clock-names = "pclk", "lsi";
1135                         status = "disabled";
1136                 };
1137
1138                 usbphyc: usbphyc@5a006000 {
1139                         #address-cells = <1>;
1140                         #size-cells = <0>;
1141                         compatible = "st,stm32mp1-usbphyc";
1142                         reg = <0x5a006000 0x1000>;
1143                         clocks = <&rcc USBPHY_K>;
1144                         resets = <&rcc USBPHY_R>;
1145                         status = "disabled";
1146
1147                         usbphyc_port0: usb-phy@0 {
1148                                 #phy-cells = <0>;
1149                                 reg = <0>;
1150                         };
1151
1152                         usbphyc_port1: usb-phy@1 {
1153                                 #phy-cells = <1>;
1154                                 reg = <1>;
1155                         };
1156                 };
1157
1158                 usart1: serial@5c000000 {
1159                         compatible = "st,stm32h7-uart";
1160                         reg = <0x5c000000 0x400>;
1161                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1162                         clocks = <&rcc USART1_K>;
1163                         status = "disabled";
1164                 };
1165
1166                 spi6: spi@5c001000 {
1167                         #address-cells = <1>;
1168                         #size-cells = <0>;
1169                         compatible = "st,stm32h7-spi";
1170                         reg = <0x5c001000 0x400>;
1171                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1172                         clocks = <&rcc SPI6_K>;
1173                         resets = <&rcc SPI6_R>;
1174                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1175                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1176                         dma-names = "rx", "tx";
1177                         status = "disabled";
1178                 };
1179
1180                 i2c4: i2c@5c002000 {
1181                         compatible = "st,stm32f7-i2c";
1182                         reg = <0x5c002000 0x400>;
1183                         interrupt-names = "event", "error";
1184                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1185                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1186                         clocks = <&rcc I2C4_K>;
1187                         resets = <&rcc I2C4_R>;
1188                         #address-cells = <1>;
1189                         #size-cells = <0>;
1190                         status = "disabled";
1191                 };
1192
1193                 rtc: rtc@5c004000 {
1194                         compatible = "st,stm32mp1-rtc";
1195                         reg = <0x5c004000 0x400>;
1196                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1197                         clock-names = "pclk", "rtc_ck";
1198                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1199                         status = "disabled";
1200                 };
1201
1202                 i2c6: i2c@5c009000 {
1203                         compatible = "st,stm32f7-i2c";
1204                         reg = <0x5c009000 0x400>;
1205                         interrupt-names = "event", "error";
1206                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1207                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1208                         clocks = <&rcc I2C6_K>;
1209                         resets = <&rcc I2C6_R>;
1210                         #address-cells = <1>;
1211                         #size-cells = <0>;
1212                         status = "disabled";
1213                 };
1214         };
1215 };