arch/arm/boot/dts/stm32mp157c.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci";
  33                 method = "smc";
  34                 cpu_off = <0x84000002>;
  35                 cpu_on = <0x84000003>;
  36         };
  37
  38         aliases {
  39                 gpio0 = &gpioa;
  40                 gpio1 = &gpiob;
  41                 gpio2 = &gpioc;
  42                 gpio3 = &gpiod;
  43                 gpio4 = &gpioe;
  44                 gpio5 = &gpiof;
  45                 gpio6 = &gpiog;
  46                 gpio7 = &gpioh;
  47                 gpio8 = &gpioi;
  48                 gpio9 = &gpioj;
  49                 gpio10 = &gpiok;
  50         };
  51
  52         intc: interrupt-controller@a0021000 {
  53                 compatible = "arm,cortex-a7-gic";
  54                 #interrupt-cells = <3>;
  55                 interrupt-controller;
  56                 reg = <0xa0021000 0x1000>,
  57                       <0xa0022000 0x2000>;
  58         };
  59
  60         timer {
  61                 compatible = "arm,armv7-timer";
  62                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  63                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  64                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  65                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  66                 interrupt-parent = <&intc>;
  67         };
  68
  69         clocks {
  70                 clk_hse: clk-hse {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-clock";
  73                         clock-frequency = <24000000>;
  74                 };
  75
  76                 clk_hsi: clk-hsi {
  77                         #clock-cells = <0>;
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <64000000>;
  80                 };
  81
  82                 clk_lse: clk-lse {
  83                         #clock-cells = <0>;
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                 };
  87
  88                 clk_lsi: clk-lsi {
  89                         #clock-cells = <0>;
  90                         compatible = "fixed-clock";
  91                         clock-frequency = <32000>;
  92                 };
  93
  94                 clk_csi: clk-csi {
  95                         #clock-cells = <0>;
  96                         compatible = "fixed-clock";
  97                         clock-frequency = <4000000>;
  98                 };
  99         };
 100
 101         soc {
 102                 compatible = "simple-bus";
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 interrupt-parent = <&intc>;
 106                 ranges;
 107
 108                 timers2: timer@40000000 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         compatible = "st,stm32-timers";
 112                         reg = <0x40000000 0x400>;
 113                         clocks = <&rcc TIM2_K>;
 114                         clock-names = "int";
 115                         status = "disabled";
 116
 117                         pwm {
 118                                 compatible = "st,stm32-pwm";
 119                                 status = "disabled";
 120                         };
 121
 122                         timer@1 {
 123                                 compatible = "st,stm32h7-timer-trigger";
 124                                 reg = <1>;
 125                                 status = "disabled";
 126                         };
 127                 };
 128
 129                 timers3: timer@40001000 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         compatible = "st,stm32-timers";
 133                         reg = <0x40001000 0x400>;
 134                         clocks = <&rcc TIM3_K>;
 135                         clock-names = "int";
 136                         status = "disabled";
 137
 138                         pwm {
 139                                 compatible = "st,stm32-pwm";
 140                                 status = "disabled";
 141                         };
 142
 143                         timer@2 {
 144                                 compatible = "st,stm32h7-timer-trigger";
 145                                 reg = <2>;
 146                                 status = "disabled";
 147                         };
 148                 };
 149
 150                 timers4: timer@40002000 {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         compatible = "st,stm32-timers";
 154                         reg = <0x40002000 0x400>;
 155                         clocks = <&rcc TIM4_K>;
 156                         clock-names = "int";
 157                         status = "disabled";
 158
 159                         pwm {
 160                                 compatible = "st,stm32-pwm";
 161                                 status = "disabled";
 162                         };
 163
 164                         timer@3 {
 165                                 compatible = "st,stm32h7-timer-trigger";
 166                                 reg = <3>;
 167                                 status = "disabled";
 168                         };
 169                 };
 170
 171                 timers5: timer@40003000 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         compatible = "st,stm32-timers";
 175                         reg = <0x40003000 0x400>;
 176                         clocks = <&rcc TIM5_K>;
 177                         clock-names = "int";
 178                         status = "disabled";
 179
 180                         pwm {
 181                                 compatible = "st,stm32-pwm";
 182                                 status = "disabled";
 183                         };
 184
 185                         timer@4 {
 186                                 compatible = "st,stm32h7-timer-trigger";
 187                                 reg = <4>;
 188                                 status = "disabled";
 189                         };
 190                 };
 191
 192                 timers6: timer@40004000 {
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         compatible = "st,stm32-timers";
 196                         reg = <0x40004000 0x400>;
 197                         clocks = <&rcc TIM6_K>;
 198                         clock-names = "int";
 199                         status = "disabled";
 200
 201                         timer@5 {
 202                                 compatible = "st,stm32h7-timer-trigger";
 203                                 reg = <5>;
 204                                 status = "disabled";
 205                         };
 206                 };
 207
 208                 timers7: timer@40005000 {
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         compatible = "st,stm32-timers";
 212                         reg = <0x40005000 0x400>;
 213                         clocks = <&rcc TIM7_K>;
 214                         clock-names = "int";
 215                         status = "disabled";
 216
 217                         timer@6 {
 218                                 compatible = "st,stm32h7-timer-trigger";
 219                                 reg = <6>;
 220                                 status = "disabled";
 221                         };
 222                 };
 223
 224                 timers12: timer@40006000 {
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         compatible = "st,stm32-timers";
 228                         reg = <0x40006000 0x400>;
 229                         clocks = <&rcc TIM12_K>;
 230                         clock-names = "int";
 231                         status = "disabled";
 232
 233                         pwm {
 234                                 compatible = "st,stm32-pwm";
 235                                 status = "disabled";
 236                         };
 237
 238                         timer@11 {
 239                                 compatible = "st,stm32h7-timer-trigger";
 240                                 reg = <11>;
 241                                 status = "disabled";
 242                         };
 243                 };
 244
 245                 timers13: timer@40007000 {
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         compatible = "st,stm32-timers";
 249                         reg = <0x40007000 0x400>;
 250                         clocks = <&rcc TIM13_K>;
 251                         clock-names = "int";
 252                         status = "disabled";
 253
 254                         pwm {
 255                                 compatible = "st,stm32-pwm";
 256                                 status = "disabled";
 257                         };
 258
 259                         timer@12 {
 260                                 compatible = "st,stm32h7-timer-trigger";
 261                                 reg = <12>;
 262                                 status = "disabled";
 263                         };
 264                 };
 265
 266                 timers14: timer@40008000 {
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         compatible = "st,stm32-timers";
 270                         reg = <0x40008000 0x400>;
 271                         clocks = <&rcc TIM14_K>;
 272                         clock-names = "int";
 273                         status = "disabled";
 274
 275                         pwm {
 276                                 compatible = "st,stm32-pwm";
 277                                 status = "disabled";
 278                         };
 279
 280                         timer@13 {
 281                                 compatible = "st,stm32h7-timer-trigger";
 282                                 reg = <13>;
 283                                 status = "disabled";
 284                         };
 285                 };
 286
 287                 lptimer1: timer@40009000 {
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         compatible = "st,stm32-lptimer";
 291                         reg = <0x40009000 0x400>;
 292                         clocks = <&rcc LPTIM1_K>;
 293                         clock-names = "mux";
 294                         status = "disabled";
 295
 296                         pwm {
 297                                 compatible = "st,stm32-pwm-lp";
 298                                 #pwm-cells = <3>;
 299                                 status = "disabled";
 300                         };
 301
 302                         trigger@0 {
 303                                 compatible = "st,stm32-lptimer-trigger";
 304                                 reg = <0>;
 305                                 status = "disabled";
 306                         };
 307
 308                         counter {
 309                                 compatible = "st,stm32-lptimer-counter";
 310                                 status = "disabled";
 311                         };
 312                 };
 313
 314                 usart2: serial@4000e000 {
 315                         compatible = "st,stm32h7-uart";
 316                         reg = <0x4000e000 0x400>;
 317                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&rcc USART2_K>;
 319                         status = "disabled";
 320                 };
 321
 322                 usart3: serial@4000f000 {
 323                         compatible = "st,stm32h7-uart";
 324                         reg = <0x4000f000 0x400>;
 325                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&rcc USART3_K>;
 327                         status = "disabled";
 328                 };
 329
 330                 uart4: serial@40010000 {
 331                         compatible = "st,stm32h7-uart";
 332                         reg = <0x40010000 0x400>;
 333                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&rcc UART4_K>;
 335                         status = "disabled";
 336                 };
 337
 338                 uart5: serial@40011000 {
 339                         compatible = "st,stm32h7-uart";
 340                         reg = <0x40011000 0x400>;
 341                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&rcc UART5_K>;
 343                         status = "disabled";
 344                 };
 345
 346                 i2c1: i2c@40012000 {
 347                         compatible = "st,stm32f7-i2c";
 348                         reg = <0x40012000 0x400>;
 349                         interrupt-names = "event", "error";
 350                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 352                         clocks = <&rcc I2C1_K>;
 353                         resets = <&rcc I2C1_R>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         status = "disabled";
 357                 };
 358
 359                 i2c2: i2c@40013000 {
 360                         compatible = "st,stm32f7-i2c";
 361                         reg = <0x40013000 0x400>;
 362                         interrupt-names = "event", "error";
 363                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&rcc I2C2_K>;
 366                         resets = <&rcc I2C2_R>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         status = "disabled";
 370                 };
 371
 372                 i2c3: i2c@40014000 {
 373                         compatible = "st,stm32f7-i2c";
 374                         reg = <0x40014000 0x400>;
 375                         interrupt-names = "event", "error";
 376                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 377                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&rcc I2C3_K>;
 379                         resets = <&rcc I2C3_R>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         status = "disabled";
 383                 };
 384
 385                 i2c5: i2c@40015000 {
 386                         compatible = "st,stm32f7-i2c";
 387                         reg = <0x40015000 0x400>;
 388                         interrupt-names = "event", "error";
 389                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&rcc I2C5_K>;
 392                         resets = <&rcc I2C5_R>;
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         status = "disabled";
 396                 };
 397
 398                 cec: cec@40016000 {
 399                         compatible = "st,stm32-cec";
 400                         reg = <0x40016000 0x400>;
 401                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&rcc CEC_K>, <&clk_lse>;
 403                         clock-names = "cec", "hdmi-cec";
 404                         status = "disabled";
 405                 };
 406
 407                 dac: dac@40017000 {
 408                         compatible = "st,stm32h7-dac-core";
 409                         reg = <0x40017000 0x400>;
 410                         clocks = <&rcc DAC12>;
 411                         clock-names = "pclk";
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         status = "disabled";
 415
 416                         dac1: dac@1 {
 417                                 compatible = "st,stm32-dac";
 418                                 #io-channels-cells = <1>;
 419                                 reg = <1>;
 420                                 status = "disabled";
 421                         };
 422
 423                         dac2: dac@2 {
 424                                 compatible = "st,stm32-dac";
 425                                 #io-channels-cells = <1>;
 426                                 reg = <2>;
 427                                 status = "disabled";
 428                         };
 429                 };
 430
 431                 uart7: serial@40018000 {
 432                         compatible = "st,stm32h7-uart";
 433                         reg = <0x40018000 0x400>;
 434                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&rcc UART7_K>;
 436                         status = "disabled";
 437                 };
 438
 439                 uart8: serial@40019000 {
 440                         compatible = "st,stm32h7-uart";
 441                         reg = <0x40019000 0x400>;
 442                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&rcc UART8_K>;
 444                         status = "disabled";
 445                 };
 446
 447                 timers1: timer@44000000 {
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         compatible = "st,stm32-timers";
 451                         reg = <0x44000000 0x400>;
 452                         clocks = <&rcc TIM1_K>;
 453                         clock-names = "int";
 454                         status = "disabled";
 455
 456                         pwm {
 457                                 compatible = "st,stm32-pwm";
 458                                 status = "disabled";
 459                         };
 460
 461                         timer@0 {
 462                                 compatible = "st,stm32h7-timer-trigger";
 463                                 reg = <0>;
 464                                 status = "disabled";
 465                         };
 466                 };
 467
 468                 timers8: timer@44001000 {
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         compatible = "st,stm32-timers";
 472                         reg = <0x44001000 0x400>;
 473                         clocks = <&rcc TIM8_K>;
 474                         clock-names = "int";
 475                         status = "disabled";
 476
 477                         pwm {
 478                                 compatible = "st,stm32-pwm";
 479                                 status = "disabled";
 480                         };
 481
 482                         timer@7 {
 483                                 compatible = "st,stm32h7-timer-trigger";
 484                                 reg = <7>;
 485                                 status = "disabled";
 486                         };
 487                 };
 488
 489                 usart6: serial@44003000 {
 490                         compatible = "st,stm32h7-uart";
 491                         reg = <0x44003000 0x400>;
 492                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 493                         clocks = <&rcc USART6_K>;
 494                         status = "disabled";
 495                 };
 496
 497                 timers15: timer@44006000 {
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         compatible = "st,stm32-timers";
 501                         reg = <0x44006000 0x400>;
 502                         clocks = <&rcc TIM15_K>;
 503                         clock-names = "int";
 504                         status = "disabled";
 505
 506                         pwm {
 507                                 compatible = "st,stm32-pwm";
 508                                 status = "disabled";
 509                         };
 510
 511                         timer@14 {
 512                                 compatible = "st,stm32h7-timer-trigger";
 513                                 reg = <14>;
 514                                 status = "disabled";
 515                         };
 516                 };
 517
 518                 timers16: timer@44007000 {
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                         compatible = "st,stm32-timers";
 522                         reg = <0x44007000 0x400>;
 523                         clocks = <&rcc TIM16_K>;
 524                         clock-names = "int";
 525                         status = "disabled";
 526
 527                         pwm {
 528                                 compatible = "st,stm32-pwm";
 529                                 status = "disabled";
 530                         };
 531                         timer@15 {
 532                                 compatible = "st,stm32h7-timer-trigger";
 533                                 reg = <15>;
 534                                 status = "disabled";
 535                         };
 536                 };
 537
 538                 timers17: timer@44008000 {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         compatible = "st,stm32-timers";
 542                         reg = <0x44008000 0x400>;
 543                         clocks = <&rcc TIM17_K>;
 544                         clock-names = "int";
 545                         status = "disabled";
 546
 547                         pwm {
 548                                 compatible = "st,stm32-pwm";
 549                                 status = "disabled";
 550                         };
 551
 552                         timer@16 {
 553                                 compatible = "st,stm32h7-timer-trigger";
 554                                 reg = <16>;
 555                                 status = "disabled";
 556                         };
 557                 };
 558
 559                 dma1: dma@48000000 {
 560                         compatible = "st,stm32-dma";
 561                         reg = <0x48000000 0x400>;
 562                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 563                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 568                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 569                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&rcc DMA1>;
 571                         #dma-cells = <4>;
 572                         st,mem2mem;
 573                         dma-requests = <8>;
 574                 };
 575
 576                 dma2: dma@48001000 {
 577                         compatible = "st,stm32-dma";
 578                         reg = <0x48001000 0x400>;
 579                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 581                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&rcc DMA2>;
 588                         #dma-cells = <4>;
 589                         st,mem2mem;
 590                         dma-requests = <8>;
 591                 };
 592
 593                 dmamux1: dma-router@48002000 {
 594                         compatible = "st,stm32h7-dmamux";
 595                         reg = <0x48002000 0x1c>;
 596                         #dma-cells = <3>;
 597                         dma-requests = <128>;
 598                         dma-masters = <&dma1 &dma2>;
 599                         dma-channels = <16>;
 600                         clocks = <&rcc DMAMUX>;
 601                 };
 602
 603                 rcc: rcc@50000000 {
 604                         compatible = "st,stm32mp1-rcc", "syscon";
 605                         reg = <0x50000000 0x1000>;
 606                         #clock-cells = <1>;
 607                         #reset-cells = <1>;
 608                 };
 609
 610                 exti: interrupt-controller@5000d000 {
 611                         compatible = "st,stm32mp1-exti", "syscon";
 612                         interrupt-controller;
 613                         #interrupt-cells = <2>;
 614                         reg = <0x5000d000 0x400>;
 615                 };
 616
 617                 lptimer2: timer@50021000 {
 618                         #address-cells = <1>;
 619                         #size-cells = <0>;
 620                         compatible = "st,stm32-lptimer";
 621                         reg = <0x50021000 0x400>;
 622                         clocks = <&rcc LPTIM2_K>;
 623                         clock-names = "mux";
 624                         status = "disabled";
 625
 626                         pwm {
 627                                 compatible = "st,stm32-pwm-lp";
 628                                 #pwm-cells = <3>;
 629                                 status = "disabled";
 630                         };
 631
 632                         trigger@1 {
 633                                 compatible = "st,stm32-lptimer-trigger";
 634                                 reg = <1>;
 635                                 status = "disabled";
 636                         };
 637
 638                         counter {
 639                                 compatible = "st,stm32-lptimer-counter";
 640                                 status = "disabled";
 641                         };
 642                 };
 643
 644                 lptimer3: timer@50022000 {
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647                         compatible = "st,stm32-lptimer";
 648                         reg = <0x50022000 0x400>;
 649                         clocks = <&rcc LPTIM3_K>;
 650                         clock-names = "mux";
 651                         status = "disabled";
 652
 653                         pwm {
 654                                 compatible = "st,stm32-pwm-lp";
 655                                 #pwm-cells = <3>;
 656                                 status = "disabled";
 657                         };
 658
 659                         trigger@2 {
 660                                 compatible = "st,stm32-lptimer-trigger";
 661                                 reg = <2>;
 662                                 status = "disabled";
 663                         };
 664                 };
 665
 666                 lptimer4: timer@50023000 {
 667                         compatible = "st,stm32-lptimer";
 668                         reg = <0x50023000 0x400>;
 669                         clocks = <&rcc LPTIM4_K>;
 670                         clock-names = "mux";
 671                         status = "disabled";
 672
 673                         pwm {
 674                                 compatible = "st,stm32-pwm-lp";
 675                                 #pwm-cells = <3>;
 676                                 status = "disabled";
 677                         };
 678                 };
 679
 680                 lptimer5: timer@50024000 {
 681                         compatible = "st,stm32-lptimer";
 682                         reg = <0x50024000 0x400>;
 683                         clocks = <&rcc LPTIM5_K>;
 684                         clock-names = "mux";
 685                         status = "disabled";
 686
 687                         pwm {
 688                                 compatible = "st,stm32-pwm-lp";
 689                                 #pwm-cells = <3>;
 690                                 status = "disabled";
 691                         };
 692                 };
 693
 694                 vrefbuf: vrefbuf@50025000 {
 695                         compatible = "st,stm32-vrefbuf";
 696                         reg = <0x50025000 0x8>;
 697                         regulator-min-microvolt = <1500000>;
 698                         regulator-max-microvolt = <2500000>;
 699                         clocks = <&rcc VREF>;
 700                         status = "disabled";
 701                 };
 702
 703                 cryp1: cryp@54001000 {
 704                         compatible = "st,stm32mp1-cryp";
 705                         reg = <0x54001000 0x400>;
 706                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&rcc CRYP1>;
 708                         resets = <&rcc CRYP1_R>;
 709                         status = "disabled";
 710                 };
 711
 712                 rng1: rng@54003000 {
 713                         compatible = "st,stm32-rng";
 714                         reg = <0x54003000 0x400>;
 715                         clocks = <&rcc RNG1_K>;
 716                         resets = <&rcc RNG1_R>;
 717                         status = "disabled";
 718                 };
 719
 720                 mdma1: dma@58000000 {
 721                         compatible = "st,stm32h7-mdma";
 722                         reg = <0x58000000 0x1000>;
 723                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&rcc MDMA>;
 725                         #dma-cells = <5>;
 726                         dma-channels = <32>;
 727                         dma-requests = <48>;
 728                 };
 729
 730                 qspi: qspi@58003000 {
 731                         compatible = "st,stm32f469-qspi";
 732                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
 733                         reg-names = "qspi", "qspi_mm";
 734                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&rcc QSPI_K>;
 736                         resets = <&rcc QSPI_R>;
 737                         status = "disabled";
 738                 };
 739
 740                 crc1: crc@58009000 {
 741                         compatible = "st,stm32f7-crc";
 742                         reg = <0x58009000 0x400>;
 743                         clocks = <&rcc CRC1>;
 744                         status = "disabled";
 745                 };
 746
 747                 usbh_ohci: usbh-ohci@5800c000 {
 748                         compatible = "generic-ohci";
 749                         reg = <0x5800c000 0x1000>;
 750                         clocks = <&rcc USBH>;
 751                         resets = <&rcc USBH_R>;
 752                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 753                         status = "disabled";
 754                 };
 755
 756                 usbh_ehci: usbh-ehci@5800d000 {
 757                         compatible = "generic-ehci";
 758                         reg = <0x5800d000 0x1000>;
 759                         clocks = <&rcc USBH>;
 760                         resets = <&rcc USBH_R>;
 761                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 762                         companion = <&usbh_ohci>;
 763                         status = "disabled";
 764                 };
 765
 766                 dsi: dsi@5a000000 {
 767                         compatible = "st,stm32-dsi";
 768                         reg = <0x5a000000 0x800>;
 769                         clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
 770                         clock-names = "pclk", "ref", "px_clk";
 771                         resets = <&rcc DSI_R>;
 772                         reset-names = "apb";
 773                         status = "disabled";
 774                 };
 775
 776                 ltdc: display-controller@5a001000 {
 777                         compatible = "st,stm32-ltdc";
 778                         reg = <0x5a001000 0x400>;
 779                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 780                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 781                         clocks = <&rcc LTDC_PX>;
 782                         clock-names = "lcd";
 783                         resets = <&rcc LTDC_R>;
 784                         status = "disabled";
 785                 };
 786
 787                 usbphyc: usbphyc@5a006000 {
 788                         #address-cells = <1>;
 789                         #size-cells = <0>;
 790                         compatible = "st,stm32mp1-usbphyc";
 791                         reg = <0x5a006000 0x1000>;
 792                         clocks = <&rcc USBPHY_K>;
 793                         resets = <&rcc USBPHY_R>;
 794                         status = "disabled";
 795
 796                         usbphyc_port0: usb-phy@0 {
 797                                 #phy-cells = <0>;
 798                                 reg = <0>;
 799                         };
 800
 801                         usbphyc_port1: usb-phy@1 {
 802                                 #phy-cells = <1>;
 803                                 reg = <1>;
 804                         };
 805                 };
 806
 807                 usart1: serial@5c000000 {
 808                         compatible = "st,stm32h7-uart";
 809                         reg = <0x5c000000 0x400>;
 810                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 811                         clocks = <&rcc USART1_K>;
 812                         status = "disabled";
 813                 };
 814
 815                 i2c4: i2c@5c002000 {
 816                         compatible = "st,stm32f7-i2c";
 817                         reg = <0x5c002000 0x400>;
 818                         interrupt-names = "event", "error";
 819                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 820                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 821                         clocks = <&rcc I2C4_K>;
 822                         resets = <&rcc I2C4_R>;
 823                         #address-cells = <1>;
 824                         #size-cells = <0>;
 825                         status = "disabled";
 826                 };
 827
 828                 i2c6: i2c@5c009000 {
 829                         compatible = "st,stm32f7-i2c";
 830                         reg = <0x5c009000 0x400>;
 831                         interrupt-names = "event", "error";
 832                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 833                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 834                         clocks = <&rcc I2C6_K>;
 835                         resets = <&rcc I2C6_R>;
 836                         #address-cells = <1>;
 837                         #size-cells = <0>;
 838                         status = "disabled";
 839                 };
 840         };
 841 };