arch/arm/boot/dts/stm32mp157-pinctrl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
   7
   8 / {
   9         soc {
  10                 pinctrl: pin-controller {
  11                         #address-cells = <1>;
  12                         #size-cells = <1>;
  13                         compatible = "st,stm32mp157-pinctrl";
  14                         ranges = <0 0x50002000 0xa400>;
  15                         pins-are-numbered;
  16
  17                         gpioa: gpio@50002000 {
  18                                 gpio-controller;
  19                                 #gpio-cells = <2>;
  20                                 interrupt-controller;
  21                                 #interrupt-cells = <2>;
  22                                 reg = <0x0 0x400>;
  23                                 clocks = <&clk_pll3_p>;
  24                                 st,bank-name = "GPIOA";
  25                                 ngpios = <16>;
  26                                 gpio-ranges = <&pinctrl 0 0 16>;
  27                         };
  28
  29                         gpiob: gpio@50003000 {
  30                                 gpio-controller;
  31                                 #gpio-cells = <2>;
  32                                 interrupt-controller;
  33                                 #interrupt-cells = <2>;
  34                                 reg = <0x1000 0x400>;
  35                                 clocks = <&clk_pll3_p>;
  36                                 st,bank-name = "GPIOB";
  37                                 ngpios = <16>;
  38                                 gpio-ranges = <&pinctrl 0 16 16>;
  39                         };
  40
  41                         gpioc: gpio@50004000 {
  42                                 gpio-controller;
  43                                 #gpio-cells = <2>;
  44                                 interrupt-controller;
  45                                 #interrupt-cells = <2>;
  46                                 reg = <0x2000 0x400>;
  47                                 clocks = <&clk_pll3_p>;
  48                                 st,bank-name = "GPIOC";
  49                                 ngpios = <16>;
  50                                 gpio-ranges = <&pinctrl 0 32 16>;
  51                         };
  52
  53                         gpiod: gpio@50005000 {
  54                                 gpio-controller;
  55                                 #gpio-cells = <2>;
  56                                 interrupt-controller;
  57                                 #interrupt-cells = <2>;
  58                                 reg = <0x3000 0x400>;
  59                                 clocks = <&clk_pll3_p>;
  60                                 st,bank-name = "GPIOD";
  61                                 ngpios = <16>;
  62                                 gpio-ranges = <&pinctrl 0 48 16>;
  63                         };
  64
  65                         gpioe: gpio@50006000 {
  66                                 gpio-controller;
  67                                 #gpio-cells = <2>;
  68                                 interrupt-controller;
  69                                 #interrupt-cells = <2>;
  70                                 reg = <0x4000 0x400>;
  71                                 clocks = <&clk_pll3_p>;
  72                                 st,bank-name = "GPIOE";
  73                                 ngpios = <16>;
  74                                 gpio-ranges = <&pinctrl 0 64 16>;
  75                         };
  76
  77                         gpiof: gpio@50007000 {
  78                                 gpio-controller;
  79                                 #gpio-cells = <2>;
  80                                 interrupt-controller;
  81                                 #interrupt-cells = <2>;
  82                                 reg = <0x5000 0x400>;
  83                                 clocks = <&clk_pll3_p>;
  84                                 st,bank-name = "GPIOF";
  85                                 ngpios = <16>;
  86                                 gpio-ranges = <&pinctrl 0 80 16>;
  87                         };
  88
  89                         gpiog: gpio@50008000 {
  90                                 gpio-controller;
  91                                 #gpio-cells = <2>;
  92                                 interrupt-controller;
  93                                 #interrupt-cells = <2>;
  94                                 reg = <0x6000 0x400>;
  95                                 clocks = <&clk_pll3_p>;
  96                                 st,bank-name = "GPIOG";
  97                                 ngpios = <16>;
  98                                 gpio-ranges = <&pinctrl 0 96 16>;
  99                         };
 100
 101                         gpioh: gpio@50009000 {
 102                                 gpio-controller;
 103                                 #gpio-cells = <2>;
 104                                 interrupt-controller;
 105                                 #interrupt-cells = <2>;
 106                                 reg = <0x7000 0x400>;
 107                                 clocks = <&clk_pll3_p>;
 108                                 st,bank-name = "GPIOH";
 109                                 ngpios = <16>;
 110                                 gpio-ranges = <&pinctrl 0 112 16>;
 111                         };
 112
 113                         gpioi: gpio@5000a000 {
 114                                 gpio-controller;
 115                                 #gpio-cells = <2>;
 116                                 interrupt-controller;
 117                                 #interrupt-cells = <2>;
 118                                 reg = <0x8000 0x400>;
 119                                 clocks = <&clk_pll3_p>;
 120                                 st,bank-name = "GPIOI";
 121                                 ngpios = <16>;
 122                                 gpio-ranges = <&pinctrl 0 128 16>;
 123                         };
 124
 125                         gpioj: gpio@5000b000 {
 126                                 gpio-controller;
 127                                 #gpio-cells = <2>;
 128                                 interrupt-controller;
 129                                 #interrupt-cells = <2>;
 130                                 reg = <0x9000 0x400>;
 131                                 clocks = <&clk_pll3_p>;
 132                                 st,bank-name = "GPIOJ";
 133                                 ngpios = <16>;
 134                                 gpio-ranges = <&pinctrl 0 144 16>;
 135                         };
 136
 137                         gpiok: gpio@5000c000 {
 138                                 gpio-controller;
 139                                 #gpio-cells = <2>;
 140                                 interrupt-controller;
 141                                 #interrupt-cells = <2>;
 142                                 reg = <0xa000 0x400>;
 143                                 clocks = <&clk_pll3_p>;
 144                                 st,bank-name = "GPIOK";
 145                                 ngpios = <8>;
 146                                 gpio-ranges = <&pinctrl 0 160 8>;
 147                         };
 148
 149                         uart4_pins_a: uart4@0 {
 150                                 pins1 {
 151                                         pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
 152                                         bias-disable;
 153                                         drive-push-pull;
 154                                         slew-rate = <0>;
 155                                 };
 156                                 pins2 {
 157                                         pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
 158                                         bias-disable;
 159                                 };
 160                         };
 161                 };
 162
 163                 pinctrl_z: pin-controller-z {
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         compatible = "st,stm32mp157-z-pinctrl";
 167                         ranges = <0 0x54004000 0x400>;
 168                         pins-are-numbered;
 169                         status = "disabled";
 170
 171                         gpioz: gpio@54004000 {
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 interrupt-controller;
 175                                 #interrupt-cells = <2>;
 176                                 reg = <0 0x400>;
 177                                 clocks = <&clk_pll2_p>;
 178                                 st,bank-name = "GPIOZ";
 179                                 st,bank-ioport = <11>;
 180                                 ngpios = <8>;
 181                                 gpio-ranges = <&pinctrl_z 0 400 8>;
 182                         };
 183                 };
 184         };
 185 };