arch/arm/boot/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44 #include "armv7-m.dtsi"
  45 #include <dt-bindings/clock/stm32fx-clock.h>
  46 #include <dt-bindings/mfd/stm32f7-rcc.h>
  47
  48 / {
  49         clocks {
  50                 clk_hse: clk-hse {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <0>;
  54                 };
  55
  56                 clk-lse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 clk-lsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32000>;
  66                 };
  67
  68                 clk_i2s_ckin: clk-i2s-ckin {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <48000000>;
  72                 };
  73         };
  74
  75         soc {
  76                 timer2: timer@40000000 {
  77                         compatible = "st,stm32-timer";
  78                         reg = <0x40000000 0x400>;
  79                         interrupts = <28>;
  80                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  81                         status = "disabled";
  82                 };
  83
  84                 timers2: timers@40000000 {
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87                         compatible = "st,stm32-timers";
  88                         reg = <0x40000000 0x400>;
  89                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  90                         clock-names = "int";
  91                         status = "disabled";
  92
  93                         pwm {
  94                                 compatible = "st,stm32-pwm";
  95                                 status = "disabled";
  96                         };
  97
  98                         timer@1 {
  99                                 compatible = "st,stm32-timer-trigger";
 100                                 reg = <1>;
 101                                 status = "disabled";
 102                         };
 103                 };
 104
 105                 timer3: timer@40000400 {
 106                         compatible = "st,stm32-timer";
 107                         reg = <0x40000400 0x400>;
 108                         interrupts = <29>;
 109                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 110                         status = "disabled";
 111                 };
 112
 113                 timers3: timers@40000400 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         compatible = "st,stm32-timers";
 117                         reg = <0x40000400 0x400>;
 118                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 119                         clock-names = "int";
 120                         status = "disabled";
 121
 122                         pwm {
 123                                 compatible = "st,stm32-pwm";
 124                                 status = "disabled";
 125                         };
 126
 127                         timer@2 {
 128                                 compatible = "st,stm32-timer-trigger";
 129                                 reg = <2>;
 130                                 status = "disabled";
 131                         };
 132                 };
 133
 134                 timer4: timer@40000800 {
 135                         compatible = "st,stm32-timer";
 136                         reg = <0x40000800 0x400>;
 137                         interrupts = <30>;
 138                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 139                         status = "disabled";
 140                 };
 141
 142                 timers4: timers@40000800 {
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         compatible = "st,stm32-timers";
 146                         reg = <0x40000800 0x400>;
 147                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 148                         clock-names = "int";
 149                         status = "disabled";
 150
 151                         pwm {
 152                                 compatible = "st,stm32-pwm";
 153                                 status = "disabled";
 154                         };
 155
 156                         timer@3 {
 157                                 compatible = "st,stm32-timer-trigger";
 158                                 reg = <3>;
 159                                 status = "disabled";
 160                         };
 161                 };
 162
 163                 timer5: timer@40000c00 {
 164                         compatible = "st,stm32-timer";
 165                         reg = <0x40000c00 0x400>;
 166                         interrupts = <50>;
 167                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 168                 };
 169
 170                 timers5: timers@40000c00 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         compatible = "st,stm32-timers";
 174                         reg = <0x40000C00 0x400>;
 175                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 176                         clock-names = "int";
 177                         status = "disabled";
 178
 179                         pwm {
 180                                 compatible = "st,stm32-pwm";
 181                                 status = "disabled";
 182                         };
 183
 184                         timer@4 {
 185                                 compatible = "st,stm32-timer-trigger";
 186                                 reg = <4>;
 187                                 status = "disabled";
 188                         };
 189                 };
 190
 191                 timer6: timer@40001000 {
 192                         compatible = "st,stm32-timer";
 193                         reg = <0x40001000 0x400>;
 194                         interrupts = <54>;
 195                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 196                         status = "disabled";
 197                 };
 198
 199                 timers6: timers@40001000 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         compatible = "st,stm32-timers";
 203                         reg = <0x40001000 0x400>;
 204                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 205                         clock-names = "int";
 206                         status = "disabled";
 207
 208                         timer@5 {
 209                                 compatible = "st,stm32-timer-trigger";
 210                                 reg = <5>;
 211                                 status = "disabled";
 212                         };
 213                 };
 214
 215                 timer7: timer@40001400 {
 216                         compatible = "st,stm32-timer";
 217                         reg = <0x40001400 0x400>;
 218                         interrupts = <55>;
 219                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 220                         status = "disabled";
 221                 };
 222
 223                 timers7: timers@40001400 {
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         compatible = "st,stm32-timers";
 227                         reg = <0x40001400 0x400>;
 228                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 229                         clock-names = "int";
 230                         status = "disabled";
 231
 232                         timer@6 {
 233                                 compatible = "st,stm32-timer-trigger";
 234                                 reg = <6>;
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 timers12: timers@40001800 {
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         compatible = "st,stm32-timers";
 243                         reg = <0x40001800 0x400>;
 244                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 245                         clock-names = "int";
 246                         status = "disabled";
 247
 248                         pwm {
 249                                 compatible = "st,stm32-pwm";
 250                                 status = "disabled";
 251                         };
 252
 253                         timer@11 {
 254                                 compatible = "st,stm32-timer-trigger";
 255                                 reg = <11>;
 256                                 status = "disabled";
 257                         };
 258                 };
 259
 260                 timers13: timers@40001c00 {
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         compatible = "st,stm32-timers";
 264                         reg = <0x40001C00 0x400>;
 265                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 266                         clock-names = "int";
 267                         status = "disabled";
 268
 269                         pwm {
 270                                 compatible = "st,stm32-pwm";
 271                                 status = "disabled";
 272                         };
 273                 };
 274
 275                 timers14: timers@40002000 {
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         compatible = "st,stm32-timers";
 279                         reg = <0x40002000 0x400>;
 280                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 281                         clock-names = "int";
 282                         status = "disabled";
 283
 284                         pwm {
 285                                 compatible = "st,stm32-pwm";
 286                                 status = "disabled";
 287                         };
 288                 };
 289
 290                 rtc: rtc@40002800 {
 291                         compatible = "st,stm32-rtc";
 292                         reg = <0x40002800 0x400>;
 293                         clocks = <&rcc 1 CLK_RTC>;
 294                         clock-names = "ck_rtc";
 295                         assigned-clocks = <&rcc 1 CLK_RTC>;
 296                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 297                         interrupt-parent = <&exti>;
 298                         interrupts = <17 1>;
 299                         interrupt-names = "alarm";
 300                         st,syscfg = <&pwrcfg 0x00 0x100>;
 301                         status = "disabled";
 302                 };
 303
 304                 usart2: serial@40004400 {
 305                         compatible = "st,stm32f7-uart";
 306                         reg = <0x40004400 0x400>;
 307                         interrupts = <38>;
 308                         clocks = <&rcc 1 CLK_USART2>;
 309                         status = "disabled";
 310                 };
 311
 312                 usart3: serial@40004800 {
 313                         compatible = "st,stm32f7-uart";
 314                         reg = <0x40004800 0x400>;
 315                         interrupts = <39>;
 316                         clocks = <&rcc 1 CLK_USART3>;
 317                         status = "disabled";
 318                 };
 319
 320                 usart4: serial@40004c00 {
 321                         compatible = "st,stm32f7-uart";
 322                         reg = <0x40004c00 0x400>;
 323                         interrupts = <52>;
 324                         clocks = <&rcc 1 CLK_UART4>;
 325                         status = "disabled";
 326                 };
 327
 328                 usart5: serial@40005000 {
 329                         compatible = "st,stm32f7-uart";
 330                         reg = <0x40005000 0x400>;
 331                         interrupts = <53>;
 332                         clocks = <&rcc 1 CLK_UART5>;
 333                         status = "disabled";
 334                 };
 335
 336                 i2c1: i2c@40005400 {
 337                         compatible = "st,stm32f7-i2c";
 338                         reg = <0x40005400 0x400>;
 339                         interrupts = <31>,
 340                                      <32>;
 341                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 342                         clocks = <&rcc 1 CLK_I2C1>;
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         status = "disabled";
 346                 };
 347
 348                 i2c2: i2c@40005800 {
 349                         compatible = "st,stm32f7-i2c";
 350                         reg = <0x40005800 0x400>;
 351                         interrupts = <33>,
 352                                      <34>;
 353                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 354                         clocks = <&rcc 1 CLK_I2C2>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         status = "disabled";
 358                 };
 359
 360                 i2c3: i2c@40005C00 {
 361                         compatible = "st,stm32f7-i2c";
 362                         reg = <0x40005C00 0x400>;
 363                         interrupts = <72>,
 364                                      <73>;
 365                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 366                         clocks = <&rcc 1 CLK_I2C3>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         status = "disabled";
 370                 };
 371
 372                 i2c4: i2c@40006000 {
 373                         compatible = "st,stm32f7-i2c";
 374                         reg = <0x40006000 0x400>;
 375                         interrupts = <95>,
 376                                      <96>;
 377                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 378                         clocks = <&rcc 1 CLK_I2C4>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         status = "disabled";
 382                 };
 383
 384                 cec: cec@40006c00 {
 385                         compatible = "st,stm32-cec";
 386                         reg = <0x40006C00 0x400>;
 387                         interrupts = <94>;
 388                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 389                         clock-names = "cec", "hdmi-cec";
 390                         status = "disabled";
 391                 };
 392
 393                 usart7: serial@40007800 {
 394                         compatible = "st,stm32f7-uart";
 395                         reg = <0x40007800 0x400>;
 396                         interrupts = <82>;
 397                         clocks = <&rcc 1 CLK_UART7>;
 398                         status = "disabled";
 399                 };
 400
 401                 usart8: serial@40007c00 {
 402                         compatible = "st,stm32f7-uart";
 403                         reg = <0x40007c00 0x400>;
 404                         interrupts = <83>;
 405                         clocks = <&rcc 1 CLK_UART8>;
 406                         status = "disabled";
 407                 };
 408
 409                 timers1: timers@40010000 {
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         compatible = "st,stm32-timers";
 413                         reg = <0x40010000 0x400>;
 414                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 415                         clock-names = "int";
 416                         status = "disabled";
 417
 418                         pwm {
 419                                 compatible = "st,stm32-pwm";
 420                                 status = "disabled";
 421                         };
 422
 423                         timer@0 {
 424                                 compatible = "st,stm32-timer-trigger";
 425                                 reg = <0>;
 426                                 status = "disabled";
 427                         };
 428                 };
 429
 430                 timers8: timers@40010400 {
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         compatible = "st,stm32-timers";
 434                         reg = <0x40010400 0x400>;
 435                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 436                         clock-names = "int";
 437                         status = "disabled";
 438
 439                         pwm {
 440                                 compatible = "st,stm32-pwm";
 441                                 status = "disabled";
 442                         };
 443
 444                         timer@7 {
 445                                 compatible = "st,stm32-timer-trigger";
 446                                 reg = <7>;
 447                                 status = "disabled";
 448                         };
 449                 };
 450
 451                 usart1: serial@40011000 {
 452                         compatible = "st,stm32f7-uart";
 453                         reg = <0x40011000 0x400>;
 454                         interrupts = <37>;
 455                         clocks = <&rcc 1 CLK_USART1>;
 456                         status = "disabled";
 457                 };
 458
 459                 usart6: serial@40011400 {
 460                         compatible = "st,stm32f7-uart";
 461                         reg = <0x40011400 0x400>;
 462                         interrupts = <71>;
 463                         clocks = <&rcc 1 CLK_USART6>;
 464                         status = "disabled";
 465                 };
 466
 467                 sdio2: sdio2@40011c00 {
 468                         compatible = "arm,pl180", "arm,primecell";
 469                         arm,primecell-periphid = <0x00880180>;
 470                         reg = <0x40011c00 0x400>;
 471                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 472                         clock-names = "apb_pclk";
 473                         interrupts = <103>;
 474                         max-frequency = <48000000>;
 475                         status = "disabled";
 476                 };
 477
 478                 sdio1: sdio1@40012c00 {
 479                         compatible = "arm,pl180", "arm,primecell";
 480                         arm,primecell-periphid = <0x00880180>;
 481                         reg = <0x40012c00 0x400>;
 482                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 483                         clock-names = "apb_pclk";
 484                         interrupts = <49>;
 485                         max-frequency = <48000000>;
 486                         status = "disabled";
 487                 };
 488
 489                 syscfg: system-config@40013800 {
 490                         compatible = "syscon";
 491                         reg = <0x40013800 0x400>;
 492                 };
 493
 494                 exti: interrupt-controller@40013c00 {
 495                         compatible = "st,stm32-exti";
 496                         interrupt-controller;
 497                         #interrupt-cells = <2>;
 498                         reg = <0x40013C00 0x400>;
 499                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 500                 };
 501
 502                 timers9: timers@40014000 {
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         compatible = "st,stm32-timers";
 506                         reg = <0x40014000 0x400>;
 507                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 508                         clock-names = "int";
 509                         status = "disabled";
 510
 511                         pwm {
 512                                 compatible = "st,stm32-pwm";
 513                                 status = "disabled";
 514                         };
 515
 516                         timer@8 {
 517                                 compatible = "st,stm32-timer-trigger";
 518                                 reg = <8>;
 519                                 status = "disabled";
 520                         };
 521                 };
 522
 523                 timers10: timers@40014400 {
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         compatible = "st,stm32-timers";
 527                         reg = <0x40014400 0x400>;
 528                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 529                         clock-names = "int";
 530                         status = "disabled";
 531
 532                         pwm {
 533                                 compatible = "st,stm32-pwm";
 534                                 status = "disabled";
 535                         };
 536                 };
 537
 538                 timers11: timers@40014800 {
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                         compatible = "st,stm32-timers";
 542                         reg = <0x40014800 0x400>;
 543                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 544                         clock-names = "int";
 545                         status = "disabled";
 546
 547                         pwm {
 548                                 compatible = "st,stm32-pwm";
 549                                 status = "disabled";
 550                         };
 551                 };
 552
 553                 pwrcfg: power-config@40007000 {
 554                         compatible = "syscon";
 555                         reg = <0x40007000 0x400>;
 556                 };
 557
 558                 crc: crc@40023000 {
 559                         compatible = "st,stm32f7-crc";
 560                         reg = <0x40023000 0x400>;
 561                         clocks = <&rcc 0 12>;
 562                         status = "disabled";
 563                 };
 564
 565                 rcc: rcc@40023800 {
 566                         #reset-cells = <1>;
 567                         #clock-cells = <2>;
 568                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 569                         reg = <0x40023800 0x400>;
 570                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 571                         st,syscfg = <&pwrcfg>;
 572                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 573                         assigned-clock-rates = <1000000>;
 574                 };
 575
 576                 dma1: dma@40026000 {
 577                         compatible = "st,stm32-dma";
 578                         reg = <0x40026000 0x400>;
 579                         interrupts = <11>,
 580                                      <12>,
 581                                      <13>,
 582                                      <14>,
 583                                      <15>,
 584                                      <16>,
 585                                      <17>,
 586                                      <47>;
 587                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 588                         #dma-cells = <4>;
 589                         status = "disabled";
 590                 };
 591
 592                 dma2: dma@40026400 {
 593                         compatible = "st,stm32-dma";
 594                         reg = <0x40026400 0x400>;
 595                         interrupts = <56>,
 596                                      <57>,
 597                                      <58>,
 598                                      <59>,
 599                                      <60>,
 600                                      <68>,
 601                                      <69>,
 602                                      <70>;
 603                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 604                         #dma-cells = <4>;
 605                         st,mem2mem;
 606                         status = "disabled";
 607                 };
 608
 609                 usbotg_hs: usb@40040000 {
 610                         compatible = "st,stm32f7-hsotg";
 611                         reg = <0x40040000 0x40000>;
 612                         interrupts = <77>;
 613                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 614                         clock-names = "otg";
 615                         g-rx-fifo-size = <256>;
 616                         g-np-tx-fifo-size = <32>;
 617                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 618                         status = "disabled";
 619                 };
 620
 621                 usbotg_fs: usb@50000000 {
 622                         compatible = "st,stm32f4x9-fsotg";
 623                         reg = <0x50000000 0x40000>;
 624                         interrupts = <67>;
 625                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 626                         clock-names = "otg";
 627                         status = "disabled";
 628                 };
 629         };
 630 };
 631
 632 &systick {
 633         clocks = <&rcc 1 0>;
 634         status = "okay";
 635 };