arch/arm/boot/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44 #include "armv7-m.dtsi"
  45 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
  46 #include <dt-bindings/clock/stm32fx-clock.h>
  47 #include <dt-bindings/mfd/stm32f7-rcc.h>
  48
  49 / {
  50         clocks {
  51                 clk_hse: clk-hse {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <0>;
  55                 };
  56
  57                 clk-lse {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <32768>;
  61                 };
  62
  63                 clk-lsi {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32000>;
  67                 };
  68
  69                 clk_i2s_ckin: clk-i2s-ckin {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <48000000>;
  73                 };
  74         };
  75
  76         soc {
  77                 timer2: timer@40000000 {
  78                         compatible = "st,stm32-timer";
  79                         reg = <0x40000000 0x400>;
  80                         interrupts = <28>;
  81                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  82                         status = "disabled";
  83                 };
  84
  85                 timer3: timer@40000400 {
  86                         compatible = "st,stm32-timer";
  87                         reg = <0x40000400 0x400>;
  88                         interrupts = <29>;
  89                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
  90                         status = "disabled";
  91                 };
  92
  93                 timer4: timer@40000800 {
  94                         compatible = "st,stm32-timer";
  95                         reg = <0x40000800 0x400>;
  96                         interrupts = <30>;
  97                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
  98                         status = "disabled";
  99                 };
 100
 101                 timer5: timer@40000c00 {
 102                         compatible = "st,stm32-timer";
 103                         reg = <0x40000c00 0x400>;
 104                         interrupts = <50>;
 105                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 106                 };
 107
 108                 timer6: timer@40001000 {
 109                         compatible = "st,stm32-timer";
 110                         reg = <0x40001000 0x400>;
 111                         interrupts = <54>;
 112                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 113                         status = "disabled";
 114                 };
 115
 116                 timer7: timer@40001400 {
 117                         compatible = "st,stm32-timer";
 118                         reg = <0x40001400 0x400>;
 119                         interrupts = <55>;
 120                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 121                         status = "disabled";
 122                 };
 123
 124                 rtc: rtc@40002800 {
 125                         compatible = "st,stm32-rtc";
 126                         reg = <0x40002800 0x400>;
 127                         clocks = <&rcc 1 CLK_RTC>;
 128                         clock-names = "ck_rtc";
 129                         assigned-clocks = <&rcc 1 CLK_RTC>;
 130                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 131                         interrupt-parent = <&exti>;
 132                         interrupts = <17 1>;
 133                         interrupt-names = "alarm";
 134                         st,syscfg = <&pwrcfg>;
 135                         status = "disabled";
 136                 };
 137
 138                 usart2: serial@40004400 {
 139                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
 140                         reg = <0x40004400 0x400>;
 141                         interrupts = <38>;
 142                         clocks = <&rcc 1 CLK_USART2>;
 143                         status = "disabled";
 144                 };
 145
 146                 usart3: serial@40004800 {
 147                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
 148                         reg = <0x40004800 0x400>;
 149                         interrupts = <39>;
 150                         clocks = <&rcc 1 CLK_USART3>;
 151                         status = "disabled";
 152                 };
 153
 154                 usart4: serial@40004c00 {
 155                         compatible = "st,stm32f7-uart";
 156                         reg = <0x40004c00 0x400>;
 157                         interrupts = <52>;
 158                         clocks = <&rcc 1 CLK_UART4>;
 159                         status = "disabled";
 160                 };
 161
 162                 usart5: serial@40005000 {
 163                         compatible = "st,stm32f7-uart";
 164                         reg = <0x40005000 0x400>;
 165                         interrupts = <53>;
 166                         clocks = <&rcc 1 CLK_UART5>;
 167                         status = "disabled";
 168                 };
 169
 170                 usart7: serial@40007800 {
 171                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
 172                         reg = <0x40007800 0x400>;
 173                         interrupts = <82>;
 174                         clocks = <&rcc 1 CLK_UART7>;
 175                         status = "disabled";
 176                 };
 177
 178                 usart8: serial@40007c00 {
 179                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
 180                         reg = <0x40007c00 0x400>;
 181                         interrupts = <83>;
 182                         clocks = <&rcc 1 CLK_UART8>;
 183                         status = "disabled";
 184                 };
 185
 186                 usart1: serial@40011000 {
 187                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
 188                         reg = <0x40011000 0x400>;
 189                         interrupts = <37>;
 190                         clocks = <&rcc 1 CLK_USART1>;
 191                         status = "disabled";
 192                 };
 193
 194                 usart6: serial@40011400 {
 195                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
 196                         reg = <0x40011400 0x400>;
 197                         interrupts = <71>;
 198                         clocks = <&rcc 1 CLK_USART6>;
 199                         status = "disabled";
 200                 };
 201
 202                 syscfg: system-config@40013800 {
 203                         compatible = "syscon";
 204                         reg = <0x40013800 0x400>;
 205                 };
 206
 207                 exti: interrupt-controller@40013c00 {
 208                         compatible = "st,stm32-exti";
 209                         interrupt-controller;
 210                         #interrupt-cells = <2>;
 211                         reg = <0x40013C00 0x400>;
 212                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 213                 };
 214
 215                 pwrcfg: power-config@40007000 {
 216                         compatible = "syscon";
 217                         reg = <0x40007000 0x400>;
 218                 };
 219
 220                 pin-controller {
 221                         #address-cells = <1>;
 222                         #size-cells = <1>;
 223                         compatible = "st,stm32f746-pinctrl";
 224                         ranges = <0 0x40020000 0x3000>;
 225                         interrupt-parent = <&exti>;
 226                         st,syscfg = <&syscfg 0x8>;
 227                         pins-are-numbered;
 228
 229                         gpioa: gpio@40020000 {
 230                                 gpio-controller;
 231                                 #gpio-cells = <2>;
 232                                 interrupt-controller;
 233                                 #interrupt-cells = <2>;
 234                                 reg = <0x0 0x400>;
 235                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
 236                                 st,bank-name = "GPIOA";
 237                         };
 238
 239                         gpiob: gpio@40020400 {
 240                                 gpio-controller;
 241                                 #gpio-cells = <2>;
 242                                 interrupt-controller;
 243                                 #interrupt-cells = <2>;
 244                                 reg = <0x400 0x400>;
 245                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
 246                                 st,bank-name = "GPIOB";
 247                         };
 248
 249                         gpioc: gpio@40020800 {
 250                                 gpio-controller;
 251                                 #gpio-cells = <2>;
 252                                 interrupt-controller;
 253                                 #interrupt-cells = <2>;
 254                                 reg = <0x800 0x400>;
 255                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
 256                                 st,bank-name = "GPIOC";
 257                         };
 258
 259                         gpiod: gpio@40020c00 {
 260                                 gpio-controller;
 261                                 #gpio-cells = <2>;
 262                                 interrupt-controller;
 263                                 #interrupt-cells = <2>;
 264                                 reg = <0xc00 0x400>;
 265                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
 266                                 st,bank-name = "GPIOD";
 267                         };
 268
 269                         gpioe: gpio@40021000 {
 270                                 gpio-controller;
 271                                 #gpio-cells = <2>;
 272                                 interrupt-controller;
 273                                 #interrupt-cells = <2>;
 274                                 reg = <0x1000 0x400>;
 275                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
 276                                 st,bank-name = "GPIOE";
 277                         };
 278
 279                         gpiof: gpio@40021400 {
 280                                 gpio-controller;
 281                                 #gpio-cells = <2>;
 282                                 interrupt-controller;
 283                                 #interrupt-cells = <2>;
 284                                 reg = <0x1400 0x400>;
 285                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
 286                                 st,bank-name = "GPIOF";
 287                         };
 288
 289                         gpiog: gpio@40021800 {
 290                                 gpio-controller;
 291                                 #gpio-cells = <2>;
 292                                 interrupt-controller;
 293                                 #interrupt-cells = <2>;
 294                                 reg = <0x1800 0x400>;
 295                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
 296                                 st,bank-name = "GPIOG";
 297                         };
 298
 299                         gpioh: gpio@40021c00 {
 300                                 gpio-controller;
 301                                 #gpio-cells = <2>;
 302                                 interrupt-controller;
 303                                 #interrupt-cells = <2>;
 304                                 reg = <0x1c00 0x400>;
 305                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
 306                                 st,bank-name = "GPIOH";
 307                         };
 308
 309                         gpioi: gpio@40022000 {
 310                                 gpio-controller;
 311                                 #gpio-cells = <2>;
 312                                 interrupt-controller;
 313                                 #interrupt-cells = <2>;
 314                                 reg = <0x2000 0x400>;
 315                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
 316                                 st,bank-name = "GPIOI";
 317                         };
 318
 319                         gpioj: gpio@40022400 {
 320                                 gpio-controller;
 321                                 #gpio-cells = <2>;
 322                                 interrupt-controller;
 323                                 #interrupt-cells = <2>;
 324                                 reg = <0x2400 0x400>;
 325                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
 326                                 st,bank-name = "GPIOJ";
 327                         };
 328
 329                         gpiok: gpio@40022800 {
 330                                 gpio-controller;
 331                                 #gpio-cells = <2>;
 332                                 interrupt-controller;
 333                                 #interrupt-cells = <2>;
 334                                 reg = <0x2800 0x400>;
 335                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
 336                                 st,bank-name = "GPIOK";
 337                         };
 338
 339                         usart1_pins_a: usart1@0 {
 340                                 pins1 {
 341                                         pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
 342                                         bias-disable;
 343                                         drive-push-pull;
 344                                         slew-rate = <0>;
 345                                 };
 346                                 pins2 {
 347                                         pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
 348                                         bias-disable;
 349                                 };
 350                         };
 351
 352                         usart1_pins_b: usart1@1 {
 353                                 pins1 {
 354                                         pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
 355                                         bias-disable;
 356                                         drive-push-pull;
 357                                         slew-rate = <0>;
 358                                 };
 359                                 pins2 {
 360                                         pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
 361                                         bias-disable;
 362                                 };
 363                         };
 364                 };
 365
 366                 crc: crc@40023000 {
 367                         compatible = "st,stm32f7-crc";
 368                         reg = <0x40023000 0x400>;
 369                         clocks = <&rcc 0 12>;
 370                         status = "disabled";
 371                 };
 372
 373                 rcc: rcc@40023800 {
 374                         #reset-cells = <1>;
 375                         #clock-cells = <2>;
 376                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 377                         reg = <0x40023800 0x400>;
 378                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 379                         st,syscfg = <&pwrcfg>;
 380                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 381                         assigned-clock-rates = <1000000>;
 382                 };
 383         };
 384 };
 385
 386 &systick {
 387         clocks = <&rcc 1 0>;
 388         status = "okay";
 389 };