2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "skeleton.dtsi"
49 #include "armv7-m.dtsi"
50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
51 #include <dt-bindings/clock/stm32fx-clock.h>
52 #include <dt-bindings/mfd/stm32f4-rcc.h>
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
70 compatible = "fixed-clock";
71 clock-frequency = <32000>;
74 clk_i2s_ckin: i2s-ckin {
76 compatible = "fixed-clock";
77 clock-frequency = <0>;
82 timer2: timer@40000000 {
83 compatible = "st,stm32-timer";
84 reg = <0x40000000 0x400>;
86 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 timers2: timers@40000000 {
93 compatible = "st,stm32-timers";
94 reg = <0x40000000 0x400>;
95 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
100 compatible = "st,stm32-pwm";
105 compatible = "st,stm32-timer-trigger";
111 timer3: timer@40000400 {
112 compatible = "st,stm32-timer";
113 reg = <0x40000400 0x400>;
115 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 timers3: timers@40000400 {
120 #address-cells = <1>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000400 0x400>;
124 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
129 compatible = "st,stm32-pwm";
134 compatible = "st,stm32-timer-trigger";
140 timer4: timer@40000800 {
141 compatible = "st,stm32-timer";
142 reg = <0x40000800 0x400>;
144 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 timers4: timers@40000800 {
149 #address-cells = <1>;
151 compatible = "st,stm32-timers";
152 reg = <0x40000800 0x400>;
153 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
158 compatible = "st,stm32-pwm";
163 compatible = "st,stm32-timer-trigger";
169 timer5: timer@40000c00 {
170 compatible = "st,stm32-timer";
171 reg = <0x40000c00 0x400>;
173 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 timers5: timers@40000c00 {
177 #address-cells = <1>;
179 compatible = "st,stm32-timers";
180 reg = <0x40000C00 0x400>;
181 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
186 compatible = "st,stm32-pwm";
191 compatible = "st,stm32-timer-trigger";
197 timer6: timer@40001000 {
198 compatible = "st,stm32-timer";
199 reg = <0x40001000 0x400>;
201 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 timers6: timers@40001000 {
206 #address-cells = <1>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
210 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
215 compatible = "st,stm32-timer-trigger";
221 timer7: timer@40001400 {
222 compatible = "st,stm32-timer";
223 reg = <0x40001400 0x400>;
225 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
229 timers7: timers@40001400 {
230 #address-cells = <1>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
234 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
239 compatible = "st,stm32-timer-trigger";
245 timers12: timers@40001800 {
246 #address-cells = <1>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
250 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
255 compatible = "st,stm32-pwm";
260 compatible = "st,stm32-timer-trigger";
266 timers13: timers@40001c00 {
267 #address-cells = <1>;
269 compatible = "st,stm32-timers";
270 reg = <0x40001C00 0x400>;
271 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
276 compatible = "st,stm32-pwm";
281 timers14: timers@40002000 {
282 #address-cells = <1>;
284 compatible = "st,stm32-timers";
285 reg = <0x40002000 0x400>;
286 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
291 compatible = "st,stm32-pwm";
297 compatible = "st,stm32-rtc";
298 reg = <0x40002800 0x400>;
299 clocks = <&rcc 1 CLK_RTC>;
300 clock-names = "ck_rtc";
301 assigned-clocks = <&rcc 1 CLK_RTC>;
302 assigned-clock-parents = <&rcc 1 CLK_LSE>;
303 interrupt-parent = <&exti>;
305 interrupt-names = "alarm";
306 st,syscfg = <&pwrcfg>;
310 usart2: serial@40004400 {
311 compatible = "st,stm32-usart", "st,stm32-uart";
312 reg = <0x40004400 0x400>;
314 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
318 usart3: serial@40004800 {
319 compatible = "st,stm32-usart", "st,stm32-uart";
320 reg = <0x40004800 0x400>;
322 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
324 dmas = <&dma1 1 4 0x400 0x0>,
325 <&dma1 3 4 0x400 0x0>;
326 dma-names = "rx", "tx";
329 usart4: serial@40004c00 {
330 compatible = "st,stm32-uart";
331 reg = <0x40004c00 0x400>;
333 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
337 usart5: serial@40005000 {
338 compatible = "st,stm32-uart";
339 reg = <0x40005000 0x400>;
341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
346 compatible = "st,stm32f4-i2c";
347 reg = <0x40005400 0x400>;
350 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
351 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
352 #address-cells = <1>;
357 usart7: serial@40007800 {
358 compatible = "st,stm32-usart", "st,stm32-uart";
359 reg = <0x40007800 0x400>;
361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
365 usart8: serial@40007c00 {
366 compatible = "st,stm32-usart", "st,stm32-uart";
367 reg = <0x40007c00 0x400>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
373 timers1: timers@40010000 {
374 #address-cells = <1>;
376 compatible = "st,stm32-timers";
377 reg = <0x40010000 0x400>;
378 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
383 compatible = "st,stm32-pwm";
388 compatible = "st,stm32-timer-trigger";
394 timers8: timers@40010400 {
395 #address-cells = <1>;
397 compatible = "st,stm32-timers";
398 reg = <0x40010400 0x400>;
399 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
404 compatible = "st,stm32-pwm";
409 compatible = "st,stm32-timer-trigger";
415 usart1: serial@40011000 {
416 compatible = "st,stm32-usart", "st,stm32-uart";
417 reg = <0x40011000 0x400>;
419 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
421 dmas = <&dma2 2 4 0x400 0x0>,
422 <&dma2 7 4 0x400 0x0>;
423 dma-names = "rx", "tx";
426 usart6: serial@40011400 {
427 compatible = "st,stm32-usart", "st,stm32-uart";
428 reg = <0x40011400 0x400>;
430 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
435 compatible = "st,stm32f4-adc-core";
436 reg = <0x40012000 0x400>;
438 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
440 interrupt-controller;
441 #interrupt-cells = <1>;
442 #address-cells = <1>;
447 compatible = "st,stm32f4-adc";
448 #io-channel-cells = <1>;
450 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
451 interrupt-parent = <&adc>;
457 compatible = "st,stm32f4-adc";
458 #io-channel-cells = <1>;
460 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
461 interrupt-parent = <&adc>;
467 compatible = "st,stm32f4-adc";
468 #io-channel-cells = <1>;
470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
471 interrupt-parent = <&adc>;
477 syscfg: system-config@40013800 {
478 compatible = "syscon";
479 reg = <0x40013800 0x400>;
482 exti: interrupt-controller@40013c00 {
483 compatible = "st,stm32-exti";
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 reg = <0x40013C00 0x400>;
487 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
490 timers9: timers@40014000 {
491 #address-cells = <1>;
493 compatible = "st,stm32-timers";
494 reg = <0x40014000 0x400>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
500 compatible = "st,stm32-pwm";
505 compatible = "st,stm32-timer-trigger";
511 timers10: timers@40014400 {
512 #address-cells = <1>;
514 compatible = "st,stm32-timers";
515 reg = <0x40014400 0x400>;
516 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
521 compatible = "st,stm32-pwm";
526 timers11: timers@40014800 {
527 #address-cells = <1>;
529 compatible = "st,stm32-timers";
530 reg = <0x40014800 0x400>;
531 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
536 compatible = "st,stm32-pwm";
541 pwrcfg: power-config@40007000 {
542 compatible = "syscon";
543 reg = <0x40007000 0x400>;
547 #address-cells = <1>;
549 compatible = "st,stm32f429-pinctrl";
550 ranges = <0 0x40020000 0x3000>;
551 interrupt-parent = <&exti>;
552 st,syscfg = <&syscfg 0x8>;
555 gpioa: gpio@40020000 {
559 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
560 st,bank-name = "GPIOA";
563 gpiob: gpio@40020400 {
567 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
568 st,bank-name = "GPIOB";
571 gpioc: gpio@40020800 {
575 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
576 st,bank-name = "GPIOC";
579 gpiod: gpio@40020c00 {
583 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
584 st,bank-name = "GPIOD";
587 gpioe: gpio@40021000 {
590 reg = <0x1000 0x400>;
591 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
592 st,bank-name = "GPIOE";
595 gpiof: gpio@40021400 {
598 reg = <0x1400 0x400>;
599 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
600 st,bank-name = "GPIOF";
603 gpiog: gpio@40021800 {
606 reg = <0x1800 0x400>;
607 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
608 st,bank-name = "GPIOG";
611 gpioh: gpio@40021c00 {
614 reg = <0x1c00 0x400>;
615 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
616 st,bank-name = "GPIOH";
619 gpioi: gpio@40022000 {
622 reg = <0x2000 0x400>;
623 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
624 st,bank-name = "GPIOI";
627 gpioj: gpio@40022400 {
630 reg = <0x2400 0x400>;
631 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
632 st,bank-name = "GPIOJ";
635 gpiok: gpio@40022800 {
638 reg = <0x2800 0x400>;
639 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
640 st,bank-name = "GPIOK";
643 usart1_pins_a: usart1@0 {
645 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
651 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
656 usart3_pins_a: usart3@0 {
658 pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
664 pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
669 usbotg_hs_pins_a: usbotg_hs@0 {
671 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
672 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
673 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
674 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
675 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
676 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
677 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
678 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
679 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
680 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
681 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
682 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
689 ethernet_mii: mii@0 {
691 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
692 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
693 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
694 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
695 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
696 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
697 <STM32F429_PA2_FUNC_ETH_MDIO>,
698 <STM32F429_PC1_FUNC_ETH_MDC>,
699 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
700 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
701 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
702 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
703 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
704 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
709 adc3_in8_pin: adc@200 {
711 pinmux = <STM32F429_PF10_FUNC_ANALOG>;
717 pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
718 <STM32F429_PB13_FUNC_TIM1_CH1N>,
719 <STM32F429_PB12_FUNC_TIM1_BKIN>;
725 pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
726 <STM32F429_PB5_FUNC_TIM3_CH2>;
732 pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
733 <STM32F429_PB6_FUNC_I2C1_SCL>;
744 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
745 reg = <0x40023800 0x400>;
746 clocks = <&clk_hse>, <&clk_i2s_ckin>;
747 st,syscfg = <&pwrcfg>;
748 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
749 assigned-clock-rates = <1000000>;
752 dma1: dma-controller@40026000 {
753 compatible = "st,stm32-dma";
754 reg = <0x40026000 0x400>;
763 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
767 dma2: dma-controller@40026400 {
768 compatible = "st,stm32-dma";
769 reg = <0x40026400 0x400>;
778 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
783 mac: ethernet@40028000 {
784 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
785 reg = <0x40028000 0x8000>;
786 reg-names = "stmmaceth";
788 interrupt-names = "macirq";
789 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
790 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
791 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
792 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
793 st,syscon = <&syscfg 0x4>;
799 usbotg_hs: usb@40040000 {
800 compatible = "snps,dwc2";
801 reg = <0x40040000 0x40000>;
803 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
809 compatible = "st,stm32-rng";
810 reg = <0x50060800 0x400>;
812 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
819 clocks = <&rcc 1 SYSTICK>;