arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton.dtsi"
  49 #include "armv7-m.dtsi"
  50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  51
  52 / {
  53         clocks {
  54                 clk_hse: clk-hse {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-clock";
  57                         clock-frequency = <0>;
  58                 };
  59
  60                 clk-lse {
  61                         #clock-cells = <0>;
  62                         compatible = "fixed-clock";
  63                         clock-frequency = <32768>;
  64                 };
  65
  66                 clk-lsi {
  67                         #clock-cells = <0>;
  68                         compatible = "fixed-clock";
  69                         clock-frequency = <32000>;
  70                 };
  71         };
  72
  73         soc {
  74                 timer2: timer@40000000 {
  75                         compatible = "st,stm32-timer";
  76                         reg = <0x40000000 0x400>;
  77                         interrupts = <28>;
  78                         clocks = <&rcc 0 128>;
  79                         status = "disabled";
  80                 };
  81
  82                 timer3: timer@40000400 {
  83                         compatible = "st,stm32-timer";
  84                         reg = <0x40000400 0x400>;
  85                         interrupts = <29>;
  86                         clocks = <&rcc 0 129>;
  87                         status = "disabled";
  88                 };
  89
  90                 timer4: timer@40000800 {
  91                         compatible = "st,stm32-timer";
  92                         reg = <0x40000800 0x400>;
  93                         interrupts = <30>;
  94                         clocks = <&rcc 0 130>;
  95                         status = "disabled";
  96                 };
  97
  98                 timer5: timer@40000c00 {
  99                         compatible = "st,stm32-timer";
 100                         reg = <0x40000c00 0x400>;
 101                         interrupts = <50>;
 102                         clocks = <&rcc 0 131>;
 103                 };
 104
 105                 timer6: timer@40001000 {
 106                         compatible = "st,stm32-timer";
 107                         reg = <0x40001000 0x400>;
 108                         interrupts = <54>;
 109                         clocks = <&rcc 0 132>;
 110                         status = "disabled";
 111                 };
 112
 113                 timer7: timer@40001400 {
 114                         compatible = "st,stm32-timer";
 115                         reg = <0x40001400 0x400>;
 116                         interrupts = <55>;
 117                         clocks = <&rcc 0 133>;
 118                         status = "disabled";
 119                 };
 120
 121                 usart2: serial@40004400 {
 122                         compatible = "st,stm32-usart", "st,stm32-uart";
 123                         reg = <0x40004400 0x400>;
 124                         interrupts = <38>;
 125                         clocks =  <&rcc 0 145>;
 126                         status = "disabled";
 127                 };
 128
 129                 usart3: serial@40004800 {
 130                         compatible = "st,stm32-usart", "st,stm32-uart";
 131                         reg = <0x40004800 0x400>;
 132                         interrupts = <39>;
 133                         clocks = <&rcc 0 146>;
 134                         status = "disabled";
 135                         dmas = <&dma1 1 4 0x400 0x0>,
 136                                <&dma1 3 4 0x400 0x0>;
 137                         dma-names = "rx", "tx";
 138                 };
 139
 140                 usart4: serial@40004c00 {
 141                         compatible = "st,stm32-uart";
 142                         reg = <0x40004c00 0x400>;
 143                         interrupts = <52>;
 144                         clocks = <&rcc 0 147>;
 145                         status = "disabled";
 146                 };
 147
 148                 usart5: serial@40005000 {
 149                         compatible = "st,stm32-uart";
 150                         reg = <0x40005000 0x400>;
 151                         interrupts = <53>;
 152                         clocks = <&rcc 0 148>;
 153                         status = "disabled";
 154                 };
 155
 156                 usart7: serial@40007800 {
 157                         compatible = "st,stm32-usart", "st,stm32-uart";
 158                         reg = <0x40007800 0x400>;
 159                         interrupts = <82>;
 160                         clocks = <&rcc 0 158>;
 161                         status = "disabled";
 162                 };
 163
 164                 usart8: serial@40007c00 {
 165                         compatible = "st,stm32-usart", "st,stm32-uart";
 166                         reg = <0x40007c00 0x400>;
 167                         interrupts = <83>;
 168                         clocks = <&rcc 0 159>;
 169                         status = "disabled";
 170                 };
 171
 172                 usart1: serial@40011000 {
 173                         compatible = "st,stm32-usart", "st,stm32-uart";
 174                         reg = <0x40011000 0x400>;
 175                         interrupts = <37>;
 176                         clocks = <&rcc 0 164>;
 177                         status = "disabled";
 178                         dmas = <&dma2 2 4 0x400 0x0>,
 179                                <&dma2 7 4 0x400 0x0>;
 180                         dma-names = "rx", "tx";
 181                 };
 182
 183                 usart6: serial@40011400 {
 184                         compatible = "st,stm32-usart", "st,stm32-uart";
 185                         reg = <0x40011400 0x400>;
 186                         interrupts = <71>;
 187                         clocks = <&rcc 0 165>;
 188                         status = "disabled";
 189                 };
 190
 191                 syscfg: system-config@40013800 {
 192                         compatible = "syscon";
 193                         reg = <0x40013800 0x400>;
 194                 };
 195
 196                 exti: interrupt-controller@40013c00 {
 197                         compatible = "st,stm32-exti";
 198                         interrupt-controller;
 199                         #interrupt-cells = <2>;
 200                         reg = <0x40013C00 0x400>;
 201                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 202                 };
 203
 204                 pwrcfg: power-config@40007000 {
 205                         compatible = "syscon";
 206                         reg = <0x40007000 0x400>;
 207                 };
 208
 209                 pin-controller {
 210                         #address-cells = <1>;
 211                         #size-cells = <1>;
 212                         compatible = "st,stm32f429-pinctrl";
 213                         ranges = <0 0x40020000 0x3000>;
 214                         interrupt-parent = <&exti>;
 215                         st,syscfg = <&syscfg 0x8>;
 216                         pins-are-numbered;
 217
 218                         gpioa: gpio@40020000 {
 219                                 gpio-controller;
 220                                 #gpio-cells = <2>;
 221                                 reg = <0x0 0x400>;
 222                                 clocks = <&rcc 0 0>;
 223                                 st,bank-name = "GPIOA";
 224                         };
 225
 226                         gpiob: gpio@40020400 {
 227                                 gpio-controller;
 228                                 #gpio-cells = <2>;
 229                                 reg = <0x400 0x400>;
 230                                 clocks = <&rcc 0 1>;
 231                                 st,bank-name = "GPIOB";
 232                         };
 233
 234                         gpioc: gpio@40020800 {
 235                                 gpio-controller;
 236                                 #gpio-cells = <2>;
 237                                 reg = <0x800 0x400>;
 238                                 clocks = <&rcc 0 2>;
 239                                 st,bank-name = "GPIOC";
 240                         };
 241
 242                         gpiod: gpio@40020c00 {
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 reg = <0xc00 0x400>;
 246                                 clocks = <&rcc 0 3>;
 247                                 st,bank-name = "GPIOD";
 248                         };
 249
 250                         gpioe: gpio@40021000 {
 251                                 gpio-controller;
 252                                 #gpio-cells = <2>;
 253                                 reg = <0x1000 0x400>;
 254                                 clocks = <&rcc 0 4>;
 255                                 st,bank-name = "GPIOE";
 256                         };
 257
 258                         gpiof: gpio@40021400 {
 259                                 gpio-controller;
 260                                 #gpio-cells = <2>;
 261                                 reg = <0x1400 0x400>;
 262                                 clocks = <&rcc 0 5>;
 263                                 st,bank-name = "GPIOF";
 264                         };
 265
 266                         gpiog: gpio@40021800 {
 267                                 gpio-controller;
 268                                 #gpio-cells = <2>;
 269                                 reg = <0x1800 0x400>;
 270                                 clocks = <&rcc 0 6>;
 271                                 st,bank-name = "GPIOG";
 272                         };
 273
 274                         gpioh: gpio@40021c00 {
 275                                 gpio-controller;
 276                                 #gpio-cells = <2>;
 277                                 reg = <0x1c00 0x400>;
 278                                 clocks = <&rcc 0 7>;
 279                                 st,bank-name = "GPIOH";
 280                         };
 281
 282                         gpioi: gpio@40022000 {
 283                                 gpio-controller;
 284                                 #gpio-cells = <2>;
 285                                 reg = <0x2000 0x400>;
 286                                 clocks = <&rcc 0 8>;
 287                                 st,bank-name = "GPIOI";
 288                         };
 289
 290                         gpioj: gpio@40022400 {
 291                                 gpio-controller;
 292                                 #gpio-cells = <2>;
 293                                 reg = <0x2400 0x400>;
 294                                 clocks = <&rcc 0 9>;
 295                                 st,bank-name = "GPIOJ";
 296                         };
 297
 298                         gpiok: gpio@40022800 {
 299                                 gpio-controller;
 300                                 #gpio-cells = <2>;
 301                                 reg = <0x2800 0x400>;
 302                                 clocks = <&rcc 0 10>;
 303                                 st,bank-name = "GPIOK";
 304                         };
 305
 306                         usart1_pins_a: usart1@0 {
 307                                 pins1 {
 308                                         pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
 309                                         bias-disable;
 310                                         drive-push-pull;
 311                                         slew-rate = <0>;
 312                                 };
 313                                 pins2 {
 314                                         pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
 315                                         bias-disable;
 316                                 };
 317                         };
 318
 319                         usbotg_hs_pins_a: usbotg_hs@0 {
 320                                 pins {
 321                                         pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
 322                                                  <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
 323                                                  <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
 324                                                  <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
 325                                                  <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
 326                                                  <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
 327                                                  <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
 328                                                  <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
 329                                                  <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
 330                                                  <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
 331                                                  <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
 332                                                  <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
 333                                         bias-disable;
 334                                         drive-push-pull;
 335                                         slew-rate = <2>;
 336                                 };
 337                         };
 338
 339                         ethernet_mii: mii@0 {
 340                                 pins {
 341                                         pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
 342                                                  <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
 343                                                  <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
 344                                                  <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
 345                                                  <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
 346                                                  <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
 347                                                  <STM32F429_PA2_FUNC_ETH_MDIO>,
 348                                                  <STM32F429_PC1_FUNC_ETH_MDC>,
 349                                                  <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
 350                                                  <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
 351                                                  <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
 352                                                  <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
 353                                                  <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
 354                                                  <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
 355                                         slew-rate = <2>;
 356                                 };
 357                         };
 358                 };
 359
 360                 rcc: rcc@40023810 {
 361                         #reset-cells = <1>;
 362                         #clock-cells = <2>;
 363                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 364                         reg = <0x40023800 0x400>;
 365                         clocks = <&clk_hse>;
 366                         st,syscfg = <&pwrcfg>;
 367                 };
 368
 369                 dma1: dma-controller@40026000 {
 370                         compatible = "st,stm32-dma";
 371                         reg = <0x40026000 0x400>;
 372                         interrupts = <11>,
 373                                      <12>,
 374                                      <13>,
 375                                      <14>,
 376                                      <15>,
 377                                      <16>,
 378                                      <17>,
 379                                      <47>;
 380                         clocks = <&rcc 0 21>;
 381                         #dma-cells = <4>;
 382                 };
 383
 384                 dma2: dma-controller@40026400 {
 385                         compatible = "st,stm32-dma";
 386                         reg = <0x40026400 0x400>;
 387                         interrupts = <56>,
 388                                      <57>,
 389                                      <58>,
 390                                      <59>,
 391                                      <60>,
 392                                      <68>,
 393                                      <69>,
 394                                      <70>;
 395                         clocks = <&rcc 0 22>;
 396                         #dma-cells = <4>;
 397                         st,mem2mem;
 398                 };
 399
 400                 mac: ethernet@40028000 {
 401                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 402                         reg = <0x40028000 0x8000>;
 403                         reg-names = "stmmaceth";
 404                         interrupts = <61>;
 405                         interrupt-names = "macirq";
 406                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 407                         clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
 408                         st,syscon = <&syscfg 0x4>;
 409                         snps,pbl = <8>;
 410                         snps,mixed-burst;
 411                         status = "disabled";
 412                 };
 413
 414                 usbotg_hs: usb@40040000 {
 415                         compatible = "snps,dwc2";
 416                         reg = <0x40040000 0x40000>;
 417                         interrupts = <77>;
 418                         clocks = <&rcc 0 29>;
 419                         clock-names = "otg";
 420                         status = "disabled";
 421                 };
 422
 423                 rng: rng@50060800 {
 424                         compatible = "st,stm32-rng";
 425                         reg = <0x50060800 0x400>;
 426                         interrupts = <80>;
 427                         clocks = <&rcc 0 38>;
 428                 };
 429         };
 430 };
 431
 432 &systick {
 433         clocks = <&rcc 1 0>;
 434         status = "okay";
 435 };