arch/arm/boot/dts/stm32f4-pinctrl.dtsi

   1 /*
   2  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  44 #include <dt-bindings/mfd/stm32f4-rcc.h>
  45
  46 / {
  47         soc {
  48                 pinctrl: pin-controller {
  49                         #address-cells = <1>;
  50                         #size-cells = <1>;
  51                         ranges = <0 0x40020000 0x3000>;
  52                         interrupt-parent = <&exti>;
  53                         st,syscfg = <&syscfg 0x8>;
  54                         pins-are-numbered;
  55
  56                         gpioa: gpio@40020000 {
  57                                 gpio-controller;
  58                                 #gpio-cells = <2>;
  59                                 interrupt-controller;
  60                                 #interrupt-cells = <2>;
  61                                 reg = <0x0 0x400>;
  62                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
  63                                 st,bank-name = "GPIOA";
  64                         };
  65
  66                         gpiob: gpio@40020400 {
  67                                 gpio-controller;
  68                                 #gpio-cells = <2>;
  69                                 interrupt-controller;
  70                                 #interrupt-cells = <2>;
  71                                 reg = <0x400 0x400>;
  72                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
  73                                 st,bank-name = "GPIOB";
  74                         };
  75
  76                         gpioc: gpio@40020800 {
  77                                 gpio-controller;
  78                                 #gpio-cells = <2>;
  79                                 interrupt-controller;
  80                                 #interrupt-cells = <2>;
  81                                 reg = <0x800 0x400>;
  82                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
  83                                 st,bank-name = "GPIOC";
  84                         };
  85
  86                         gpiod: gpio@40020c00 {
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89                                 interrupt-controller;
  90                                 #interrupt-cells = <2>;
  91                                 reg = <0xc00 0x400>;
  92                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
  93                                 st,bank-name = "GPIOD";
  94                         };
  95
  96                         gpioe: gpio@40021000 {
  97                                 gpio-controller;
  98                                 #gpio-cells = <2>;
  99                                 interrupt-controller;
 100                                 #interrupt-cells = <2>;
 101                                 reg = <0x1000 0x400>;
 102                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
 103                                 st,bank-name = "GPIOE";
 104                         };
 105
 106                         gpiof: gpio@40021400 {
 107                                 gpio-controller;
 108                                 #gpio-cells = <2>;
 109                                 interrupt-controller;
 110                                 #interrupt-cells = <2>;
 111                                 reg = <0x1400 0x400>;
 112                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
 113                                 st,bank-name = "GPIOF";
 114                         };
 115
 116                         gpiog: gpio@40021800 {
 117                                 gpio-controller;
 118                                 #gpio-cells = <2>;
 119                                 interrupt-controller;
 120                                 #interrupt-cells = <2>;
 121                                 reg = <0x1800 0x400>;
 122                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
 123                                 st,bank-name = "GPIOG";
 124                         };
 125
 126                         gpioh: gpio@40021c00 {
 127                                 gpio-controller;
 128                                 #gpio-cells = <2>;
 129                                 interrupt-controller;
 130                                 #interrupt-cells = <2>;
 131                                 reg = <0x1c00 0x400>;
 132                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
 133                                 st,bank-name = "GPIOH";
 134                         };
 135
 136                         gpioi: gpio@40022000 {
 137                                 gpio-controller;
 138                                 #gpio-cells = <2>;
 139                                 interrupt-controller;
 140                                 #interrupt-cells = <2>;
 141                                 reg = <0x2000 0x400>;
 142                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
 143                                 st,bank-name = "GPIOI";
 144                         };
 145
 146                         gpioj: gpio@40022400 {
 147                                 gpio-controller;
 148                                 #gpio-cells = <2>;
 149                                 interrupt-controller;
 150                                 #interrupt-cells = <2>;
 151                                 reg = <0x2400 0x400>;
 152                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
 153                                 st,bank-name = "GPIOJ";
 154                         };
 155
 156                         gpiok: gpio@40022800 {
 157                                 gpio-controller;
 158                                 #gpio-cells = <2>;
 159                                 interrupt-controller;
 160                                 #interrupt-cells = <2>;
 161                                 reg = <0x2800 0x400>;
 162                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
 163                                 st,bank-name = "GPIOK";
 164                         };
 165
 166                         usart1_pins_a: usart1@0 {
 167                                 pins1 {
 168                                         pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
 169                                         bias-disable;
 170                                         drive-push-pull;
 171                                         slew-rate = <0>;
 172                                 };
 173                                 pins2 {
 174                                         pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
 175                                         bias-disable;
 176                                 };
 177                         };
 178
 179                         usart3_pins_a: usart3@0 {
 180                                 pins1 {
 181                                         pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
 182                                         bias-disable;
 183                                         drive-push-pull;
 184                                         slew-rate = <0>;
 185                                 };
 186                                 pins2 {
 187                                         pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
 188                                         bias-disable;
 189                                 };
 190                         };
 191
 192                         usbotg_fs_pins_a: usbotg_fs@0 {
 193                                 pins {
 194                                         pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
 195                                                  <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
 196                                                  <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
 197                                         bias-disable;
 198                                         drive-push-pull;
 199                                         slew-rate = <2>;
 200                                 };
 201                         };
 202
 203                         usbotg_fs_pins_b: usbotg_fs@1 {
 204                                 pins {
 205                                         pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
 206                                                  <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
 207                                                  <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
 208                                         bias-disable;
 209                                         drive-push-pull;
 210                                         slew-rate = <2>;
 211                                 };
 212                         };
 213
 214                         usbotg_hs_pins_a: usbotg_hs@0 {
 215                                 pins {
 216                                         pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
 217                                                  <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
 218                                                  <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
 219                                                  <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
 220                                                  <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
 221                                                  <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
 222                                                  <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
 223                                                  <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
 224                                                  <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
 225                                                  <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
 226                                                  <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
 227                                                  <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
 228                                         bias-disable;
 229                                         drive-push-pull;
 230                                         slew-rate = <2>;
 231                                 };
 232                         };
 233
 234                         ethernet_mii: mii@0 {
 235                                 pins {
 236                                         pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
 237                                                  <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
 238                                                  <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
 239                                                  <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
 240                                                  <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
 241                                                  <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
 242                                                  <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
 243                                                  <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
 244                                                  <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
 245                                                  <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
 246                                                  <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
 247                                                  <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
 248                                                  <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
 249                                                  <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
 250                                         slew-rate = <2>;
 251                                 };
 252                         };
 253
 254                         adc3_in8_pin: adc@200 {
 255                                 pins {
 256                                         pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
 257                                 };
 258                         };
 259
 260                         pwm1_pins: pwm@1 {
 261                                 pins {
 262                                         pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
 263                                                  <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
 264                                                  <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
 265                                 };
 266                         };
 267
 268                         pwm3_pins: pwm@3 {
 269                                 pins {
 270                                         pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
 271                                                  <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
 272                                 };
 273                         };
 274
 275                         i2c1_pins: i2c1@0 {
 276                                 pins {
 277                                         pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
 278                                                  <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
 279                                         bias-disable;
 280                                         drive-open-drain;
 281                                         slew-rate = <3>;
 282                                 };
 283                         };
 284
 285                         ltdc_pins: ltdc@0 {
 286                                 pins {
 287                                         pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
 288                                                  <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
 289                                                  <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
 290                                                  <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
 291                                                  <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
 292                                                  <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
 293                                                  <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
 294                                                  <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
 295                                                  <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
 296                                                  <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
 297                                                  <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
 298                                                  <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
 299                                                  <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
 300                                                  <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
 301                                                  <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
 302                                                  <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
 303                                                  <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
 304                                                  <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
 305                                                  <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
 306                                                  <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
 307                                                  <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
 308                                                  <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
 309                                                  <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
 310                                                  <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
 311                                                  <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
 312                                                  <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
 313                                                  <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
 314                                                  <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
 315                                         slew-rate = <2>;
 316                                 };
 317                         };
 318
 319                         dcmi_pins: dcmi@0 {
 320                                 pins {
 321                                         pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
 322                                                  <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
 323                                                  <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
 324                                                  <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
 325                                                  <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
 326                                                  <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
 327                                                  <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
 328                                                  <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
 329                                                  <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
 330                                                  <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
 331                                                  <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
 332                                                  <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
 333                                                  <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
 334                                                  <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
 335                                                  <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
 336                                         bias-disable;
 337                                         drive-push-pull;
 338                                         slew-rate = <3>;
 339                                 };
 340                         };
 341
 342                         sdio_pins: sdio_pins@0 {
 343                                 pins {
 344                                         pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
 345                                                  <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
 346                                                  <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
 347                                                  <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
 348                                                  <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
 349                                                  <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
 350                                         drive-push-pull;
 351                                         slew-rate = <2>;
 352                                 };
 353                         };
 354
 355                         sdio_pins_od: sdio_pins_od@0 {
 356                                 pins1 {
 357                                         pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
 358                                                  <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
 359                                                  <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
 360                                                  <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
 361                                                  <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
 362                                         drive-push-pull;
 363                                         slew-rate = <2>;
 364                                 };
 365
 366                                 pins2 {
 367                                         pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
 368                                         drive-open-drain;
 369                                         slew-rate = <2>;
 370                                 };
 371                         };
 372                 };
 373         };
 374 };