arch/arm/boot/dts/stih407-family.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-pinctrl.dtsi"
  10 #include <dt-bindings/mfd/st-lpc.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/reset/stih407-resets.h>
  13 #include <dt-bindings/interrupt-controller/irq-st.h>
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         reserved-memory {
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges;
  22
  23                 gp0_reserved: rproc@40000000 {
  24                         compatible = "shared-dma-pool";
  25                         reg = <0x40000000 0x01000000>;
  26                         no-map;
  27                         status = "disabled";
  28                 };
  29
  30                 gp1_reserved: rproc@41000000 {
  31                         compatible = "shared-dma-pool";
  32                         reg = <0x41000000 0x01000000>;
  33                         no-map;
  34                         status = "disabled";
  35                 };
  36
  37                 audio_reserved: rproc@42000000 {
  38                         compatible = "shared-dma-pool";
  39                         reg = <0x42000000 0x01000000>;
  40                         no-map;
  41                         status = "disabled";
  42                 };
  43
  44                 dmu_reserved: rproc@43000000 {
  45                         compatible = "shared-dma-pool";
  46                         reg = <0x43000000 0x01000000>;
  47                         no-map;
  48                 };
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0>;
  58
  59                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  60                         cpu-release-addr = <0x94100A4>;
  61
  62                                          /* kHz     uV   */
  63                         operating-points = <1500000 0
  64                                             1200000 0
  65                                             800000  0
  66                                             500000  0>;
  67
  68                         clocks = <&clk_m_a9>;
  69                         clock-names = "cpu";
  70                         clock-latency = <100000>;
  71                         cpu0-supply = <&pwm_regulator>;
  72                         st,syscfg = <&syscfg_core 0x8e0>;
  73                 };
  74                 cpu@1 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a9";
  77                         reg = <1>;
  78
  79                         /* u-boot puts hpen in SBC dmem at 0xa4 offset */
  80                         cpu-release-addr = <0x94100A4>;
  81
  82                                          /* kHz     uV   */
  83                         operating-points = <1500000 0
  84                                             1200000 0
  85                                             800000  0
  86                                             500000  0>;
  87                 };
  88         };
  89
  90         intc: interrupt-controller@08761000 {
  91                 compatible = "arm,cortex-a9-gic";
  92                 #interrupt-cells = <3>;
  93                 interrupt-controller;
  94                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
  95         };
  96
  97         scu@08760000 {
  98                 compatible = "arm,cortex-a9-scu";
  99                 reg = <0x08760000 0x1000>;
 100         };
 101
 102         timer@08760200 {
 103                 interrupt-parent = <&intc>;
 104                 compatible = "arm,cortex-a9-global-timer";
 105                 reg = <0x08760200 0x100>;
 106                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
 107                 clocks = <&arm_periph_clk>;
 108         };
 109
 110         l2: cache-controller {
 111                 compatible = "arm,pl310-cache";
 112                 reg = <0x08762000 0x1000>;
 113                 arm,data-latency = <3 3 3>;
 114                 arm,tag-latency = <2 2 2>;
 115                 cache-unified;
 116                 cache-level = <2>;
 117         };
 118
 119         arm-pmu {
 120                 interrupt-parent = <&intc>;
 121                 compatible = "arm,cortex-a9-pmu";
 122                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 123         };
 124
 125         pwm_regulator: pwm-regulator {
 126                 compatible = "pwm-regulator";
 127                 pwms = <&pwm1 3 8448>;
 128                 regulator-name = "CPU_1V0_AVS";
 129                 regulator-min-microvolt = <784000>;
 130                 regulator-max-microvolt = <1299000>;
 131                 regulator-always-on;
 132                 max-duty-cycle = <255>;
 133                 status = "okay";
 134         };
 135
 136         soc {
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 interrupt-parent = <&intc>;
 140                 ranges;
 141                 compatible = "simple-bus";
 142
 143                 restart {
 144                         compatible = "st,stih407-restart";
 145                         st,syscfg = <&syscfg_sbc_reg>;
 146                         status = "okay";
 147                 };
 148
 149                 powerdown: powerdown-controller {
 150                         compatible = "st,stih407-powerdown";
 151                         #reset-cells = <1>;
 152                 };
 153
 154                 softreset: softreset-controller {
 155                         compatible = "st,stih407-softreset";
 156                         #reset-cells = <1>;
 157                 };
 158
 159                 picophyreset: picophyreset-controller {
 160                         compatible = "st,stih407-picophyreset";
 161                         #reset-cells = <1>;
 162                 };
 163
 164                 syscfg_sbc: sbc-syscfg@9620000 {
 165                         compatible = "st,stih407-sbc-syscfg", "syscon";
 166                         reg = <0x9620000 0x1000>;
 167                 };
 168
 169                 syscfg_front: front-syscfg@9280000 {
 170                         compatible = "st,stih407-front-syscfg", "syscon";
 171                         reg = <0x9280000 0x1000>;
 172                 };
 173
 174                 syscfg_rear: rear-syscfg@9290000 {
 175                         compatible = "st,stih407-rear-syscfg", "syscon";
 176                         reg = <0x9290000 0x1000>;
 177                 };
 178
 179                 syscfg_flash: flash-syscfg@92a0000 {
 180                         compatible = "st,stih407-flash-syscfg", "syscon";
 181                         reg = <0x92a0000 0x1000>;
 182                 };
 183
 184                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
 185                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
 186                         reg = <0x9600000 0x1000>;
 187                 };
 188
 189                 syscfg_core: core-syscfg@92b0000 {
 190                         compatible = "st,stih407-core-syscfg", "syscon";
 191                         reg = <0x92b0000 0x1000>;
 192                 };
 193
 194                 syscfg_lpm: lpm-syscfg@94b5100 {
 195                         compatible = "st,stih407-lpm-syscfg", "syscon";
 196                         reg = <0x94b5100 0x1000>;
 197                 };
 198
 199                 irq-syscfg {
 200                         compatible    = "st,stih407-irq-syscfg";
 201                         st,syscfg     = <&syscfg_core>;
 202                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
 203                                         <ST_IRQ_SYSCFG_PMU_1>;
 204                         st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
 205                                         <ST_IRQ_SYSCFG_DISABLED>;
 206                 };
 207
 208                 /* Display */
 209                 vtg_main: sti-vtg-main@8d02800 {
 210                         compatible = "st,vtg";
 211                         reg = <0x8d02800 0x200>;
 212                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
 213                 };
 214
 215                 vtg_aux: sti-vtg-aux@8d00200 {
 216                         compatible = "st,vtg";
 217                         reg = <0x8d00200 0x100>;
 218                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
 219                 };
 220
 221                 serial@9830000 {
 222                         compatible = "st,asc";
 223                         reg = <0x9830000 0x2c>;
 224                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
 225                         pinctrl-names = "default";
 226                         pinctrl-0 = <&pinctrl_serial0>;
 227                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 228
 229                         status = "disabled";
 230                 };
 231
 232                 serial@9831000 {
 233                         compatible = "st,asc";
 234                         reg = <0x9831000 0x2c>;
 235                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
 236                         pinctrl-names = "default";
 237                         pinctrl-0 = <&pinctrl_serial1>;
 238                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 239
 240                         status = "disabled";
 241                 };
 242
 243                 serial@9832000 {
 244                         compatible = "st,asc";
 245                         reg = <0x9832000 0x2c>;
 246                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 247                         pinctrl-names = "default";
 248                         pinctrl-0 = <&pinctrl_serial2>;
 249                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 250
 251                         status = "disabled";
 252                 };
 253
 254                 /* SBC_ASC0 - UART10 */
 255                 sbc_serial0: serial@9530000 {
 256                         compatible = "st,asc";
 257                         reg = <0x9530000 0x2c>;
 258                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
 259                         pinctrl-names = "default";
 260                         pinctrl-0 = <&pinctrl_sbc_serial0>;
 261                         clocks = <&clk_sysin>;
 262
 263                         status = "disabled";
 264                 };
 265
 266                 serial@9531000 {
 267                         compatible = "st,asc";
 268                         reg = <0x9531000 0x2c>;
 269                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
 270                         pinctrl-names = "default";
 271                         pinctrl-0 = <&pinctrl_sbc_serial1>;
 272                         clocks = <&clk_sysin>;
 273
 274                         status = "disabled";
 275                 };
 276
 277                 i2c@9840000 {
 278                         compatible = "st,comms-ssc4-i2c";
 279                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 280                         reg = <0x9840000 0x110>;
 281                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 282                         clock-names = "ssc";
 283                         clock-frequency = <400000>;
 284                         pinctrl-names = "default";
 285                         pinctrl-0 = <&pinctrl_i2c0_default>;
 286
 287                         status = "disabled";
 288                 };
 289
 290                 i2c@9841000 {
 291                         compatible = "st,comms-ssc4-i2c";
 292                         reg = <0x9841000 0x110>;
 293                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 295                         clock-names = "ssc";
 296                         clock-frequency = <400000>;
 297                         pinctrl-names = "default";
 298                         pinctrl-0 = <&pinctrl_i2c1_default>;
 299
 300                         status = "disabled";
 301                 };
 302
 303                 i2c@9842000 {
 304                         compatible = "st,comms-ssc4-i2c";
 305                         reg = <0x9842000 0x110>;
 306                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 308                         clock-names = "ssc";
 309                         clock-frequency = <400000>;
 310                         pinctrl-names = "default";
 311                         pinctrl-0 = <&pinctrl_i2c2_default>;
 312
 313                         status = "disabled";
 314                 };
 315
 316                 i2c@9843000 {
 317                         compatible = "st,comms-ssc4-i2c";
 318                         reg = <0x9843000 0x110>;
 319                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 320                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 321                         clock-names = "ssc";
 322                         clock-frequency = <400000>;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&pinctrl_i2c3_default>;
 325
 326                         status = "disabled";
 327                 };
 328
 329                 i2c@9844000 {
 330                         compatible = "st,comms-ssc4-i2c";
 331                         reg = <0x9844000 0x110>;
 332                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 334                         clock-names = "ssc";
 335                         clock-frequency = <400000>;
 336                         pinctrl-names = "default";
 337                         pinctrl-0 = <&pinctrl_i2c4_default>;
 338
 339                         status = "disabled";
 340                 };
 341
 342                 i2c@9845000 {
 343                         compatible = "st,comms-ssc4-i2c";
 344                         reg = <0x9845000 0x110>;
 345                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 347                         clock-names = "ssc";
 348                         clock-frequency = <400000>;
 349                         pinctrl-names = "default";
 350                         pinctrl-0 = <&pinctrl_i2c5_default>;
 351
 352                         status = "disabled";
 353                 };
 354
 355
 356                 /* SSCs on SBC */
 357                 i2c@9540000 {
 358                         compatible = "st,comms-ssc4-i2c";
 359                         reg = <0x9540000 0x110>;
 360                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 361                         clocks = <&clk_sysin>;
 362                         clock-names = "ssc";
 363                         clock-frequency = <400000>;
 364                         pinctrl-names = "default";
 365                         pinctrl-0 = <&pinctrl_i2c10_default>;
 366
 367                         status = "disabled";
 368                 };
 369
 370                 i2c@9541000 {
 371                         compatible = "st,comms-ssc4-i2c";
 372                         reg = <0x9541000 0x110>;
 373                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&clk_sysin>;
 375                         clock-names = "ssc";
 376                         clock-frequency = <400000>;
 377                         pinctrl-names = "default";
 378                         pinctrl-0 = <&pinctrl_i2c11_default>;
 379
 380                         status = "disabled";
 381                 };
 382
 383                 usb2_picophy0: phy1 {
 384                         compatible = "st,stih407-usb2-phy";
 385                         #phy-cells = <0>;
 386                         st,syscfg = <&syscfg_core 0x100 0xf4>;
 387                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 388                                  <&picophyreset STIH407_PICOPHY2_RESET>;
 389                         reset-names = "global", "port";
 390                 };
 391
 392                 miphy28lp_phy: miphy28lp@9b22000 {
 393                         compatible = "st,miphy28lp-phy";
 394                         st,syscfg = <&syscfg_core>;
 395                         #address-cells  = <1>;
 396                         #size-cells     = <1>;
 397                         ranges;
 398
 399                         phy_port0: port@9b22000 {
 400                                 reg = <0x9b22000 0xff>,
 401                                       <0x9b09000 0xff>,
 402                                       <0x9b04000 0xff>;
 403                                 reg-names = "sata-up",
 404                                             "pcie-up",
 405                                             "pipew";
 406
 407                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 408                                 #phy-cells = <1>;
 409
 410                                 reset-names = "miphy-sw-rst";
 411                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 412                         };
 413
 414                         phy_port1: port@9b2a000 {
 415                                 reg = <0x9b2a000 0xff>,
 416                                       <0x9b19000 0xff>,
 417                                       <0x9b14000 0xff>;
 418                                 reg-names = "sata-up",
 419                                             "pcie-up",
 420                                             "pipew";
 421
 422                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 423
 424                                 #phy-cells = <1>;
 425
 426                                 reset-names = "miphy-sw-rst";
 427                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 428                         };
 429
 430                         phy_port2: port@8f95000 {
 431                                 reg = <0x8f95000 0xff>,
 432                                       <0x8f90000 0xff>;
 433                                 reg-names = "pipew",
 434                                             "usb3-up";
 435
 436                                 st,syscfg = <0x11c 0x820>;
 437
 438                                 #phy-cells = <1>;
 439
 440                                 reset-names = "miphy-sw-rst";
 441                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 442                         };
 443                 };
 444
 445                 spi@9840000 {
 446                         compatible = "st,comms-ssc4-spi";
 447                         reg = <0x9840000 0x110>;
 448                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 450                         clock-names = "ssc";
 451                         pinctrl-0 = <&pinctrl_spi0_default>;
 452                         pinctrl-names = "default";
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455
 456                         status = "disabled";
 457                 };
 458
 459                 spi@9841000 {
 460                         compatible = "st,comms-ssc4-spi";
 461                         reg = <0x9841000 0x110>;
 462                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 464                         clock-names = "ssc";
 465                         pinctrl-names = "default";
 466                         pinctrl-0 = <&pinctrl_spi1_default>;
 467
 468                         status = "disabled";
 469                 };
 470
 471                 spi@9842000 {
 472                         compatible = "st,comms-ssc4-spi";
 473                         reg = <0x9842000 0x110>;
 474                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 475                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 476                         clock-names = "ssc";
 477                         pinctrl-names = "default";
 478                         pinctrl-0 = <&pinctrl_spi2_default>;
 479
 480                         status = "disabled";
 481                 };
 482
 483                 spi@9843000 {
 484                         compatible = "st,comms-ssc4-spi";
 485                         reg = <0x9843000 0x110>;
 486                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 488                         clock-names = "ssc";
 489                         pinctrl-names = "default";
 490                         pinctrl-0 = <&pinctrl_spi3_default>;
 491
 492                         status = "disabled";
 493                 };
 494
 495                 spi@9844000 {
 496                         compatible = "st,comms-ssc4-spi";
 497                         reg = <0x9844000 0x110>;
 498                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 500                         clock-names = "ssc";
 501                         pinctrl-names = "default";
 502                         pinctrl-0 = <&pinctrl_spi4_default>;
 503
 504                         status = "disabled";
 505                 };
 506
 507                 /* SBC SSC */
 508                 spi@9540000 {
 509                         compatible = "st,comms-ssc4-spi";
 510                         reg = <0x9540000 0x110>;
 511                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&clk_sysin>;
 513                         clock-names = "ssc";
 514                         pinctrl-names = "default";
 515                         pinctrl-0 = <&pinctrl_spi10_default>;
 516
 517                         status = "disabled";
 518                 };
 519
 520                 spi@9541000 {
 521                         compatible = "st,comms-ssc4-spi";
 522                         reg = <0x9541000 0x110>;
 523                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&clk_sysin>;
 525                         clock-names = "ssc";
 526                         pinctrl-names = "default";
 527                         pinctrl-0 = <&pinctrl_spi11_default>;
 528
 529                         status = "disabled";
 530                 };
 531
 532                 spi@9542000 {
 533                         compatible = "st,comms-ssc4-spi";
 534                         reg = <0x9542000 0x110>;
 535                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&clk_sysin>;
 537                         clock-names = "ssc";
 538                         pinctrl-names = "default";
 539                         pinctrl-0 = <&pinctrl_spi12_default>;
 540
 541                         status = "disabled";
 542                 };
 543
 544                 mmc0: sdhci@09060000 {
 545                         compatible = "st,sdhci-stih407", "st,sdhci";
 546                         status = "disabled";
 547                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
 548                         reg-names = "mmc", "top-mmc-delay";
 549                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
 550                         interrupt-names = "mmcirq";
 551                         pinctrl-names = "default";
 552                         pinctrl-0 = <&pinctrl_mmc0>;
 553                         clock-names = "mmc";
 554                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
 555                         bus-width = <8>;
 556                         non-removable;
 557                 };
 558
 559                 mmc1: sdhci@09080000 {
 560                         compatible = "st,sdhci-stih407", "st,sdhci";
 561                         status = "disabled";
 562                         reg = <0x09080000 0x7ff>;
 563                         reg-names = "mmc";
 564                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
 565                         interrupt-names = "mmcirq";
 566                         pinctrl-names = "default";
 567                         pinctrl-0 = <&pinctrl_sd1>;
 568                         clock-names = "mmc";
 569                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
 570                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
 571                         bus-width = <4>;
 572                 };
 573
 574                 /* Watchdog and Real-Time Clock */
 575                 lpc@8787000 {
 576                         compatible = "st,stih407-lpc";
 577                         reg = <0x8787000 0x1000>;
 578                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
 579                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
 580                         timeout-sec = <120>;
 581                         st,syscfg = <&syscfg_core>;
 582                         st,lpc-mode = <ST_LPC_MODE_WDT>;
 583                 };
 584
 585                 lpc@8788000 {
 586                         compatible = "st,stih407-lpc";
 587                         reg = <0x8788000 0x1000>;
 588                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 589                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
 590                         st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
 591                 };
 592
 593                 sata0: sata@9b20000 {
 594                         compatible = "st,ahci";
 595                         reg = <0x9b20000 0x1000>;
 596
 597                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 598                         interrupt-names = "hostc";
 599
 600                         phys = <&phy_port0 PHY_TYPE_SATA>;
 601                         phy-names = "ahci_phy";
 602
 603                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
 604                                  <&softreset STIH407_SATA0_SOFTRESET>,
 605                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
 606                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
 607
 608                         clock-names = "ahci_clk";
 609                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 610
 611                         status = "disabled";
 612                 };
 613
 614                 sata1: sata@9b28000 {
 615                         compatible = "st,ahci";
 616                         reg = <0x9b28000 0x1000>;
 617
 618                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 619                         interrupt-names = "hostc";
 620
 621                         phys = <&phy_port1 PHY_TYPE_SATA>;
 622                         phy-names = "ahci_phy";
 623
 624                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
 625                                  <&softreset STIH407_SATA1_SOFTRESET>,
 626                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
 627                         reset-names = "pwr-dwn",
 628                                       "sw-rst",
 629                                       "pwr-rst";
 630
 631                         clock-names = "ahci_clk";
 632                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 633
 634                         status = "disabled";
 635                 };
 636
 637
 638                 st_dwc3: dwc3@8f94000 {
 639                         compatible      = "st,stih407-dwc3";
 640                         reg             = <0x08f94000 0x1000>, <0x110 0x4>;
 641                         reg-names       = "reg-glue", "syscfg-reg";
 642                         st,syscfg       = <&syscfg_core>;
 643                         resets          = <&powerdown STIH407_USB3_POWERDOWN>,
 644                                           <&softreset STIH407_MIPHY2_SOFTRESET>;
 645                         reset-names     = "powerdown", "softreset";
 646                         #address-cells  = <1>;
 647                         #size-cells     = <1>;
 648                         pinctrl-names   = "default";
 649                         pinctrl-0       = <&pinctrl_usb3>;
 650                         ranges;
 651
 652                         status = "disabled";
 653
 654                         dwc3: dwc3@9900000 {
 655                                 compatible      = "snps,dwc3";
 656                                 reg             = <0x09900000 0x100000>;
 657                                 interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
 658                                 dr_mode         = "host";
 659                                 phy-names       = "usb2-phy", "usb3-phy";
 660                                 phys            = <&usb2_picophy0>,
 661                                                   <&phy_port2 PHY_TYPE_USB3>;
 662                         };
 663                 };
 664
 665                 /* COMMS PWM Module */
 666                 pwm0: pwm@9810000 {
 667                         compatible      = "st,sti-pwm";
 668                         #pwm-cells      = <2>;
 669                         reg             = <0x9810000 0x68>;
 670                         pinctrl-names   = "default";
 671                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
 672                         clock-names     = "pwm";
 673                         clocks          = <&clk_sysin>;
 674                         st,pwm-num-chan = <1>;
 675
 676                         status          = "disabled";
 677                 };
 678
 679                 /* SBC PWM Module */
 680                 pwm1: pwm@9510000 {
 681                         compatible      = "st,sti-pwm";
 682                         #pwm-cells      = <2>;
 683                         reg             = <0x9510000 0x68>;
 684                         pinctrl-names   = "default";
 685                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
 686                                         &pinctrl_pwm1_chan1_default
 687                                         &pinctrl_pwm1_chan2_default
 688                                         &pinctrl_pwm1_chan3_default>;
 689                         clock-names     = "pwm";
 690                         clocks          = <&clk_sysin>;
 691                         st,pwm-num-chan = <4>;
 692
 693                         status          = "disabled";
 694                 };
 695
 696                 rng10: rng@08a89000 {
 697                         compatible      = "st,rng";
 698                         reg             = <0x08a89000 0x1000>;
 699                         clocks          = <&clk_sysin>;
 700                         status          = "okay";
 701                 };
 702
 703                 rng11: rng@08a8a000 {
 704                         compatible      = "st,rng";
 705                         reg             = <0x08a8a000 0x1000>;
 706                         clocks          = <&clk_sysin>;
 707                         status          = "okay";
 708                 };
 709
 710                 ethernet0: dwmac@9630000 {
 711                         device_type = "network";
 712                         status = "disabled";
 713                         compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 714                         reg = <0x9630000 0x8000>, <0x80 0x4>;
 715                         reg-names = "stmmaceth", "sti-ethconf";
 716
 717                         st,syscon = <&syscfg_sbc_reg 0x80>;
 718                         st,gmac_en;
 719                         resets = <&softreset STIH407_ETH1_SOFTRESET>;
 720                         reset-names = "stmmaceth";
 721
 722                         interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
 723                                      <GIC_SPI 99 IRQ_TYPE_NONE>;
 724                         interrupt-names = "macirq", "eth_wake_irq";
 725
 726                         /* DMA Bus Mode */
 727                         snps,pbl = <8>;
 728
 729                         pinctrl-names = "default";
 730                         pinctrl-0 = <&pinctrl_rgmii1>;
 731
 732                         clock-names = "stmmaceth", "sti-ethclk";
 733                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
 734                                  <&clk_s_c0_flexgen CLK_ETH_PHY>;
 735                 };
 736
 737                 rng10: rng@08a89000 {
 738                         compatible      = "st,rng";
 739                         reg             = <0x08a89000 0x1000>;
 740                         clocks          = <&clk_sysin>;
 741                         status          = "okay";
 742                 };
 743
 744                 rng11: rng@08a8a000 {
 745                         compatible      = "st,rng";
 746                         reg             = <0x08a8a000 0x1000>;
 747                         clocks          = <&clk_sysin>;
 748                         status          = "okay";
 749                 };
 750
 751                 mailbox0: mailbox@8f00000  {
 752                         compatible      = "st,stih407-mailbox";
 753                         reg             = <0x8f00000 0x1000>;
 754                         interrupts      = <GIC_SPI 1 IRQ_TYPE_NONE>;
 755                         #mbox-cells     = <2>;
 756                         mbox-name       = "a9";
 757                         status          = "okay";
 758                 };
 759
 760                 mailbox1: mailbox@8f01000 {
 761                         compatible      = "st,stih407-mailbox";
 762                         reg             = <0x8f01000 0x1000>;
 763                         #mbox-cells     = <2>;
 764                         mbox-name       = "st231_gp_1";
 765                         status          = "okay";
 766                 };
 767
 768                 mailbox2: mailbox@8f02000 {
 769                         compatible      = "st,stih407-mailbox";
 770                         reg             = <0x8f02000 0x1000>;
 771                         #mbox-cells     = <2>;
 772                         mbox-name       = "st231_gp_0";
 773                         status          = "okay";
 774                 };
 775
 776                 mailbox3: mailbox@8f03000 {
 777                         compatible      = "st,stih407-mailbox";
 778                         reg             = <0x8f03000 0x1000>;
 779                         #mbox-cells     = <2>;
 780                         mbox-name       = "st231_audio_video";
 781                         status          = "okay";
 782                 };
 783
 784                 st231_gp0: remote-processor {
 785                         compatible      = "st,st231-rproc";
 786                         memory-region   = <&gp0_reserved>;
 787                         resets          = <&softreset STIH407_ST231_GP0_SOFTRESET>;
 788                         reset-names     = "sw_reset";
 789                         clocks          = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
 790                         clock-frequency = <600000000>;
 791                         st,syscfg       = <&syscfg_core 0x22c>;
 792                 };
 793
 794
 795                 st231_gp1: remote-processor {
 796                         compatible      = "st,st231-rproc";
 797                         memory-region   = <&gp1_reserved>;
 798                         resets          = <&softreset STIH407_ST231_GP1_SOFTRESET>;
 799                         reset-names     = "sw_reset";
 800                         clocks          = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
 801                         clock-frequency = <600000000>;
 802                         st,syscfg       = <&syscfg_core 0x220>;
 803                 };
 804
 805                 st231_audio: remote-processor {
 806                         compatible      = "st,st231-rproc";
 807                         memory-region   = <&audio_reserved>;
 808                         resets          = <&softreset STIH407_ST231_AUD_SOFTRESET>;
 809                         reset-names     = "sw_reset";
 810                         clocks          = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
 811                         clock-frequency = <600000000>;
 812                         st,syscfg       = <&syscfg_core 0x228>;
 813                 };
 814
 815                 st231_dmu: remote-processor {
 816                         compatible      = "st,st231-rproc";
 817                         memory-region   = <&dmu_reserved>;
 818                         resets          = <&softreset STIH407_ST231_DMU_SOFTRESET>;
 819                         reset-names     = "sw_reset";
 820                         clocks          = <&clk_s_c0_flexgen CLK_ST231_DMU>;
 821                         clock-frequency = <600000000>;
 822                         st,syscfg       = <&syscfg_core 0x224>;
 823                 };
 824         };
 825 };