arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/mfd/dbx500-prcmu.h>
  15 #include <dt-bindings/arm/ux500_pm_domains.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/clock/ste-ab8500.h>
  18
  19 / {
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         chosen {
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 enable-method = "ste,dbx500-smp";
  30
  31                 cpu-map {
  32                         cluster0 {
  33                                 core0 {
  34                                         cpu = <&CPU0>;
  35                                 };
  36                                 core1 {
  37                                         cpu = <&CPU1>;
  38                                 };
  39                         };
  40                 };
  41                 CPU0: cpu@300 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <0x300>;
  45                         /* cpufreq controls */
  46                         operating-points = <998400 0
  47                                             800000 0
  48                                             400000 0
  49                                             200000 0>;
  50                         clocks = <&prcmu_clk PRCMU_ARMSS>;
  51                         clock-names = "cpu";
  52                         clock-latency = <20000>;
  53                 };
  54                 CPU1: cpu@301 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0x301>;
  58                 };
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "stericsson,db8500";
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 ptm@801ae000 {
  69                         compatible = "arm,coresight-etm3x", "arm,primecell";
  70                         reg = <0x801ae000 0x1000>;
  71
  72                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  73                         clock-names = "apb_pclk", "atclk";
  74                         cpu = <&CPU0>;
  75                         out-ports {
  76                                 port {
  77                                         ptm0_out_port: endpoint {
  78                                                 remote-endpoint = <&funnel_in_port0>;
  79                                         };
  80                                 };
  81                         };
  82                 };
  83
  84                 ptm@801af000 {
  85                         compatible = "arm,coresight-etm3x", "arm,primecell";
  86                         reg = <0x801af000 0x1000>;
  87
  88                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  89                         clock-names = "apb_pclk", "atclk";
  90                         cpu = <&CPU1>;
  91                         out-ports {
  92                                 port {
  93                                         ptm1_out_port: endpoint {
  94                                                 remote-endpoint = <&funnel_in_port1>;
  95                                         };
  96                                 };
  97                         };
  98                 };
  99
 100                 funnel@801a6000 {
 101                         compatible = "arm,coresight-funnel", "arm,primecell";
 102                         reg = <0x801a6000 0x1000>;
 103
 104                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 105                         clock-names = "apb_pclk", "atclk";
 106                         out-ports {
 107                                 port {
 108                                         funnel_out_port: endpoint {
 109                                                 remote-endpoint =
 110                                                         <&replicator_in_port0>;
 111                                         };
 112                                 };
 113                         };
 114
 115                         in-ports {
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118
 119                                 port@0 {
 120                                         reg = <0>;
 121                                         funnel_in_port0: endpoint {
 122                                                 remote-endpoint = <&ptm0_out_port>;
 123                                         };
 124                                 };
 125
 126                                 port@1 {
 127                                         reg = <1>;
 128                                         funnel_in_port1: endpoint {
 129                                                 remote-endpoint = <&ptm1_out_port>;
 130                                         };
 131                                 };
 132                         };
 133                 };
 134
 135                 replicator {
 136                         compatible = "arm,coresight-replicator";
 137                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 138                         clock-names = "atclk";
 139
 140                         out-ports {
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143
 144                                 port@0 {
 145                                         reg = <0>;
 146                                         replicator_out_port0: endpoint {
 147                                                 remote-endpoint = <&tpiu_in_port>;
 148                                         };
 149                                 };
 150                                 port@1 {
 151                                         reg = <1>;
 152                                         replicator_out_port1: endpoint {
 153                                                 remote-endpoint = <&etb_in_port>;
 154                                         };
 155                                 };
 156                         };
 157
 158                         in-ports {
 159                                 port {
 160                                         replicator_in_port0: endpoint {
 161                                                 remote-endpoint = <&funnel_out_port>;
 162                                         };
 163                                 };
 164                         };
 165                 };
 166
 167                 tpiu@80190000 {
 168                         compatible = "arm,coresight-tpiu", "arm,primecell";
 169                         reg = <0x80190000 0x1000>;
 170
 171                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 172                         clock-names = "apb_pclk", "atclk";
 173                         in-ports {
 174                                 port {
 175                                         tpiu_in_port: endpoint {
 176                                                 remote-endpoint = <&replicator_out_port0>;
 177                                         };
 178                                 };
 179                         };
 180                 };
 181
 182                 etb@801a4000 {
 183                         compatible = "arm,coresight-etb10", "arm,primecell";
 184                         reg = <0x801a4000 0x1000>;
 185
 186                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 187                         clock-names = "apb_pclk", "atclk";
 188                         in-ports {
 189                                 port {
 190                                         etb_in_port: endpoint {
 191                                                 remote-endpoint = <&replicator_out_port1>;
 192                                         };
 193                                 };
 194                         };
 195                 };
 196
 197                 intc: interrupt-controller@a0411000 {
 198                         compatible = "arm,cortex-a9-gic";
 199                         #interrupt-cells = <3>;
 200                         #address-cells = <1>;
 201                         interrupt-controller;
 202                         reg = <0xa0411000 0x1000>,
 203                               <0xa0410100 0x100>;
 204                 };
 205
 206                 scu@a0410000 {
 207                         compatible = "arm,cortex-a9-scu";
 208                         reg = <0xa0410000 0x100>;
 209                 };
 210
 211                 /*
 212                  * The backup RAM is used for retention during sleep
 213                  * and various things like spin tables
 214                  */
 215                 backupram@80150000 {
 216                         compatible = "ste,dbx500-backupram";
 217                         reg = <0x80150000 0x2000>;
 218                 };
 219
 220                 L2: l2-cache {
 221                         compatible = "arm,pl310-cache";
 222                         reg = <0xa0412000 0x1000>;
 223                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 224                         cache-unified;
 225                         cache-level = <2>;
 226                 };
 227
 228                 pmu {
 229                         compatible = "arm,cortex-a9-pmu";
 230                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 231                 };
 232
 233                 pm_domains: pm_domains0 {
 234                         compatible = "stericsson,ux500-pm-domains";
 235                         #power-domain-cells = <1>;
 236                 };
 237
 238                 clocks {
 239                         compatible = "stericsson,u8500-clks";
 240                         /*
 241                          * Registers for the CLKRST block on peripheral
 242                          * groups 1, 2, 3, 5, 6,
 243                          */
 244                         reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 245                             <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 246                             <0xa03cf000 0x1000>;
 247
 248                         prcmu_clk: prcmu-clock {
 249                                 #clock-cells = <1>;
 250                         };
 251
 252                         prcc_pclk: prcc-periph-clock {
 253                                 #clock-cells = <2>;
 254                         };
 255
 256                         prcc_kclk: prcc-kernel-clock {
 257                                 #clock-cells = <2>;
 258                         };
 259
 260                         rtc_clk: rtc32k-clock {
 261                                 #clock-cells = <0>;
 262                         };
 263
 264                         smp_twd_clk: smp-twd-clock {
 265                                 #clock-cells = <0>;
 266                         };
 267                 };
 268
 269                 mtu@a03c6000 {
 270                         /* Nomadik System Timer */
 271                         compatible = "st,nomadik-mtu";
 272                         reg = <0xa03c6000 0x1000>;
 273                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 274
 275                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 276                         clock-names = "timclk", "apb_pclk";
 277                 };
 278
 279                 timer@a0410600 {
 280                         compatible = "arm,cortex-a9-twd-timer";
 281                         reg = <0xa0410600 0x20>;
 282                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 283
 284                         clocks = <&smp_twd_clk>;
 285                 };
 286
 287                 watchdog@a0410620 {
 288                         compatible = "arm,cortex-a9-twd-wdt";
 289                         reg = <0xa0410620 0x20>;
 290                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 291                         clocks = <&smp_twd_clk>;
 292                 };
 293
 294                 rtc@80154000 {
 295                         compatible = "arm,rtc-pl031", "arm,primecell";
 296                         reg = <0x80154000 0x1000>;
 297                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 298
 299                         clocks = <&rtc_clk>;
 300                         clock-names = "apb_pclk";
 301                 };
 302
 303                 gpio0: gpio@8012e000 {
 304                         compatible = "stericsson,db8500-gpio",
 305                                 "st,nomadik-gpio";
 306                         reg =  <0x8012e000 0x80>;
 307                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                         st,supports-sleepmode;
 311                         gpio-controller;
 312                         #gpio-cells = <2>;
 313                         gpio-bank = <0>;
 314                         gpio-ranges = <&pinctrl 0 0 32>;
 315                         clocks = <&prcc_pclk 1 9>;
 316                 };
 317
 318                 gpio1: gpio@8012e080 {
 319                         compatible = "stericsson,db8500-gpio",
 320                                 "st,nomadik-gpio";
 321                         reg =  <0x8012e080 0x80>;
 322                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                         st,supports-sleepmode;
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                         gpio-bank = <1>;
 329                         gpio-ranges = <&pinctrl 0 32 5>;
 330                         clocks = <&prcc_pclk 1 9>;
 331                 };
 332
 333                 gpio2: gpio@8000e000 {
 334                         compatible = "stericsson,db8500-gpio",
 335                                 "st,nomadik-gpio";
 336                         reg =  <0x8000e000 0x80>;
 337                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                         st,supports-sleepmode;
 341                         gpio-controller;
 342                         #gpio-cells = <2>;
 343                         gpio-bank = <2>;
 344                         gpio-ranges = <&pinctrl 0 64 32>;
 345                         clocks = <&prcc_pclk 3 8>;
 346                 };
 347
 348                 gpio3: gpio@8000e080 {
 349                         compatible = "stericsson,db8500-gpio",
 350                                 "st,nomadik-gpio";
 351                         reg =  <0x8000e080 0x80>;
 352                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                         st,supports-sleepmode;
 356                         gpio-controller;
 357                         #gpio-cells = <2>;
 358                         gpio-bank = <3>;
 359                         gpio-ranges = <&pinctrl 0 96 2>;
 360                         clocks = <&prcc_pclk 3 8>;
 361                 };
 362
 363                 gpio4: gpio@8000e100 {
 364                         compatible = "stericsson,db8500-gpio",
 365                                 "st,nomadik-gpio";
 366                         reg =  <0x8000e100 0x80>;
 367                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 368                         interrupt-controller;
 369                         #interrupt-cells = <2>;
 370                         st,supports-sleepmode;
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                         gpio-bank = <4>;
 374                         gpio-ranges = <&pinctrl 0 128 32>;
 375                         clocks = <&prcc_pclk 3 8>;
 376                 };
 377
 378                 gpio5: gpio@8000e180 {
 379                         compatible = "stericsson,db8500-gpio",
 380                                 "st,nomadik-gpio";
 381                         reg =  <0x8000e180 0x80>;
 382                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 383                         interrupt-controller;
 384                         #interrupt-cells = <2>;
 385                         st,supports-sleepmode;
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         gpio-bank = <5>;
 389                         gpio-ranges = <&pinctrl 0 160 12>;
 390                         clocks = <&prcc_pclk 3 8>;
 391                 };
 392
 393                 gpio6: gpio@8011e000 {
 394                         compatible = "stericsson,db8500-gpio",
 395                                 "st,nomadik-gpio";
 396                         reg =  <0x8011e000 0x80>;
 397                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 398                         interrupt-controller;
 399                         #interrupt-cells = <2>;
 400                         st,supports-sleepmode;
 401                         gpio-controller;
 402                         #gpio-cells = <2>;
 403                         gpio-bank = <6>;
 404                         gpio-ranges = <&pinctrl 0 192 32>;
 405                         clocks = <&prcc_pclk 2 11>;
 406                 };
 407
 408                 gpio7: gpio@8011e080 {
 409                         compatible = "stericsson,db8500-gpio",
 410                                 "st,nomadik-gpio";
 411                         reg =  <0x8011e080 0x80>;
 412                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 413                         interrupt-controller;
 414                         #interrupt-cells = <2>;
 415                         st,supports-sleepmode;
 416                         gpio-controller;
 417                         #gpio-cells = <2>;
 418                         gpio-bank = <7>;
 419                         gpio-ranges = <&pinctrl 0 224 7>;
 420                         clocks = <&prcc_pclk 2 11>;
 421                 };
 422
 423                 gpio8: gpio@a03fe000 {
 424                         compatible = "stericsson,db8500-gpio",
 425                                 "st,nomadik-gpio";
 426                         reg =  <0xa03fe000 0x80>;
 427                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                         st,supports-sleepmode;
 431                         gpio-controller;
 432                         #gpio-cells = <2>;
 433                         gpio-bank = <8>;
 434                         gpio-ranges = <&pinctrl 0 256 12>;
 435                         clocks = <&prcc_pclk 5 1>;
 436                 };
 437
 438                 pinctrl: pinctrl {
 439                         compatible = "stericsson,db8500-pinctrl";
 440                         nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
 441                                                 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
 442                                                 <&gpio8>;
 443                         prcm = <&prcmu>;
 444                 };
 445
 446                 usb_per5@a03e0000 {
 447                         compatible = "stericsson,db8500-musb";
 448                         reg = <0xa03e0000 0x10000>;
 449                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 450                         interrupt-names = "mc";
 451
 452                         dr_mode = "otg";
 453
 454                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 455                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 456                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 457                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 458                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 459                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 460                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 461                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 462                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 463                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 464                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 465                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 466                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 467                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 468                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 469                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 470
 471                         dma-names = "iep_1_9",  "oep_1_9",
 472                                     "iep_2_10", "oep_2_10",
 473                                     "iep_3_11", "oep_3_11",
 474                                     "iep_4_12", "oep_4_12",
 475                                     "iep_5_13", "oep_5_13",
 476                                     "iep_6_14", "oep_6_14",
 477                                     "iep_7_15", "oep_7_15",
 478                                     "iep_8",    "oep_8";
 479
 480                         clocks = <&prcc_pclk 5 0>;
 481                 };
 482
 483                 dma: dma-controller@801C0000 {
 484                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 485                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 486                         reg-names = "base", "lcpa";
 487                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 488
 489                         #dma-cells = <3>;
 490                         memcpy-channels = <56 57 58 59 60>;
 491
 492                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 493                 };
 494
 495                 prcmu: prcmu@80157000 {
 496                         compatible = "stericsson,db8500-prcmu", "syscon";
 497                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 498                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 499                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 500                         #address-cells = <1>;
 501                         #size-cells = <1>;
 502                         interrupt-controller;
 503                         #interrupt-cells = <2>;
 504                         ranges;
 505
 506                         prcmu-timer-4@80157450 {
 507                                 compatible = "stericsson,db8500-prcmu-timer-4";
 508                                 reg = <0x80157450 0xC>;
 509                         };
 510
 511                         thermal@801573c0 {
 512                                 compatible = "stericsson,db8500-thermal";
 513                                 reg = <0x801573c0 0x40>;
 514                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 515                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 516                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 517                                 status = "disabled";
 518                         };
 519
 520                         db8500-prcmu-regulators {
 521                                 compatible = "stericsson,db8500-prcmu-regulator";
 522
 523                                 // DB8500_REGULATOR_VAPE
 524                                 db8500_vape_reg: db8500_vape {
 525                                         regulator-always-on;
 526                                 };
 527
 528                                 // DB8500_REGULATOR_VARM
 529                                 db8500_varm_reg: db8500_varm {
 530                                 };
 531
 532                                 // DB8500_REGULATOR_VMODEM
 533                                 db8500_vmodem_reg: db8500_vmodem {
 534                                 };
 535
 536                                 // DB8500_REGULATOR_VPLL
 537                                 db8500_vpll_reg: db8500_vpll {
 538                                 };
 539
 540                                 // DB8500_REGULATOR_VSMPS1
 541                                 db8500_vsmps1_reg: db8500_vsmps1 {
 542                                 };
 543
 544                                 // DB8500_REGULATOR_VSMPS2
 545                                 db8500_vsmps2_reg: db8500_vsmps2 {
 546                                 };
 547
 548                                 // DB8500_REGULATOR_VSMPS3
 549                                 db8500_vsmps3_reg: db8500_vsmps3 {
 550                                 };
 551
 552                                 // DB8500_REGULATOR_VRF1
 553                                 db8500_vrf1_reg: db8500_vrf1 {
 554                                 };
 555
 556                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 557                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 558                                 };
 559
 560                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 561                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 562                                 };
 563
 564                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 565                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 566                                 };
 567
 568                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 569                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 570                                 };
 571
 572                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 573                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 574                                 };
 575
 576                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 577                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 578                                 };
 579
 580                                 // DB8500_REGULATOR_SWITCH_SGA
 581                                 db8500_sga_reg: db8500_sga {
 582                                         vin-supply = <&db8500_vape_reg>;
 583                                 };
 584
 585                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 586                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 587                                         vin-supply = <&db8500_vape_reg>;
 588                                 };
 589
 590                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 591                                 db8500_esram12_reg: db8500_esram12 {
 592                                 };
 593
 594                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 595                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 596                                 };
 597
 598                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 599                                 db8500_esram34_reg: db8500_esram34 {
 600                                 };
 601
 602                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 603                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 604                                 };
 605                         };
 606
 607                         ab8500 {
 608                                 compatible = "stericsson,ab8500";
 609                                 interrupt-parent = <&intc>;
 610                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 611                                 interrupt-controller;
 612                                 #interrupt-cells = <2>;
 613
 614                                 ab8500_clock: clock-controller {
 615                                         compatible = "stericsson,ab8500-clk";
 616                                         #clock-cells = <1>;
 617                                 };
 618
 619                                 ab8500_gpio: ab8500-gpio {
 620                                         compatible = "stericsson,ab8500-gpio";
 621                                         gpio-controller;
 622                                         #gpio-cells = <2>;
 623                                 };
 624
 625                                 ab8500-rtc {
 626                                         compatible = "stericsson,ab8500-rtc";
 627                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 628                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 629                                         interrupt-names = "60S", "ALARM";
 630                                 };
 631
 632                                 ab8500-gpadc {
 633                                         compatible = "stericsson,ab8500-gpadc";
 634                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 635                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 636                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 637                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 638                                 };
 639
 640                                 ab8500_battery: ab8500_battery {
 641                                         stericsson,battery-type = "LIPO";
 642                                         thermistor-on-batctrl;
 643                                 };
 644
 645                                 ab8500_fg {
 646                                         compatible = "stericsson,ab8500-fg";
 647                                         battery    = <&ab8500_battery>;
 648                                 };
 649
 650                                 ab8500_btemp {
 651                                         compatible = "stericsson,ab8500-btemp";
 652                                         battery    = <&ab8500_battery>;
 653                                 };
 654
 655                                 ab8500_charger {
 656                                         compatible      = "stericsson,ab8500-charger";
 657                                         battery         = <&ab8500_battery>;
 658                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 659                                 };
 660
 661                                 ab8500_chargalg {
 662                                         compatible      = "stericsson,ab8500-chargalg";
 663                                         battery         = <&ab8500_battery>;
 664                                 };
 665
 666                                 ab8500_usb {
 667                                         compatible = "stericsson,ab8500-usb";
 668                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 669                                                        96 IRQ_TYPE_LEVEL_HIGH
 670                                                        14 IRQ_TYPE_LEVEL_HIGH
 671                                                        15 IRQ_TYPE_LEVEL_HIGH
 672                                                        79 IRQ_TYPE_LEVEL_HIGH
 673                                                        74 IRQ_TYPE_LEVEL_HIGH
 674                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 675                                         interrupt-names = "ID_WAKEUP_R",
 676                                                           "ID_WAKEUP_F",
 677                                                           "VBUS_DET_F",
 678                                                           "VBUS_DET_R",
 679                                                           "USB_LINK_STATUS",
 680                                                           "USB_ADP_PROBE_PLUG",
 681                                                           "USB_ADP_PROBE_UNPLUG";
 682                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 683                                         v-ape-supply = <&db8500_vape_reg>;
 684                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 685                                         clocks = <&prcmu_clk PRCMU_SYSCLK>;
 686                                         clock-names = "sysclk";
 687                                 };
 688
 689                                 ab8500-ponkey {
 690                                         compatible = "stericsson,ab8500-poweron-key";
 691                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 692                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 693                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 694                                 };
 695
 696                                 ab8500-sysctrl {
 697                                         compatible = "stericsson,ab8500-sysctrl";
 698                                 };
 699
 700                                 ab8500-pwm {
 701                                         compatible = "stericsson,ab8500-pwm";
 702                                         clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
 703                                         clock-names = "intclk";
 704                                 };
 705
 706                                 ab8500-debugfs {
 707                                         compatible = "stericsson,ab8500-debug";
 708                                 };
 709
 710                                 codec: ab8500-codec {
 711                                         compatible = "stericsson,ab8500-codec";
 712
 713                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 714                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 715                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 716                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 717
 718                                         clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
 719                                         clock-names = "audioclk";
 720
 721                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 722                                 };
 723
 724                                 ext_regulators: ab8500-ext-regulators {
 725                                         compatible = "stericsson,ab8500-ext-regulator";
 726
 727                                         ab8500_ext1_reg: ab8500_ext1 {
 728                                                 regulator-min-microvolt = <1800000>;
 729                                                 regulator-max-microvolt = <1800000>;
 730                                                 regulator-boot-on;
 731                                                 regulator-always-on;
 732                                         };
 733
 734                                         ab8500_ext2_reg: ab8500_ext2 {
 735                                                 regulator-min-microvolt = <1360000>;
 736                                                 regulator-max-microvolt = <1360000>;
 737                                                 regulator-boot-on;
 738                                                 regulator-always-on;
 739                                         };
 740
 741                                         ab8500_ext3_reg: ab8500_ext3 {
 742                                                 regulator-min-microvolt = <3400000>;
 743                                                 regulator-max-microvolt = <3400000>;
 744                                                 regulator-boot-on;
 745                                         };
 746                                 };
 747
 748                                 ab8500-regulators {
 749                                         compatible = "stericsson,ab8500-regulator";
 750                                         vin-supply = <&ab8500_ext3_reg>;
 751
 752                                         // supplies to the display/camera
 753                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 754                                                 regulator-min-microvolt = <2500000>;
 755                                                 regulator-max-microvolt = <2900000>;
 756                                                 regulator-boot-on;
 757                                                 /* BUG: If turned off MMC will be affected. */
 758                                                 regulator-always-on;
 759                                         };
 760
 761                                         // supplies to the on-board eMMC
 762                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 763                                                 regulator-min-microvolt = <1100000>;
 764                                                 regulator-max-microvolt = <3300000>;
 765                                         };
 766
 767                                         // supply for VAUX3; SDcard slots
 768                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 769                                                 regulator-min-microvolt = <1100000>;
 770                                                 regulator-max-microvolt = <3300000>;
 771                                         };
 772
 773                                         // supply for v-intcore12; VINTCORE12 LDO
 774                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 775                                         };
 776
 777                                         // supply for tvout; gpadc; TVOUT LDO
 778                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 779                                         };
 780
 781                                         // supply for ab8500-usb; USB LDO
 782                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 783                                         };
 784
 785                                         // supply for ab8500-vaudio; VAUDIO LDO
 786                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 787                                         };
 788
 789                                         // supply for v-anamic1 VAMIC1 LDO
 790                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 791                                         };
 792
 793                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 794                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 795                                         };
 796
 797                                         // supply for v-dmic; VDMIC LDO
 798                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 799                                         };
 800
 801                                         // supply for U8500 CSI/DSI; VANA LDO
 802                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 803                                         };
 804                                 };
 805                         };
 806                 };
 807
 808                 i2c@80004000 {
 809                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 810                         reg = <0x80004000 0x1000>;
 811                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 812
 813                         #address-cells = <1>;
 814                         #size-cells = <0>;
 815                         v-i2c-supply = <&db8500_vape_reg>;
 816
 817                         clock-frequency = <400000>;
 818                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 819                         clock-names = "i2cclk", "apb_pclk";
 820                         power-domains = <&pm_domains DOMAIN_VAPE>;
 821                 };
 822
 823                 i2c@80122000 {
 824                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 825                         reg = <0x80122000 0x1000>;
 826                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 827
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830                         v-i2c-supply = <&db8500_vape_reg>;
 831
 832                         clock-frequency = <400000>;
 833
 834                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 835                         clock-names = "i2cclk", "apb_pclk";
 836                         power-domains = <&pm_domains DOMAIN_VAPE>;
 837                 };
 838
 839                 i2c@80128000 {
 840                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 841                         reg = <0x80128000 0x1000>;
 842                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 843
 844                         #address-cells = <1>;
 845                         #size-cells = <0>;
 846                         v-i2c-supply = <&db8500_vape_reg>;
 847
 848                         clock-frequency = <400000>;
 849
 850                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 851                         clock-names = "i2cclk", "apb_pclk";
 852                         power-domains = <&pm_domains DOMAIN_VAPE>;
 853                 };
 854
 855                 i2c@80110000 {
 856                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 857                         reg = <0x80110000 0x1000>;
 858                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 859
 860                         #address-cells = <1>;
 861                         #size-cells = <0>;
 862                         v-i2c-supply = <&db8500_vape_reg>;
 863
 864                         clock-frequency = <400000>;
 865
 866                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 867                         clock-names = "i2cclk", "apb_pclk";
 868                         power-domains = <&pm_domains DOMAIN_VAPE>;
 869                 };
 870
 871                 i2c@8012a000 {
 872                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 873                         reg = <0x8012a000 0x1000>;
 874                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 875
 876                         #address-cells = <1>;
 877                         #size-cells = <0>;
 878                         v-i2c-supply = <&db8500_vape_reg>;
 879
 880                         clock-frequency = <400000>;
 881
 882                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 883                         clock-names = "i2cclk", "apb_pclk";
 884                         power-domains = <&pm_domains DOMAIN_VAPE>;
 885                 };
 886
 887                 spi@80002000 {
 888                         compatible = "arm,pl022", "arm,primecell";
 889                         reg = <0x80002000 0x1000>;
 890                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 891                         #address-cells = <1>;
 892                         #size-cells = <0>;
 893                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 894                         clock-names = "SSPCLK", "apb_pclk";
 895                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 896                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 897                         dma-names = "rx", "tx";
 898                         power-domains = <&pm_domains DOMAIN_VAPE>;
 899                 };
 900
 901                 spi@80003000 {
 902                         compatible = "arm,pl022", "arm,primecell";
 903                         reg = <0x80003000 0x1000>;
 904                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 905                         #address-cells = <1>;
 906                         #size-cells = <0>;
 907                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 908                         clock-names = "SSPCLK", "apb_pclk";
 909                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 910                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 911                         dma-names = "rx", "tx";
 912                         power-domains = <&pm_domains DOMAIN_VAPE>;
 913                 };
 914
 915                 spi@8011a000 {
 916                         compatible = "arm,pl022", "arm,primecell";
 917                         reg = <0x8011a000 0x1000>;
 918                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 919                         #address-cells = <1>;
 920                         #size-cells = <0>;
 921                         /* Same clock wired to kernel and pclk */
 922                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 923                         clock-names = "SSPCLK", "apb_pclk";
 924                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 925                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 926                         dma-names = "rx", "tx";
 927                         power-domains = <&pm_domains DOMAIN_VAPE>;
 928                 };
 929
 930                 spi@80112000 {
 931                         compatible = "arm,pl022", "arm,primecell";
 932                         reg = <0x80112000 0x1000>;
 933                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 934                         #address-cells = <1>;
 935                         #size-cells = <0>;
 936                         /* Same clock wired to kernel and pclk */
 937                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 938                         clock-names = "SSPCLK", "apb_pclk";
 939                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 940                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 941                         dma-names = "rx", "tx";
 942                         power-domains = <&pm_domains DOMAIN_VAPE>;
 943                 };
 944
 945                 spi@80111000 {
 946                         compatible = "arm,pl022", "arm,primecell";
 947                         reg = <0x80111000 0x1000>;
 948                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 949                         #address-cells = <1>;
 950                         #size-cells = <0>;
 951                         /* Same clock wired to kernel and pclk */
 952                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 953                         clock-names = "SSPCLK", "apb_pclk";
 954                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 955                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 956                         dma-names = "rx", "tx";
 957                         power-domains = <&pm_domains DOMAIN_VAPE>;
 958                 };
 959
 960                 spi@80129000 {
 961                         compatible = "arm,pl022", "arm,primecell";
 962                         reg = <0x80129000 0x1000>;
 963                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 964                         #address-cells = <1>;
 965                         #size-cells = <0>;
 966                         /* Same clock wired to kernel and pclk */
 967                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 968                         clock-names = "SSPCLK", "apb_pclk";
 969                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 970                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 971                         dma-names = "rx", "tx";
 972                         power-domains = <&pm_domains DOMAIN_VAPE>;
 973                 };
 974
 975                 ux500_serial0: uart@80120000 {
 976                         compatible = "arm,pl011", "arm,primecell";
 977                         reg = <0x80120000 0x1000>;
 978                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 979
 980                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 981                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 982                         dma-names = "rx", "tx";
 983
 984                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 985                         clock-names = "uart", "apb_pclk";
 986
 987                         status = "disabled";
 988                 };
 989
 990                 ux500_serial1: uart@80121000 {
 991                         compatible = "arm,pl011", "arm,primecell";
 992                         reg = <0x80121000 0x1000>;
 993                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 994
 995                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 996                                <&dma 12 0 0x0>; /* Logical - MemToDev */
 997                         dma-names = "rx", "tx";
 998
 999                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
1000                         clock-names = "uart", "apb_pclk";
1001
1002                         status = "disabled";
1003                 };
1004
1005                 ux500_serial2: uart@80007000 {
1006                         compatible = "arm,pl011", "arm,primecell";
1007                         reg = <0x80007000 0x1000>;
1008                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1009
1010                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1011                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1012                         dma-names = "rx", "tx";
1013
1014                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1015                         clock-names = "uart", "apb_pclk";
1016
1017                         status = "disabled";
1018                 };
1019
1020                 sdi0_per1@80126000 {
1021                         compatible = "arm,pl18x", "arm,primecell";
1022                         reg = <0x80126000 0x1000>;
1023                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1024
1025                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1026                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1027                         dma-names = "rx", "tx";
1028
1029                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1030                         clock-names = "sdi", "apb_pclk";
1031                         power-domains = <&pm_domains DOMAIN_VAPE>;
1032
1033                         status = "disabled";
1034                 };
1035
1036                 sdi1_per2@80118000 {
1037                         compatible = "arm,pl18x", "arm,primecell";
1038                         reg = <0x80118000 0x1000>;
1039                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1040
1041                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1042                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1043                         dma-names = "rx", "tx";
1044
1045                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1046                         clock-names = "sdi", "apb_pclk";
1047                         power-domains = <&pm_domains DOMAIN_VAPE>;
1048
1049                         status = "disabled";
1050                 };
1051
1052                 sdi2_per3@80005000 {
1053                         compatible = "arm,pl18x", "arm,primecell";
1054                         reg = <0x80005000 0x1000>;
1055                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1056
1057                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1058                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1059                         dma-names = "rx", "tx";
1060
1061                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1062                         clock-names = "sdi", "apb_pclk";
1063                         power-domains = <&pm_domains DOMAIN_VAPE>;
1064
1065                         status = "disabled";
1066                 };
1067
1068                 sdi3_per2@80119000 {
1069                         compatible = "arm,pl18x", "arm,primecell";
1070                         reg = <0x80119000 0x1000>;
1071                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1072
1073                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1074                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1075                         dma-names = "rx", "tx";
1076
1077                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1078                         clock-names = "sdi", "apb_pclk";
1079                         power-domains = <&pm_domains DOMAIN_VAPE>;
1080
1081                         status = "disabled";
1082                 };
1083
1084                 sdi4_per2@80114000 {
1085                         compatible = "arm,pl18x", "arm,primecell";
1086                         reg = <0x80114000 0x1000>;
1087                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1088
1089                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1090                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1091                         dma-names = "rx", "tx";
1092
1093                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1094                         clock-names = "sdi", "apb_pclk";
1095                         power-domains = <&pm_domains DOMAIN_VAPE>;
1096
1097                         status = "disabled";
1098                 };
1099
1100                 sdi5_per3@80008000 {
1101                         compatible = "arm,pl18x", "arm,primecell";
1102                         reg = <0x80008000 0x1000>;
1103                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1104
1105                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1106                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1107                         dma-names = "rx", "tx";
1108
1109                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1110                         clock-names = "sdi", "apb_pclk";
1111                         power-domains = <&pm_domains DOMAIN_VAPE>;
1112
1113                         status = "disabled";
1114                 };
1115
1116                 sound {
1117                         compatible = "stericsson,snd-soc-mop500";
1118                         stericsson,cpu-dai = <&msp1 &msp3>;
1119                         stericsson,audio-codec = <&codec>;
1120                         clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
1121                         clock-names = "sysclk", "ulpclk", "intclk";
1122                 };
1123
1124                 msp0: msp@80123000 {
1125                         compatible = "stericsson,ux500-msp-i2s";
1126                         reg = <0x80123000 0x1000>;
1127                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1128                         v-ape-supply = <&db8500_vape_reg>;
1129
1130                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1131                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1132                         dma-names = "rx", "tx";
1133
1134                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1135                         clock-names = "msp", "apb_pclk";
1136
1137                         status = "disabled";
1138                 };
1139
1140                 msp1: msp@80124000 {
1141                         compatible = "stericsson,ux500-msp-i2s";
1142                         reg = <0x80124000 0x1000>;
1143                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1144                         v-ape-supply = <&db8500_vape_reg>;
1145
1146                         /* This DMA channel only exist on DB8500 v1 */
1147                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1148                         dma-names = "tx";
1149
1150                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1151                         clock-names = "msp", "apb_pclk";
1152
1153                         status = "disabled";
1154                 };
1155
1156                 // HDMI sound
1157                 msp2: msp@80117000 {
1158                         compatible = "stericsson,ux500-msp-i2s";
1159                         reg = <0x80117000 0x1000>;
1160                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1161                         v-ape-supply = <&db8500_vape_reg>;
1162
1163                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1164                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1165                                                     HighPrio - Fixed */
1166                         dma-names = "rx", "tx";
1167
1168                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1169                         clock-names = "msp", "apb_pclk";
1170
1171                         status = "disabled";
1172                 };
1173
1174                 msp3: msp@80125000 {
1175                         compatible = "stericsson,ux500-msp-i2s";
1176                         reg = <0x80125000 0x1000>;
1177                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1178                         v-ape-supply = <&db8500_vape_reg>;
1179
1180                         /* This DMA channel only exist on DB8500 v2 */
1181                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1182                         dma-names = "rx";
1183
1184                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1185                         clock-names = "msp", "apb_pclk";
1186
1187                         status = "disabled";
1188                 };
1189
1190                 external-bus@50000000 {
1191                         compatible = "simple-bus";
1192                         reg = <0x50000000 0x4000000>;
1193                         #address-cells = <1>;
1194                         #size-cells = <1>;
1195                         ranges = <0 0x50000000 0x4000000>;
1196                         status = "disabled";
1197                 };
1198
1199                 mcde@a0350000 {
1200                         compatible = "stericsson,mcde";
1201                         reg = <0xa0350000 0x1000>, /* MCDE */
1202                               <0xa0351000 0x1000>, /* DSI link 1 */
1203                               <0xa0352000 0x1000>, /* DSI link 2 */
1204                               <0xa0353000 0x1000>; /* DSI link 3 */
1205                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1206                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1207                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1208                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1209                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1210                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1211                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1212                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1213                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1214                 };
1215
1216                 cryp@a03cb000 {
1217                         compatible = "stericsson,ux500-cryp";
1218                         reg = <0xa03cb000 0x1000>;
1219                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1220
1221                         v-ape-supply = <&db8500_vape_reg>;
1222                         clocks = <&prcc_pclk 6 1>;
1223                 };
1224
1225                 hash@a03c2000 {
1226                         compatible = "stericsson,ux500-hash";
1227                         reg = <0xa03c2000 0x1000>;
1228
1229                         v-ape-supply = <&db8500_vape_reg>;
1230                         clocks = <&prcc_pclk 6 2>;
1231                 };
1232         };
1233 };