arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2012 Linaro Ltd
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/mfd/dbx500-prcmu.h>
   9 #include <dt-bindings/arm/ux500_pm_domains.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/clock/ste-ab8500.h>
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         chosen {
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 enable-method = "ste,dbx500-smp";
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&CPU0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&CPU1>;
  32                                 };
  33                         };
  34                 };
  35                 CPU0: cpu@300 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <0x300>;
  39                         /* cpufreq controls */
  40                         operating-points = <998400 0
  41                                             800000 0
  42                                             400000 0
  43                                             200000 0>;
  44                         clocks = <&prcmu_clk PRCMU_ARMSS>;
  45                         clock-names = "cpu";
  46                         clock-latency = <20000>;
  47                 };
  48                 CPU1: cpu@301 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         reg = <0x301>;
  52                 };
  53         };
  54
  55         soc {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 compatible = "stericsson,db8500";
  59                 interrupt-parent = <&intc>;
  60                 ranges;
  61
  62                 ptm@801ae000 {
  63                         compatible = "arm,coresight-etm3x", "arm,primecell";
  64                         reg = <0x801ae000 0x1000>;
  65
  66                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  67                         clock-names = "apb_pclk", "atclk";
  68                         cpu = <&CPU0>;
  69                         out-ports {
  70                                 port {
  71                                         ptm0_out_port: endpoint {
  72                                                 remote-endpoint = <&funnel_in_port0>;
  73                                         };
  74                                 };
  75                         };
  76                 };
  77
  78                 ptm@801af000 {
  79                         compatible = "arm,coresight-etm3x", "arm,primecell";
  80                         reg = <0x801af000 0x1000>;
  81
  82                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  83                         clock-names = "apb_pclk", "atclk";
  84                         cpu = <&CPU1>;
  85                         out-ports {
  86                                 port {
  87                                         ptm1_out_port: endpoint {
  88                                                 remote-endpoint = <&funnel_in_port1>;
  89                                         };
  90                                 };
  91                         };
  92                 };
  93
  94                 funnel@801a6000 {
  95                         compatible = "arm,coresight-funnel", "arm,primecell";
  96                         reg = <0x801a6000 0x1000>;
  97
  98                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  99                         clock-names = "apb_pclk", "atclk";
 100                         out-ports {
 101                                 port {
 102                                         funnel_out_port: endpoint {
 103                                                 remote-endpoint =
 104                                                         <&replicator_in_port0>;
 105                                         };
 106                                 };
 107                         };
 108
 109                         in-ports {
 110                                 #address-cells = <1>;
 111                                 #size-cells = <0>;
 112
 113                                 port@0 {
 114                                         reg = <0>;
 115                                         funnel_in_port0: endpoint {
 116                                                 remote-endpoint = <&ptm0_out_port>;
 117                                         };
 118                                 };
 119
 120                                 port@1 {
 121                                         reg = <1>;
 122                                         funnel_in_port1: endpoint {
 123                                                 remote-endpoint = <&ptm1_out_port>;
 124                                         };
 125                                 };
 126                         };
 127                 };
 128
 129                 replicator {
 130                         compatible = "arm,coresight-replicator";
 131                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 132                         clock-names = "atclk";
 133
 134                         out-ports {
 135                                 #address-cells = <1>;
 136                                 #size-cells = <0>;
 137
 138                                 port@0 {
 139                                         reg = <0>;
 140                                         replicator_out_port0: endpoint {
 141                                                 remote-endpoint = <&tpiu_in_port>;
 142                                         };
 143                                 };
 144                                 port@1 {
 145                                         reg = <1>;
 146                                         replicator_out_port1: endpoint {
 147                                                 remote-endpoint = <&etb_in_port>;
 148                                         };
 149                                 };
 150                         };
 151
 152                         in-ports {
 153                                 port {
 154                                         replicator_in_port0: endpoint {
 155                                                 remote-endpoint = <&funnel_out_port>;
 156                                         };
 157                                 };
 158                         };
 159                 };
 160
 161                 tpiu@80190000 {
 162                         compatible = "arm,coresight-tpiu", "arm,primecell";
 163                         reg = <0x80190000 0x1000>;
 164
 165                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 166                         clock-names = "apb_pclk", "atclk";
 167                         in-ports {
 168                                 port {
 169                                         tpiu_in_port: endpoint {
 170                                                 remote-endpoint = <&replicator_out_port0>;
 171                                         };
 172                                 };
 173                         };
 174                 };
 175
 176                 etb@801a4000 {
 177                         compatible = "arm,coresight-etb10", "arm,primecell";
 178                         reg = <0x801a4000 0x1000>;
 179
 180                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 181                         clock-names = "apb_pclk", "atclk";
 182                         in-ports {
 183                                 port {
 184                                         etb_in_port: endpoint {
 185                                                 remote-endpoint = <&replicator_out_port1>;
 186                                         };
 187                                 };
 188                         };
 189                 };
 190
 191                 intc: interrupt-controller@a0411000 {
 192                         compatible = "arm,cortex-a9-gic";
 193                         #interrupt-cells = <3>;
 194                         #address-cells = <1>;
 195                         interrupt-controller;
 196                         reg = <0xa0411000 0x1000>,
 197                               <0xa0410100 0x100>;
 198                 };
 199
 200                 scu@a0410000 {
 201                         compatible = "arm,cortex-a9-scu";
 202                         reg = <0xa0410000 0x100>;
 203                 };
 204
 205                 /*
 206                  * The backup RAM is used for retention during sleep
 207                  * and various things like spin tables
 208                  */
 209                 backupram@80150000 {
 210                         compatible = "ste,dbx500-backupram";
 211                         reg = <0x80150000 0x2000>;
 212                 };
 213
 214                 L2: l2-cache {
 215                         compatible = "arm,pl310-cache";
 216                         reg = <0xa0412000 0x1000>;
 217                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 218                         cache-unified;
 219                         cache-level = <2>;
 220                 };
 221
 222                 pmu {
 223                         compatible = "arm,cortex-a9-pmu";
 224                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 225                 };
 226
 227                 pm_domains: pm_domains0 {
 228                         compatible = "stericsson,ux500-pm-domains";
 229                         #power-domain-cells = <1>;
 230                 };
 231
 232                 clocks {
 233                         compatible = "stericsson,u8500-clks";
 234                         /*
 235                          * Registers for the CLKRST block on peripheral
 236                          * groups 1, 2, 3, 5, 6,
 237                          */
 238                         reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
 239                             <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
 240                             <0xa03cf000 0x1000>;
 241
 242                         prcmu_clk: prcmu-clock {
 243                                 #clock-cells = <1>;
 244                         };
 245
 246                         prcc_pclk: prcc-periph-clock {
 247                                 #clock-cells = <2>;
 248                         };
 249
 250                         prcc_kclk: prcc-kernel-clock {
 251                                 #clock-cells = <2>;
 252                         };
 253
 254                         rtc_clk: rtc32k-clock {
 255                                 #clock-cells = <0>;
 256                         };
 257
 258                         smp_twd_clk: smp-twd-clock {
 259                                 #clock-cells = <0>;
 260                         };
 261                 };
 262
 263                 mtu@a03c6000 {
 264                         /* Nomadik System Timer */
 265                         compatible = "st,nomadik-mtu";
 266                         reg = <0xa03c6000 0x1000>;
 267                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 268
 269                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 270                         clock-names = "timclk", "apb_pclk";
 271                 };
 272
 273                 timer@a0410600 {
 274                         compatible = "arm,cortex-a9-twd-timer";
 275                         reg = <0xa0410600 0x20>;
 276                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 277
 278                         clocks = <&smp_twd_clk>;
 279                 };
 280
 281                 watchdog@a0410620 {
 282                         compatible = "arm,cortex-a9-twd-wdt";
 283                         reg = <0xa0410620 0x20>;
 284                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 285                         clocks = <&smp_twd_clk>;
 286                 };
 287
 288                 rtc@80154000 {
 289                         compatible = "arm,rtc-pl031", "arm,primecell";
 290                         reg = <0x80154000 0x1000>;
 291                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 292
 293                         clocks = <&rtc_clk>;
 294                         clock-names = "apb_pclk";
 295                 };
 296
 297                 gpio0: gpio@8012e000 {
 298                         compatible = "stericsson,db8500-gpio",
 299                                 "st,nomadik-gpio";
 300                         reg =  <0x8012e000 0x80>;
 301                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 302                         interrupt-controller;
 303                         #interrupt-cells = <2>;
 304                         st,supports-sleepmode;
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307                         gpio-bank = <0>;
 308                         gpio-ranges = <&pinctrl 0 0 32>;
 309                         clocks = <&prcc_pclk 1 9>;
 310                 };
 311
 312                 gpio1: gpio@8012e080 {
 313                         compatible = "stericsson,db8500-gpio",
 314                                 "st,nomadik-gpio";
 315                         reg =  <0x8012e080 0x80>;
 316                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                         st,supports-sleepmode;
 320                         gpio-controller;
 321                         #gpio-cells = <2>;
 322                         gpio-bank = <1>;
 323                         gpio-ranges = <&pinctrl 0 32 5>;
 324                         clocks = <&prcc_pclk 1 9>;
 325                 };
 326
 327                 gpio2: gpio@8000e000 {
 328                         compatible = "stericsson,db8500-gpio",
 329                                 "st,nomadik-gpio";
 330                         reg =  <0x8000e000 0x80>;
 331                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 332                         interrupt-controller;
 333                         #interrupt-cells = <2>;
 334                         st,supports-sleepmode;
 335                         gpio-controller;
 336                         #gpio-cells = <2>;
 337                         gpio-bank = <2>;
 338                         gpio-ranges = <&pinctrl 0 64 32>;
 339                         clocks = <&prcc_pclk 3 8>;
 340                 };
 341
 342                 gpio3: gpio@8000e080 {
 343                         compatible = "stericsson,db8500-gpio",
 344                                 "st,nomadik-gpio";
 345                         reg =  <0x8000e080 0x80>;
 346                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349                         st,supports-sleepmode;
 350                         gpio-controller;
 351                         #gpio-cells = <2>;
 352                         gpio-bank = <3>;
 353                         gpio-ranges = <&pinctrl 0 96 2>;
 354                         clocks = <&prcc_pclk 3 8>;
 355                 };
 356
 357                 gpio4: gpio@8000e100 {
 358                         compatible = "stericsson,db8500-gpio",
 359                                 "st,nomadik-gpio";
 360                         reg =  <0x8000e100 0x80>;
 361                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 362                         interrupt-controller;
 363                         #interrupt-cells = <2>;
 364                         st,supports-sleepmode;
 365                         gpio-controller;
 366                         #gpio-cells = <2>;
 367                         gpio-bank = <4>;
 368                         gpio-ranges = <&pinctrl 0 128 32>;
 369                         clocks = <&prcc_pclk 3 8>;
 370                 };
 371
 372                 gpio5: gpio@8000e180 {
 373                         compatible = "stericsson,db8500-gpio",
 374                                 "st,nomadik-gpio";
 375                         reg =  <0x8000e180 0x80>;
 376                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 377                         interrupt-controller;
 378                         #interrupt-cells = <2>;
 379                         st,supports-sleepmode;
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         gpio-bank = <5>;
 383                         gpio-ranges = <&pinctrl 0 160 12>;
 384                         clocks = <&prcc_pclk 3 8>;
 385                 };
 386
 387                 gpio6: gpio@8011e000 {
 388                         compatible = "stericsson,db8500-gpio",
 389                                 "st,nomadik-gpio";
 390                         reg =  <0x8011e000 0x80>;
 391                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 392                         interrupt-controller;
 393                         #interrupt-cells = <2>;
 394                         st,supports-sleepmode;
 395                         gpio-controller;
 396                         #gpio-cells = <2>;
 397                         gpio-bank = <6>;
 398                         gpio-ranges = <&pinctrl 0 192 32>;
 399                         clocks = <&prcc_pclk 2 11>;
 400                 };
 401
 402                 gpio7: gpio@8011e080 {
 403                         compatible = "stericsson,db8500-gpio",
 404                                 "st,nomadik-gpio";
 405                         reg =  <0x8011e080 0x80>;
 406                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 407                         interrupt-controller;
 408                         #interrupt-cells = <2>;
 409                         st,supports-sleepmode;
 410                         gpio-controller;
 411                         #gpio-cells = <2>;
 412                         gpio-bank = <7>;
 413                         gpio-ranges = <&pinctrl 0 224 7>;
 414                         clocks = <&prcc_pclk 2 11>;
 415                 };
 416
 417                 gpio8: gpio@a03fe000 {
 418                         compatible = "stericsson,db8500-gpio",
 419                                 "st,nomadik-gpio";
 420                         reg =  <0xa03fe000 0x80>;
 421                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 422                         interrupt-controller;
 423                         #interrupt-cells = <2>;
 424                         st,supports-sleepmode;
 425                         gpio-controller;
 426                         #gpio-cells = <2>;
 427                         gpio-bank = <8>;
 428                         gpio-ranges = <&pinctrl 0 256 12>;
 429                         clocks = <&prcc_pclk 5 1>;
 430                 };
 431
 432                 pinctrl: pinctrl {
 433                         compatible = "stericsson,db8500-pinctrl";
 434                         nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
 435                                                 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
 436                                                 <&gpio8>;
 437                         prcm = <&prcmu>;
 438                 };
 439
 440                 usb_per5@a03e0000 {
 441                         compatible = "stericsson,db8500-musb";
 442                         reg = <0xa03e0000 0x10000>;
 443                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 444                         interrupt-names = "mc";
 445
 446                         dr_mode = "otg";
 447
 448                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 449                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 450                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 451                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 452                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 453                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 454                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 455                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 456                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 457                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 458                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 459                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 460                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 461                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 462                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 463                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 464
 465                         dma-names = "iep_1_9",  "oep_1_9",
 466                                     "iep_2_10", "oep_2_10",
 467                                     "iep_3_11", "oep_3_11",
 468                                     "iep_4_12", "oep_4_12",
 469                                     "iep_5_13", "oep_5_13",
 470                                     "iep_6_14", "oep_6_14",
 471                                     "iep_7_15", "oep_7_15",
 472                                     "iep_8",    "oep_8";
 473
 474                         clocks = <&prcc_pclk 5 0>;
 475                 };
 476
 477                 dma: dma-controller@801C0000 {
 478                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 479                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 480                         reg-names = "base", "lcpa";
 481                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 482
 483                         #dma-cells = <3>;
 484                         memcpy-channels = <56 57 58 59 60>;
 485
 486                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 487                 };
 488
 489                 prcmu: prcmu@80157000 {
 490                         compatible = "stericsson,db8500-prcmu", "syscon";
 491                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 492                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 493                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 494                         #address-cells = <1>;
 495                         #size-cells = <1>;
 496                         interrupt-controller;
 497                         #interrupt-cells = <2>;
 498                         ranges;
 499
 500                         prcmu-timer-4@80157450 {
 501                                 compatible = "stericsson,db8500-prcmu-timer-4";
 502                                 reg = <0x80157450 0xC>;
 503                         };
 504
 505                         thermal@801573c0 {
 506                                 compatible = "stericsson,db8500-thermal";
 507                                 reg = <0x801573c0 0x40>;
 508                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 509                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 510                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 511                                 status = "disabled";
 512                         };
 513
 514                         db8500-prcmu-regulators {
 515                                 compatible = "stericsson,db8500-prcmu-regulator";
 516
 517                                 // DB8500_REGULATOR_VAPE
 518                                 db8500_vape_reg: db8500_vape {
 519                                         regulator-always-on;
 520                                 };
 521
 522                                 // DB8500_REGULATOR_VARM
 523                                 db8500_varm_reg: db8500_varm {
 524                                 };
 525
 526                                 // DB8500_REGULATOR_VMODEM
 527                                 db8500_vmodem_reg: db8500_vmodem {
 528                                 };
 529
 530                                 // DB8500_REGULATOR_VPLL
 531                                 db8500_vpll_reg: db8500_vpll {
 532                                 };
 533
 534                                 // DB8500_REGULATOR_VSMPS1
 535                                 db8500_vsmps1_reg: db8500_vsmps1 {
 536                                 };
 537
 538                                 // DB8500_REGULATOR_VSMPS2
 539                                 db8500_vsmps2_reg: db8500_vsmps2 {
 540                                 };
 541
 542                                 // DB8500_REGULATOR_VSMPS3
 543                                 db8500_vsmps3_reg: db8500_vsmps3 {
 544                                 };
 545
 546                                 // DB8500_REGULATOR_VRF1
 547                                 db8500_vrf1_reg: db8500_vrf1 {
 548                                 };
 549
 550                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 551                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 552                                 };
 553
 554                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 555                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 556                                 };
 557
 558                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 559                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 560                                 };
 561
 562                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 563                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 564                                 };
 565
 566                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 567                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 568                                 };
 569
 570                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 571                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 572                                 };
 573
 574                                 // DB8500_REGULATOR_SWITCH_SGA
 575                                 db8500_sga_reg: db8500_sga {
 576                                         vin-supply = <&db8500_vape_reg>;
 577                                 };
 578
 579                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 580                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 581                                         vin-supply = <&db8500_vape_reg>;
 582                                 };
 583
 584                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 585                                 db8500_esram12_reg: db8500_esram12 {
 586                                 };
 587
 588                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 589                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 590                                 };
 591
 592                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 593                                 db8500_esram34_reg: db8500_esram34 {
 594                                 };
 595
 596                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 597                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 598                                 };
 599                         };
 600
 601                         ab8500 {
 602                                 compatible = "stericsson,ab8500";
 603                                 interrupt-parent = <&intc>;
 604                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 605                                 interrupt-controller;
 606                                 #interrupt-cells = <2>;
 607
 608                                 ab8500_clock: clock-controller {
 609                                         compatible = "stericsson,ab8500-clk";
 610                                         #clock-cells = <1>;
 611                                 };
 612
 613                                 ab8500_gpio: ab8500-gpio {
 614                                         compatible = "stericsson,ab8500-gpio";
 615                                         gpio-controller;
 616                                         #gpio-cells = <2>;
 617                                 };
 618
 619                                 ab8500-rtc {
 620                                         compatible = "stericsson,ab8500-rtc";
 621                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 622                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 623                                         interrupt-names = "60S", "ALARM";
 624                                 };
 625
 626                                 ab8500-gpadc {
 627                                         compatible = "stericsson,ab8500-gpadc";
 628                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 629                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 630                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 631                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 632                                 };
 633
 634                                 ab8500_battery: ab8500_battery {
 635                                         stericsson,battery-type = "LIPO";
 636                                         thermistor-on-batctrl;
 637                                 };
 638
 639                                 ab8500_fg {
 640                                         compatible = "stericsson,ab8500-fg";
 641                                         battery    = <&ab8500_battery>;
 642                                 };
 643
 644                                 ab8500_btemp {
 645                                         compatible = "stericsson,ab8500-btemp";
 646                                         battery    = <&ab8500_battery>;
 647                                 };
 648
 649                                 ab8500_charger {
 650                                         compatible      = "stericsson,ab8500-charger";
 651                                         battery         = <&ab8500_battery>;
 652                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 653                                 };
 654
 655                                 ab8500_chargalg {
 656                                         compatible      = "stericsson,ab8500-chargalg";
 657                                         battery         = <&ab8500_battery>;
 658                                 };
 659
 660                                 ab8500_usb {
 661                                         compatible = "stericsson,ab8500-usb";
 662                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 663                                                        96 IRQ_TYPE_LEVEL_HIGH
 664                                                        14 IRQ_TYPE_LEVEL_HIGH
 665                                                        15 IRQ_TYPE_LEVEL_HIGH
 666                                                        79 IRQ_TYPE_LEVEL_HIGH
 667                                                        74 IRQ_TYPE_LEVEL_HIGH
 668                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 669                                         interrupt-names = "ID_WAKEUP_R",
 670                                                           "ID_WAKEUP_F",
 671                                                           "VBUS_DET_F",
 672                                                           "VBUS_DET_R",
 673                                                           "USB_LINK_STATUS",
 674                                                           "USB_ADP_PROBE_PLUG",
 675                                                           "USB_ADP_PROBE_UNPLUG";
 676                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 677                                         v-ape-supply = <&db8500_vape_reg>;
 678                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 679                                         clocks = <&prcmu_clk PRCMU_SYSCLK>;
 680                                         clock-names = "sysclk";
 681                                 };
 682
 683                                 ab8500-ponkey {
 684                                         compatible = "stericsson,ab8500-poweron-key";
 685                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 686                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 687                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 688                                 };
 689
 690                                 ab8500-sysctrl {
 691                                         compatible = "stericsson,ab8500-sysctrl";
 692                                 };
 693
 694                                 ab8500-pwm {
 695                                         compatible = "stericsson,ab8500-pwm";
 696                                         clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
 697                                         clock-names = "intclk";
 698                                 };
 699
 700                                 ab8500-debugfs {
 701                                         compatible = "stericsson,ab8500-debug";
 702                                 };
 703
 704                                 codec: ab8500-codec {
 705                                         compatible = "stericsson,ab8500-codec";
 706
 707                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 708                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 709                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 710                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 711
 712                                         clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
 713                                         clock-names = "audioclk";
 714
 715                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 716                                 };
 717
 718                                 ext_regulators: ab8500-ext-regulators {
 719                                         compatible = "stericsson,ab8500-ext-regulator";
 720
 721                                         ab8500_ext1_reg: ab8500_ext1 {
 722                                                 regulator-min-microvolt = <1800000>;
 723                                                 regulator-max-microvolt = <1800000>;
 724                                                 regulator-boot-on;
 725                                                 regulator-always-on;
 726                                         };
 727
 728                                         ab8500_ext2_reg: ab8500_ext2 {
 729                                                 regulator-min-microvolt = <1360000>;
 730                                                 regulator-max-microvolt = <1360000>;
 731                                                 regulator-boot-on;
 732                                                 regulator-always-on;
 733                                         };
 734
 735                                         ab8500_ext3_reg: ab8500_ext3 {
 736                                                 regulator-min-microvolt = <3400000>;
 737                                                 regulator-max-microvolt = <3400000>;
 738                                                 regulator-boot-on;
 739                                         };
 740                                 };
 741
 742                                 ab8500-regulators {
 743                                         compatible = "stericsson,ab8500-regulator";
 744                                         vin-supply = <&ab8500_ext3_reg>;
 745
 746                                         // supplies to the display/camera
 747                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 748                                                 regulator-min-microvolt = <2500000>;
 749                                                 regulator-max-microvolt = <2900000>;
 750                                                 regulator-boot-on;
 751                                                 /* BUG: If turned off MMC will be affected. */
 752                                                 regulator-always-on;
 753                                         };
 754
 755                                         // supplies to the on-board eMMC
 756                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 757                                                 regulator-min-microvolt = <1100000>;
 758                                                 regulator-max-microvolt = <3300000>;
 759                                         };
 760
 761                                         // supply for VAUX3; SDcard slots
 762                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 763                                                 regulator-min-microvolt = <1100000>;
 764                                                 regulator-max-microvolt = <3300000>;
 765                                         };
 766
 767                                         // supply for v-intcore12; VINTCORE12 LDO
 768                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 769                                         };
 770
 771                                         // supply for tvout; gpadc; TVOUT LDO
 772                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 773                                         };
 774
 775                                         // supply for ab8500-usb; USB LDO
 776                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 777                                         };
 778
 779                                         // supply for ab8500-vaudio; VAUDIO LDO
 780                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 781                                         };
 782
 783                                         // supply for v-anamic1 VAMIC1 LDO
 784                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 785                                         };
 786
 787                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 788                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 789                                         };
 790
 791                                         // supply for v-dmic; VDMIC LDO
 792                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 793                                         };
 794
 795                                         // supply for U8500 CSI/DSI; VANA LDO
 796                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 797                                         };
 798                                 };
 799                         };
 800                 };
 801
 802                 i2c@80004000 {
 803                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 804                         reg = <0x80004000 0x1000>;
 805                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 806
 807                         #address-cells = <1>;
 808                         #size-cells = <0>;
 809                         v-i2c-supply = <&db8500_vape_reg>;
 810
 811                         clock-frequency = <400000>;
 812                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 813                         clock-names = "i2cclk", "apb_pclk";
 814                         power-domains = <&pm_domains DOMAIN_VAPE>;
 815                 };
 816
 817                 i2c@80122000 {
 818                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 819                         reg = <0x80122000 0x1000>;
 820                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 821
 822                         #address-cells = <1>;
 823                         #size-cells = <0>;
 824                         v-i2c-supply = <&db8500_vape_reg>;
 825
 826                         clock-frequency = <400000>;
 827
 828                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 829                         clock-names = "i2cclk", "apb_pclk";
 830                         power-domains = <&pm_domains DOMAIN_VAPE>;
 831                 };
 832
 833                 i2c@80128000 {
 834                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 835                         reg = <0x80128000 0x1000>;
 836                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 837
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                         v-i2c-supply = <&db8500_vape_reg>;
 841
 842                         clock-frequency = <400000>;
 843
 844                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 845                         clock-names = "i2cclk", "apb_pclk";
 846                         power-domains = <&pm_domains DOMAIN_VAPE>;
 847                 };
 848
 849                 i2c@80110000 {
 850                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 851                         reg = <0x80110000 0x1000>;
 852                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 853
 854                         #address-cells = <1>;
 855                         #size-cells = <0>;
 856                         v-i2c-supply = <&db8500_vape_reg>;
 857
 858                         clock-frequency = <400000>;
 859
 860                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 861                         clock-names = "i2cclk", "apb_pclk";
 862                         power-domains = <&pm_domains DOMAIN_VAPE>;
 863                 };
 864
 865                 i2c@8012a000 {
 866                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 867                         reg = <0x8012a000 0x1000>;
 868                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 869
 870                         #address-cells = <1>;
 871                         #size-cells = <0>;
 872                         v-i2c-supply = <&db8500_vape_reg>;
 873
 874                         clock-frequency = <400000>;
 875
 876                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 877                         clock-names = "i2cclk", "apb_pclk";
 878                         power-domains = <&pm_domains DOMAIN_VAPE>;
 879                 };
 880
 881                 spi@80002000 {
 882                         compatible = "arm,pl022", "arm,primecell";
 883                         reg = <0x80002000 0x1000>;
 884                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 885                         #address-cells = <1>;
 886                         #size-cells = <0>;
 887                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 888                         clock-names = "SSPCLK", "apb_pclk";
 889                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 890                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 891                         dma-names = "rx", "tx";
 892                         power-domains = <&pm_domains DOMAIN_VAPE>;
 893                 };
 894
 895                 spi@80003000 {
 896                         compatible = "arm,pl022", "arm,primecell";
 897                         reg = <0x80003000 0x1000>;
 898                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 899                         #address-cells = <1>;
 900                         #size-cells = <0>;
 901                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 902                         clock-names = "SSPCLK", "apb_pclk";
 903                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 904                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 905                         dma-names = "rx", "tx";
 906                         power-domains = <&pm_domains DOMAIN_VAPE>;
 907                 };
 908
 909                 spi@8011a000 {
 910                         compatible = "arm,pl022", "arm,primecell";
 911                         reg = <0x8011a000 0x1000>;
 912                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 913                         #address-cells = <1>;
 914                         #size-cells = <0>;
 915                         /* Same clock wired to kernel and pclk */
 916                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 917                         clock-names = "SSPCLK", "apb_pclk";
 918                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 919                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 920                         dma-names = "rx", "tx";
 921                         power-domains = <&pm_domains DOMAIN_VAPE>;
 922                 };
 923
 924                 spi@80112000 {
 925                         compatible = "arm,pl022", "arm,primecell";
 926                         reg = <0x80112000 0x1000>;
 927                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 928                         #address-cells = <1>;
 929                         #size-cells = <0>;
 930                         /* Same clock wired to kernel and pclk */
 931                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 932                         clock-names = "SSPCLK", "apb_pclk";
 933                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 934                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 935                         dma-names = "rx", "tx";
 936                         power-domains = <&pm_domains DOMAIN_VAPE>;
 937                 };
 938
 939                 spi@80111000 {
 940                         compatible = "arm,pl022", "arm,primecell";
 941                         reg = <0x80111000 0x1000>;
 942                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 943                         #address-cells = <1>;
 944                         #size-cells = <0>;
 945                         /* Same clock wired to kernel and pclk */
 946                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 947                         clock-names = "SSPCLK", "apb_pclk";
 948                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 949                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 950                         dma-names = "rx", "tx";
 951                         power-domains = <&pm_domains DOMAIN_VAPE>;
 952                 };
 953
 954                 spi@80129000 {
 955                         compatible = "arm,pl022", "arm,primecell";
 956                         reg = <0x80129000 0x1000>;
 957                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 958                         #address-cells = <1>;
 959                         #size-cells = <0>;
 960                         /* Same clock wired to kernel and pclk */
 961                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 962                         clock-names = "SSPCLK", "apb_pclk";
 963                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 964                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 965                         dma-names = "rx", "tx";
 966                         power-domains = <&pm_domains DOMAIN_VAPE>;
 967                 };
 968
 969                 ux500_serial0: uart@80120000 {
 970                         compatible = "arm,pl011", "arm,primecell";
 971                         reg = <0x80120000 0x1000>;
 972                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 973
 974                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 975                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 976                         dma-names = "rx", "tx";
 977
 978                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 979                         clock-names = "uart", "apb_pclk";
 980
 981                         status = "disabled";
 982                 };
 983
 984                 ux500_serial1: uart@80121000 {
 985                         compatible = "arm,pl011", "arm,primecell";
 986                         reg = <0x80121000 0x1000>;
 987                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 988
 989                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 990                                <&dma 12 0 0x0>; /* Logical - MemToDev */
 991                         dma-names = "rx", "tx";
 992
 993                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
 994                         clock-names = "uart", "apb_pclk";
 995
 996                         status = "disabled";
 997                 };
 998
 999                 ux500_serial2: uart@80007000 {
1000                         compatible = "arm,pl011", "arm,primecell";
1001                         reg = <0x80007000 0x1000>;
1002                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1003
1004                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1005                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1006                         dma-names = "rx", "tx";
1007
1008                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1009                         clock-names = "uart", "apb_pclk";
1010
1011                         status = "disabled";
1012                 };
1013
1014                 sdi0_per1@80126000 {
1015                         compatible = "arm,pl18x", "arm,primecell";
1016                         reg = <0x80126000 0x1000>;
1017                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1018
1019                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1020                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1021                         dma-names = "rx", "tx";
1022
1023                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1024                         clock-names = "sdi", "apb_pclk";
1025                         power-domains = <&pm_domains DOMAIN_VAPE>;
1026
1027                         status = "disabled";
1028                 };
1029
1030                 sdi1_per2@80118000 {
1031                         compatible = "arm,pl18x", "arm,primecell";
1032                         reg = <0x80118000 0x1000>;
1033                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1034
1035                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1036                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1037                         dma-names = "rx", "tx";
1038
1039                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1040                         clock-names = "sdi", "apb_pclk";
1041                         power-domains = <&pm_domains DOMAIN_VAPE>;
1042
1043                         status = "disabled";
1044                 };
1045
1046                 sdi2_per3@80005000 {
1047                         compatible = "arm,pl18x", "arm,primecell";
1048                         reg = <0x80005000 0x1000>;
1049                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1050
1051                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1052                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1053                         dma-names = "rx", "tx";
1054
1055                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1056                         clock-names = "sdi", "apb_pclk";
1057                         power-domains = <&pm_domains DOMAIN_VAPE>;
1058
1059                         status = "disabled";
1060                 };
1061
1062                 sdi3_per2@80119000 {
1063                         compatible = "arm,pl18x", "arm,primecell";
1064                         reg = <0x80119000 0x1000>;
1065                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1066
1067                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1068                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1069                         dma-names = "rx", "tx";
1070
1071                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1072                         clock-names = "sdi", "apb_pclk";
1073                         power-domains = <&pm_domains DOMAIN_VAPE>;
1074
1075                         status = "disabled";
1076                 };
1077
1078                 sdi4_per2@80114000 {
1079                         compatible = "arm,pl18x", "arm,primecell";
1080                         reg = <0x80114000 0x1000>;
1081                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1082
1083                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1084                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1085                         dma-names = "rx", "tx";
1086
1087                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1088                         clock-names = "sdi", "apb_pclk";
1089                         power-domains = <&pm_domains DOMAIN_VAPE>;
1090
1091                         status = "disabled";
1092                 };
1093
1094                 sdi5_per3@80008000 {
1095                         compatible = "arm,pl18x", "arm,primecell";
1096                         reg = <0x80008000 0x1000>;
1097                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1098
1099                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1100                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1101                         dma-names = "rx", "tx";
1102
1103                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1104                         clock-names = "sdi", "apb_pclk";
1105                         power-domains = <&pm_domains DOMAIN_VAPE>;
1106
1107                         status = "disabled";
1108                 };
1109
1110                 sound {
1111                         compatible = "stericsson,snd-soc-mop500";
1112                         stericsson,cpu-dai = <&msp1 &msp3>;
1113                         stericsson,audio-codec = <&codec>;
1114                         clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
1115                         clock-names = "sysclk", "ulpclk", "intclk";
1116                 };
1117
1118                 msp0: msp@80123000 {
1119                         compatible = "stericsson,ux500-msp-i2s";
1120                         reg = <0x80123000 0x1000>;
1121                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1122                         v-ape-supply = <&db8500_vape_reg>;
1123
1124                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1125                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1126                         dma-names = "rx", "tx";
1127
1128                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1129                         clock-names = "msp", "apb_pclk";
1130
1131                         status = "disabled";
1132                 };
1133
1134                 msp1: msp@80124000 {
1135                         compatible = "stericsson,ux500-msp-i2s";
1136                         reg = <0x80124000 0x1000>;
1137                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1138                         v-ape-supply = <&db8500_vape_reg>;
1139
1140                         /* This DMA channel only exist on DB8500 v1 */
1141                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1142                         dma-names = "tx";
1143
1144                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1145                         clock-names = "msp", "apb_pclk";
1146
1147                         status = "disabled";
1148                 };
1149
1150                 // HDMI sound
1151                 msp2: msp@80117000 {
1152                         compatible = "stericsson,ux500-msp-i2s";
1153                         reg = <0x80117000 0x1000>;
1154                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1155                         v-ape-supply = <&db8500_vape_reg>;
1156
1157                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1158                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1159                                                     HighPrio - Fixed */
1160                         dma-names = "rx", "tx";
1161
1162                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1163                         clock-names = "msp", "apb_pclk";
1164
1165                         status = "disabled";
1166                 };
1167
1168                 msp3: msp@80125000 {
1169                         compatible = "stericsson,ux500-msp-i2s";
1170                         reg = <0x80125000 0x1000>;
1171                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1172                         v-ape-supply = <&db8500_vape_reg>;
1173
1174                         /* This DMA channel only exist on DB8500 v2 */
1175                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1176                         dma-names = "rx";
1177
1178                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1179                         clock-names = "msp", "apb_pclk";
1180
1181                         status = "disabled";
1182                 };
1183
1184                 external-bus@50000000 {
1185                         compatible = "simple-bus";
1186                         reg = <0x50000000 0x4000000>;
1187                         #address-cells = <1>;
1188                         #size-cells = <1>;
1189                         ranges = <0 0x50000000 0x4000000>;
1190                         status = "disabled";
1191                 };
1192
1193                 gpu@a0300000 {
1194                         /*
1195                          * This block is referred to as "Smart Graphics Adapter SGA500"
1196                          * in documentation but is in practice a pretty straight-forward
1197                          * MALI-400 GPU block.
1198                          */
1199                         compatible = "stericsson,db8500-mali", "arm,mali-400";
1200                         reg = <0xa0300000 0x10000>;
1201                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1206                         interrupt-names = "gp",
1207                                           "gpmmu",
1208                                           "pp0",
1209                                           "ppmmu0",
1210                                           "combined";
1211                         clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1212                         clock-names = "bus", "core";
1213                         mali-supply = <&db8500_sga_reg>;
1214                         power-domains = <&pm_domains DOMAIN_VAPE>;
1215                 };
1216
1217                 mcde@a0350000 {
1218                         compatible = "ste,mcde";
1219                         reg = <0xa0350000 0x1000>;
1220                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1221                         epod-supply = <&db8500_b2r2_mcde_reg>;
1222                         vana-supply = <&ab8500_ldo_ana_reg>;
1223                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1224                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1225                                  <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1226                         clock-names = "mcde", "lcd", "hdmi";
1227                         #address-cells = <1>;
1228                         #size-cells = <1>;
1229                         ranges;
1230                         status = "disabled";
1231
1232                         dsi0: dsi@a0351000 {
1233                                 compatible = "ste,mcde-dsi";
1234                                 reg = <0xa0351000 0x1000>;
1235                                 vana-supply = <&ab8500_ldo_ana_reg>;
1236                                 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1237                                 clock-names = "hs", "lp";
1238                                 #address-cells = <1>;
1239                                 #size-cells = <0>;
1240                         };
1241                         dsi1: dsi@a0352000 {
1242                                 compatible = "ste,mcde-dsi";
1243                                 reg = <0xa0352000 0x1000>;
1244                                 vana-supply = <&ab8500_ldo_ana_reg>;
1245                                 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1246                                 clock-names = "hs", "lp";
1247                                 #address-cells = <1>;
1248                                 #size-cells = <0>;
1249                         };
1250                         dsi2: dsi@a0353000 {
1251                                 compatible = "ste,mcde-dsi";
1252                                 reg = <0xa0353000 0x1000>;
1253                                 vana-supply = <&ab8500_ldo_ana_reg>;
1254                                 /* This DSI port only has the Low Power / Energy Save clock */
1255                                 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1256                                 clock-names = "lp";
1257                                 #address-cells = <1>;
1258                                 #size-cells = <0>;
1259                         };
1260                 };
1261
1262                 cryp@a03cb000 {
1263                         compatible = "stericsson,ux500-cryp";
1264                         reg = <0xa03cb000 0x1000>;
1265                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1266
1267                         v-ape-supply = <&db8500_vape_reg>;
1268                         clocks = <&prcc_pclk 6 1>;
1269                 };
1270
1271                 hash@a03c2000 {
1272                         compatible = "stericsson,ux500-hash";
1273                         reg = <0xa03c2000 0x1000>;
1274
1275                         v-ape-supply = <&db8500_vape_reg>;
1276                         clocks = <&prcc_pclk 6 2>;
1277                 };
1278         };
1279 };