arch/arm/boot/dts/socfpga_cyclone5.dts

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /dts-v1/;
  19 /include/ "socfpga.dtsi"
  20
  21 / {
  22         model = "Altera SOCFPGA Cyclone V";
  23         compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  24
  25         chosen {
  26                 bootargs = "console=ttyS0,57600";
  27         };
  28
  29         memory {
  30                 name = "memory";
  31                 device_type = "memory";
  32                 reg = <0x0 0x40000000>; /* 1GB */
  33         };
  34
  35         aliases {
  36                 /* this allow the ethaddr uboot environmnet variable contents
  37                  * to be added to the gmac1 device tree blob.
  38                  */
  39                 ethernet0 = &gmac1;
  40         };
  41
  42         soc {
  43                 clkmgr@ffd04000 {
  44                         clocks {
  45                                 osc1 {
  46                                         clock-frequency = <25000000>;
  47                                 };
  48                         };
  49                 };
  50
  51                 ethernet@ff702000 {
  52                         phy-mode = "rgmii";
  53                         phy-addr = <0xffffffff>; /* probe for phy addr */
  54                         status = "okay";
  55                 };
  56
  57                 timer0@ffc08000 {
  58                         clock-frequency = <100000000>;
  59                 };
  60
  61                 timer1@ffc09000 {
  62                         clock-frequency = <100000000>;
  63                 };
  64
  65                 timer2@ffd00000 {
  66                         clock-frequency = <25000000>;
  67                 };
  68
  69                 timer3@ffd01000 {
  70                         clock-frequency = <25000000>;
  71                 };
  72
  73                 serial0@ffc02000 {
  74                         clock-frequency = <100000000>;
  75                 };
  76
  77                 serial1@ffc03000 {
  78                         clock-frequency = <100000000>;
  79                 };
  80
  81                 sysmgr@ffd08000 {
  82                         cpu1-start-addr = <0xffd080c4>;
  83                 };
  84         };
  85 };