arch/arm/boot/dts/socfpga_arria10.dtsi

   1 /*
   2  * Copyright Altera Corporation (C) 2014. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "skeleton.dtsi"
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
  20
  21 / {
  22         #address-cells = <1>;
  23         #size-cells = <1>;
  24
  25         aliases {
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 enable-method = "altr,socfpga-a10-smp";
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a9";
  37                         device_type = "cpu";
  38                         reg = <0>;
  39                         next-level-cache = <&L2>;
  40                 };
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a9";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                 };
  47         };
  48
  49         intc: intc@ffffd000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0xffffd000 0x1000>,
  54                       <0xffffc100 0x100>;
  55         };
  56
  57         soc {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 compatible = "simple-bus";
  61                 device_type = "soc";
  62                 interrupt-parent = <&intc>;
  63                 ranges;
  64
  65                 amba {
  66                         compatible = "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         ranges;
  70
  71                         pdma: pdma@ffda1000 {
  72                                 compatible = "arm,pl330", "arm,primecell";
  73                                 reg = <0xffda1000 0x1000>;
  74                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  75                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  76                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  77                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  78                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  79                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  80                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  81                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  82                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  83                                 #dma-cells = <1>;
  84                                 #dma-channels = <8>;
  85                                 #dma-requests = <32>;
  86                                 clocks = <&l4_main_clk>;
  87                                 clock-names = "apb_pclk";
  88                         };
  89                 };
  90
  91                 clkmgr@ffd04000 {
  92                                 compatible = "altr,clk-mgr";
  93                                 reg = <0xffd04000 0x1000>;
  94
  95                                 clocks {
  96                                         #address-cells = <1>;
  97                                         #size-cells = <0>;
  98
  99                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 100                                                 #clock-cells = <0>;
 101                                                 compatible = "fixed-clock";
 102                                         };
 103
 104                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
 105                                                 #clock-cells = <0>;
 106                                                 compatible = "fixed-clock";
 107                                         };
 108
 109                                         f2s_free_clk: f2s_free_clk {
 110                                                 #clock-cells = <0>;
 111                                                 compatible = "fixed-clock";
 112                                         };
 113
 114                                         osc1: osc1 {
 115                                                 #clock-cells = <0>;
 116                                                 compatible = "fixed-clock";
 117                                         };
 118
 119                                         main_pll: main_pll {
 120                                                 #address-cells = <1>;
 121                                                 #size-cells = <0>;
 122                                                 #clock-cells = <0>;
 123                                                 compatible = "altr,socfpga-a10-pll-clock";
 124                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 125                                                          <&f2s_free_clk>;
 126                                                 reg = <0x40>;
 127
 128                                                 main_mpu_base_clk: main_mpu_base_clk {
 129                                                         #clock-cells = <0>;
 130                                                         compatible = "altr,socfpga-a10-perip-clk";
 131                                                         clocks = <&main_pll>;
 132                                                         div-reg = <0x140 0 11>;
 133                                                 };
 134
 135                                                 main_noc_base_clk: main_noc_base_clk {
 136                                                         #clock-cells = <0>;
 137                                                         compatible = "altr,socfpga-a10-perip-clk";
 138                                                         clocks = <&main_pll>;
 139                                                         div-reg = <0x144 0 11>;
 140                                                 };
 141
 142                                                 main_emaca_clk: main_emaca_clk {
 143                                                         #clock-cells = <0>;
 144                                                         compatible = "altr,socfpga-a10-perip-clk";
 145                                                         clocks = <&main_pll>;
 146                                                         reg = <0x68>;
 147                                                 };
 148
 149                                                 main_emacb_clk: main_emacb_clk {
 150                                                         #clock-cells = <0>;
 151                                                         compatible = "altr,socfpga-a10-perip-clk";
 152                                                         clocks = <&main_pll>;
 153                                                         reg = <0x6C>;
 154                                                 };
 155
 156                                                 main_emac_ptp_clk: main_emac_ptp_clk {
 157                                                         #clock-cells = <0>;
 158                                                         compatible = "altr,socfpga-a10-perip-clk";
 159                                                         clocks = <&main_pll>;
 160                                                         reg = <0x70>;
 161                                                 };
 162
 163                                                 main_gpio_db_clk: main_gpio_db_clk {
 164                                                         #clock-cells = <0>;
 165                                                         compatible = "altr,socfpga-a10-perip-clk";
 166                                                         clocks = <&main_pll>;
 167                                                         reg = <0x74>;
 168                                                 };
 169
 170                                                 main_sdmmc_clk: main_sdmmc_clk {
 171                                                         #clock-cells = <0>;
 172                                                         compatible = "altr,socfpga-a10-perip-clk"
 173 ;
 174                                                         clocks = <&main_pll>;
 175                                                         reg = <0x78>;
 176                                                 };
 177
 178                                                 main_s2f_usr0_clk: main_s2f_usr0_clk {
 179                                                         #clock-cells = <0>;
 180                                                         compatible = "altr,socfpga-a10-perip-clk";
 181                                                         clocks = <&main_pll>;
 182                                                         reg = <0x7C>;
 183                                                 };
 184
 185                                                 main_s2f_usr1_clk: main_s2f_usr1_clk {
 186                                                         #clock-cells = <0>;
 187                                                         compatible = "altr,socfpga-a10-perip-clk";
 188                                                         clocks = <&main_pll>;
 189                                                         reg = <0x80>;
 190                                                 };
 191
 192                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
 193                                                         #clock-cells = <0>;
 194                                                         compatible = "altr,socfpga-a10-perip-clk";
 195                                                         clocks = <&main_pll>;
 196                                                         reg = <0x84>;
 197                                                 };
 198
 199                                                 main_periph_ref_clk: main_periph_ref_clk {
 200                                                         #clock-cells = <0>;
 201                                                         compatible = "altr,socfpga-a10-perip-clk";
 202                                                         clocks = <&main_pll>;
 203                                                         reg = <0x9C>;
 204                                                 };
 205                                         };
 206
 207                                         periph_pll: periph_pll {
 208                                                 #address-cells = <1>;
 209                                                 #size-cells = <0>;
 210                                                 #clock-cells = <0>;
 211                                                 compatible = "altr,socfpga-a10-pll-clock";
 212                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 213                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 214                                                 reg = <0xC0>;
 215
 216                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 217                                                         #clock-cells = <0>;
 218                                                         compatible = "altr,socfpga-a10-perip-clk";
 219                                                         clocks = <&periph_pll>;
 220                                                         div-reg = <0x140 16 11>;
 221                                                 };
 222
 223                                                 peri_noc_base_clk: peri_noc_base_clk {
 224                                                         #clock-cells = <0>;
 225                                                         compatible = "altr,socfpga-a10-perip-clk";
 226                                                         clocks = <&periph_pll>;
 227                                                         div-reg = <0x144 16 11>;
 228                                                 };
 229
 230                                                 peri_emaca_clk: peri_emaca_clk {
 231                                                         #clock-cells = <0>;
 232                                                         compatible = "altr,socfpga-a10-perip-clk";
 233                                                         clocks = <&periph_pll>;
 234                                                         reg = <0xE8>;
 235                                                 };
 236
 237                                                 peri_emacb_clk: peri_emacb_clk {
 238                                                         #clock-cells = <0>;
 239                                                         compatible = "altr,socfpga-a10-perip-clk";
 240                                                         clocks = <&periph_pll>;
 241                                                         reg = <0xEC>;
 242                                                 };
 243
 244                                                 peri_emac_ptp_clk: peri_emac_ptp_clk {
 245                                                         #clock-cells = <0>;
 246                                                         compatible = "altr,socfpga-a10-perip-clk";
 247                                                         clocks = <&periph_pll>;
 248                                                         reg = <0xF0>;
 249                                                 };
 250
 251                                                 peri_gpio_db_clk: peri_gpio_db_clk {
 252                                                         #clock-cells = <0>;
 253                                                         compatible = "altr,socfpga-a10-perip-clk";
 254                                                         clocks = <&periph_pll>;
 255                                                         reg = <0xF4>;
 256                                                 };
 257
 258                                                 peri_sdmmc_clk: peri_sdmmc_clk {
 259                                                         #clock-cells = <0>;
 260                                                         compatible = "altr,socfpga-a10-perip-clk";
 261                                                         clocks = <&periph_pll>;
 262                                                         reg = <0xF8>;
 263                                                 };
 264
 265                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
 266                                                         #clock-cells = <0>;
 267                                                         compatible = "altr,socfpga-a10-perip-clk";
 268                                                         clocks = <&periph_pll>;
 269                                                         reg = <0xFC>;
 270                                                 };
 271
 272                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
 273                                                         #clock-cells = <0>;
 274                                                         compatible = "altr,socfpga-a10-perip-clk";
 275                                                         clocks = <&periph_pll>;
 276                                                         reg = <0x100>;
 277                                                 };
 278
 279                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
 280                                                         #clock-cells = <0>;
 281                                                         compatible = "altr,socfpga-a10-perip-clk";
 282                                                         clocks = <&periph_pll>;
 283                                                         reg = <0x104>;
 284                                                 };
 285                                         };
 286
 287                                         mpu_free_clk: mpu_free_clk {
 288                                                 #clock-cells = <0>;
 289                                                 compatible = "altr,socfpga-a10-perip-clk";
 290                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 291                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 292                                                          <&f2s_free_clk>;
 293                                                 reg = <0x60>;
 294                                         };
 295
 296                                         noc_free_clk: noc_free_clk {
 297                                                 #clock-cells = <0>;
 298                                                 compatible = "altr,socfpga-a10-perip-clk";
 299                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 300                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 301                                                          <&f2s_free_clk>;
 302                                                 reg = <0x64>;
 303                                         };
 304
 305                                         s2f_user1_free_clk: s2f_user1_free_clk {
 306                                                 #clock-cells = <0>;
 307                                                 compatible = "altr,socfpga-a10-perip-clk";
 308                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 309                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 310                                                          <&f2s_free_clk>;
 311                                                 reg = <0x104>;
 312                                         };
 313
 314                                         sdmmc_free_clk: sdmmc_free_clk {
 315                                                 #clock-cells = <0>;
 316                                                 compatible = "altr,socfpga-a10-perip-clk";
 317                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 318                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 319                                                          <&f2s_free_clk>;
 320                                                 fixed-divider = <4>;
 321                                                 reg = <0xF8>;
 322                                         };
 323
 324                                         l4_sys_free_clk: l4_sys_free_clk {
 325                                                 #clock-cells = <0>;
 326                                                 compatible = "altr,socfpga-a10-perip-clk";
 327                                                 clocks = <&noc_free_clk>;
 328                                                 fixed-divider = <4>;
 329                                         };
 330
 331                                         l4_main_clk: l4_main_clk {
 332                                                 #clock-cells = <0>;
 333                                                 compatible = "altr,socfpga-a10-gate-clk";
 334                                                 clocks = <&noc_free_clk>;
 335                                                 div-reg = <0xA8 0 2>;
 336                                                 clk-gate = <0x48 1>;
 337                                         };
 338
 339                                         l4_mp_clk: l4_mp_clk {
 340                                                 #clock-cells = <0>;
 341                                                 compatible = "altr,socfpga-a10-gate-clk";
 342                                                 clocks = <&noc_free_clk>;
 343                                                 div-reg = <0xA8 8 2>;
 344                                                 clk-gate = <0x48 2>;
 345                                         };
 346
 347                                         l4_sp_clk: l4_sp_clk {
 348                                                 #clock-cells = <0>;
 349                                                 compatible = "altr,socfpga-a10-gate-clk";
 350                                                 clocks = <&noc_free_clk>;
 351                                                 div-reg = <0xA8 16 2>;
 352                                                 clk-gate = <0x48 3>;
 353                                         };
 354
 355                                         mpu_periph_clk: mpu_periph_clk {
 356                                                 #clock-cells = <0>;
 357                                                 compatible = "altr,socfpga-a10-gate-clk";
 358                                                 clocks = <&mpu_free_clk>;
 359                                                 fixed-divider = <4>;
 360                                                 clk-gate = <0x48 0>;
 361                                         };
 362
 363                                         sdmmc_clk: sdmmc_clk {
 364                                                 #clock-cells = <0>;
 365                                                 compatible = "altr,socfpga-a10-gate-clk";
 366                                                 clocks = <&sdmmc_free_clk>;
 367                                                 clk-gate = <0xC8 5>;
 368                                                 clk-phase = <0 135>;
 369                                         };
 370
 371                                         qspi_clk: qspi_clk {
 372                                                 #clock-cells = <0>;
 373                                                 compatible = "altr,socfpga-a10-gate-clk";
 374                                                 clocks = <&l4_main_clk>;
 375                                                 clk-gate = <0xC8 11>;
 376                                         };
 377
 378                                         nand_clk: nand_clk {
 379                                                 #clock-cells = <0>;
 380                                                 compatible = "altr,socfpga-a10-gate-clk";
 381                                                 clocks = <&l4_mp_clk>;
 382                                                 clk-gate = <0xC8 10>;
 383                                         };
 384
 385                                         spi_m_clk: spi_m_clk {
 386                                                 #clock-cells = <0>;
 387                                                 compatible = "altr,socfpga-a10-gate-clk";
 388                                                 clocks = <&l4_main_clk>;
 389                                                 clk-gate = <0xC8 9>;
 390                                         };
 391
 392                                         usb_clk: usb_clk {
 393                                                 #clock-cells = <0>;
 394                                                 compatible = "altr,socfpga-a10-gate-clk";
 395                                                 clocks = <&l4_mp_clk>;
 396                                                 clk-gate = <0xC8 8>;
 397                                         };
 398
 399                                         s2f_usr1_clk: s2f_usr1_clk {
 400                                                 #clock-cells = <0>;
 401                                                 compatible = "altr,socfpga-a10-gate-clk";
 402                                                 clocks = <&peri_s2f_usr1_clk>;
 403                                                 clk-gate = <0xC8 6>;
 404                                         };
 405                                 };
 406                 };
 407
 408                 gmac0: ethernet@ff800000 {
 409                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 410                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 411                         reg = <0xff800000 0x2000>;
 412                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 413                         interrupt-names = "macirq";
 414                         /* Filled in by bootloader */
 415                         mac-address = [00 00 00 00 00 00];
 416                         snps,multicast-filter-bins = <256>;
 417                         snps,perfect-filter-entries = <128>;
 418                         tx-fifo-depth = <4096>;
 419                         rx-fifo-depth = <16384>;
 420                         clocks = <&l4_mp_clk>;
 421                         clock-names = "stmmaceth";
 422                         resets = <&rst EMAC0_RESET>;
 423                         reset-names = "stmmaceth";
 424                         status = "disabled";
 425                 };
 426
 427                 gmac1: ethernet@ff802000 {
 428                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 429                         altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 430                         reg = <0xff802000 0x2000>;
 431                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 432                         interrupt-names = "macirq";
 433                         /* Filled in by bootloader */
 434                         mac-address = [00 00 00 00 00 00];
 435                         snps,multicast-filter-bins = <256>;
 436                         snps,perfect-filter-entries = <128>;
 437                         tx-fifo-depth = <4096>;
 438                         rx-fifo-depth = <16384>;
 439                         clocks = <&l4_mp_clk>;
 440                         clock-names = "stmmaceth";
 441                         resets = <&rst EMAC1_RESET>;
 442                         reset-names = "stmmaceth";
 443                         status = "disabled";
 444                 };
 445
 446                 gmac2: ethernet@ff804000 {
 447                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 448                         altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
 449                         reg = <0xff804000 0x2000>;
 450                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 451                         interrupt-names = "macirq";
 452                         /* Filled in by bootloader */
 453                         mac-address = [00 00 00 00 00 00];
 454                         snps,multicast-filter-bins = <256>;
 455                         snps,perfect-filter-entries = <128>;
 456                         tx-fifo-depth = <4096>;
 457                         rx-fifo-depth = <16384>;
 458                         clocks = <&l4_mp_clk>;
 459                         clock-names = "stmmaceth";
 460                         status = "disabled";
 461                 };
 462
 463                 gpio0: gpio@ffc02900 {
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         compatible = "snps,dw-apb-gpio";
 467                         reg = <0xffc02900 0x100>;
 468                         status = "disabled";
 469
 470                         porta: gpio-controller@0 {
 471                                 compatible = "snps,dw-apb-gpio-port";
 472                                 gpio-controller;
 473                                 #gpio-cells = <2>;
 474                                 snps,nr-gpios = <29>;
 475                                 reg = <0>;
 476                                 interrupt-controller;
 477                                 #interrupt-cells = <2>;
 478                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 479                         };
 480                 };
 481
 482                 gpio1: gpio@ffc02a00 {
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         compatible = "snps,dw-apb-gpio";
 486                         reg = <0xffc02a00 0x100>;
 487                         status = "disabled";
 488
 489                         portb: gpio-controller@0 {
 490                                 compatible = "snps,dw-apb-gpio-port";
 491                                 gpio-controller;
 492                                 #gpio-cells = <2>;
 493                                 snps,nr-gpios = <29>;
 494                                 reg = <0>;
 495                                 interrupt-controller;
 496                                 #interrupt-cells = <2>;
 497                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 498                         };
 499                 };
 500
 501                 gpio2: gpio@ffc02b00 {
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         compatible = "snps,dw-apb-gpio";
 505                         reg = <0xffc02b00 0x100>;
 506                         status = "disabled";
 507
 508                         portc: gpio-controller@0 {
 509                                 compatible = "snps,dw-apb-gpio-port";
 510                                 gpio-controller;
 511                                 #gpio-cells = <2>;
 512                                 snps,nr-gpios = <27>;
 513                                 reg = <0>;
 514                                 interrupt-controller;
 515                                 #interrupt-cells = <2>;
 516                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 517                         };
 518                 };
 519
 520                 i2c0: i2c@ffc02200 {
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         compatible = "snps,designware-i2c";
 524                         reg = <0xffc02200 0x100>;
 525                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&l4_sp_clk>;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c1: i2c@ffc02300 {
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         compatible = "snps,designware-i2c";
 534                         reg = <0xffc02300 0x100>;
 535                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&l4_sp_clk>;
 537                         status = "disabled";
 538                 };
 539
 540                 i2c2: i2c@ffc02400 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         compatible = "snps,designware-i2c";
 544                         reg = <0xffc02400 0x100>;
 545                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&l4_sp_clk>;
 547                         status = "disabled";
 548                 };
 549
 550                 i2c3: i2c@ffc02500 {
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                         compatible = "snps,designware-i2c";
 554                         reg = <0xffc02500 0x100>;
 555                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&l4_sp_clk>;
 557                         status = "disabled";
 558                 };
 559
 560                 i2c4: i2c@ffc02600 {
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         compatible = "snps,designware-i2c";
 564                         reg = <0xffc02600 0x100>;
 565                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&l4_sp_clk>;
 567                         status = "disabled";
 568                 };
 569
 570                 sdr: sdr@ffc25000 {
 571                         compatible = "syscon";
 572                         reg = <0xffcfb100 0x80>;
 573                 };
 574
 575                 sdramedac {
 576                         compatible = "altr,sdram-edac-a10";
 577                         altr,sdr-syscon = <&sdr>;
 578                         interrupts = <0 2 4>, <0 0 4>;
 579                 };
 580
 581                 L2: l2-cache@fffff000 {
 582                         compatible = "arm,pl310-cache";
 583                         reg = <0xfffff000 0x1000>;
 584                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 585                         cache-unified;
 586                         cache-level = <2>;
 587                 };
 588
 589                 mmc: dwmmc0@ff808000 {
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                         compatible = "altr,socfpga-dw-mshc";
 593                         reg = <0xff808000 0x1000>;
 594                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 595                         fifo-depth = <0x400>;
 596                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 597                         clock-names = "biu", "ciu";
 598                         status = "disabled";
 599                 };
 600
 601                 ocram: sram@ffe00000 {
 602                         compatible = "mmio-sram";
 603                         reg = <0xffe00000 0x40000>;
 604                 };
 605
 606                 eccmgr: eccmgr@ffd06000 {
 607                         compatible = "altr,socfpga-a10-ecc-manager";
 608                         altr,sysmgr-syscon = <&sysmgr>;
 609                         #address-cells = <1>;
 610                         #size-cells = <1>;
 611                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 612                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 613                         ranges;
 614
 615                         l2-ecc@ffd06010 {
 616                                 compatible = "altr,socfpga-a10-l2-ecc";
 617                                 reg = <0xffd06010 0x4>;
 618                         };
 619
 620                         ocram-ecc@ff8c3000 {
 621                                 compatible = "altr,socfpga-a10-ocram-ecc";
 622                                 reg = <0xff8c3000 0x400>;
 623                         };
 624                 };
 625
 626                 rst: rstmgr@ffd05000 {
 627                         #reset-cells = <1>;
 628                         compatible = "altr,rst-mgr";
 629                         reg = <0xffd05000 0x100>;
 630                         altr,modrst-offset = <0x20>;
 631                 };
 632
 633                 scu: snoop-control-unit@ffffc000 {
 634                         compatible = "arm,cortex-a9-scu";
 635                         reg = <0xffffc000 0x100>;
 636                 };
 637
 638                 sysmgr: sysmgr@ffd06000 {
 639                         compatible = "altr,sys-mgr", "syscon";
 640                         reg = <0xffd06000 0x300>;
 641                         cpu1-start-addr = <0xffd06230>;
 642                 };
 643
 644                 /* Local timer */
 645                 timer@ffffc600 {
 646                         compatible = "arm,cortex-a9-twd-timer";
 647                         reg = <0xffffc600 0x100>;
 648                         interrupts = <1 13 0xf04>;
 649                         clocks = <&mpu_periph_clk>;
 650                 };
 651
 652                 timer0: timer0@ffc02700 {
 653                         compatible = "snps,dw-apb-timer";
 654                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 655                         reg = <0xffc02700 0x100>;
 656                         clocks = <&l4_sp_clk>;
 657                         clock-names = "timer";
 658                 };
 659
 660                 timer1: timer1@ffc02800 {
 661                         compatible = "snps,dw-apb-timer";
 662                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 663                         reg = <0xffc02800 0x100>;
 664                         clocks = <&l4_sp_clk>;
 665                         clock-names = "timer";
 666                 };
 667
 668                 timer2: timer2@ffd00000 {
 669                         compatible = "snps,dw-apb-timer";
 670                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 671                         reg = <0xffd00000 0x100>;
 672                         clocks = <&l4_sys_free_clk>;
 673                         clock-names = "timer";
 674                 };
 675
 676                 timer3: timer3@ffd00100 {
 677                         compatible = "snps,dw-apb-timer";
 678                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 679                         reg = <0xffd01000 0x100>;
 680                         clocks = <&l4_sys_free_clk>;
 681                         clock-names = "timer";
 682                 };
 683
 684                 uart0: serial0@ffc02000 {
 685                         compatible = "snps,dw-apb-uart";
 686                         reg = <0xffc02000 0x100>;
 687                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 688                         reg-shift = <2>;
 689                         reg-io-width = <4>;
 690                         clocks = <&l4_sp_clk>;
 691                         status = "disabled";
 692                 };
 693
 694                 uart1: serial1@ffc02100 {
 695                         compatible = "snps,dw-apb-uart";
 696                         reg = <0xffc02100 0x100>;
 697                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 698                         reg-shift = <2>;
 699                         reg-io-width = <4>;
 700                         clocks = <&l4_sp_clk>;
 701                         status = "disabled";
 702                 };
 703
 704                 usbphy0: usbphy@0 {
 705                         #phy-cells = <0>;
 706                         compatible = "usb-nop-xceiv";
 707                         status = "okay";
 708                 };
 709
 710                 usb0: usb@ffb00000 {
 711                         compatible = "snps,dwc2";
 712                         reg = <0xffb00000 0xffff>;
 713                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 714                         clocks = <&usb_clk>;
 715                         clock-names = "otg";
 716                         resets = <&rst USB0_RESET>;
 717                         reset-names = "dwc2";
 718                         phys = <&usbphy0>;
 719                         phy-names = "usb2-phy";
 720                         status = "disabled";
 721                 };
 722
 723                 usb1: usb@ffb40000 {
 724                         compatible = "snps,dwc2";
 725                         reg = <0xffb40000 0xffff>;
 726                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&usb_clk>;
 728                         clock-names = "otg";
 729                         resets = <&rst USB1_RESET>;
 730                         reset-names = "dwc2";
 731                         phys = <&usbphy0>;
 732                         phy-names = "usb2-phy";
 733                         status = "disabled";
 734                 };
 735
 736                 watchdog0: watchdog@ffd00200 {
 737                         compatible = "snps,dw-wdt";
 738                         reg = <0xffd00200 0x100>;
 739                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 740                         clocks = <&l4_sys_free_clk>;
 741                         status = "disabled";
 742                 };
 743
 744                 watchdog1: watchdog@ffd00300 {
 745                         compatible = "snps,dw-wdt";
 746                         reg = <0xffd00300 0x100>;
 747                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&l4_sys_free_clk>;
 749                         status = "disabled";
 750                 };
 751         };
 752 };