arch/arm/boot/dts/socfpga_arria10.dtsi

   1 /*
   2  * Copyright Altera Corporation (C) 2014. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "altr,socfpga-a10-smp";
  28
  29                 cpu@0 {
  30                         compatible = "arm,cortex-a9";
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         next-level-cache = <&L2>;
  34                 };
  35                 cpu@1 {
  36                         compatible = "arm,cortex-a9";
  37                         device_type = "cpu";
  38                         reg = <1>;
  39                         next-level-cache = <&L2>;
  40                 };
  41         };
  42
  43         intc: intc@ffffd000 {
  44                 compatible = "arm,cortex-a9-gic";
  45                 #interrupt-cells = <3>;
  46                 interrupt-controller;
  47                 reg = <0xffffd000 0x1000>,
  48                       <0xffffc100 0x100>;
  49         };
  50
  51         soc {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 compatible = "simple-bus";
  55                 device_type = "soc";
  56                 interrupt-parent = <&intc>;
  57                 ranges;
  58
  59                 amba {
  60                         compatible = "simple-bus";
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         ranges;
  64
  65                         pdma: pdma@ffda1000 {
  66                                 compatible = "arm,pl330", "arm,primecell";
  67                                 reg = <0xffda1000 0x1000>;
  68                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  69                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  70                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  71                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  72                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  73                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  74                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  75                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  76                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  77                                 #dma-cells = <1>;
  78                                 #dma-channels = <8>;
  79                                 #dma-requests = <32>;
  80                                 clocks = <&l4_main_clk>;
  81                                 clock-names = "apb_pclk";
  82                         };
  83                 };
  84
  85                 base_fpga_region {
  86                         #address-cells = <0x1>;
  87                         #size-cells = <0x1>;
  88
  89                         compatible = "fpga-region";
  90                         fpga-mgr = <&fpga_mgr>;
  91                 };
  92
  93                 clkmgr@ffd04000 {
  94                                 compatible = "altr,clk-mgr";
  95                                 reg = <0xffd04000 0x1000>;
  96
  97                                 clocks {
  98                                         #address-cells = <1>;
  99                                         #size-cells = <0>;
 100
 101                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 102                                                 #clock-cells = <0>;
 103                                                 compatible = "fixed-clock";
 104                                         };
 105
 106                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
 107                                                 #clock-cells = <0>;
 108                                                 compatible = "fixed-clock";
 109                                         };
 110
 111                                         f2s_free_clk: f2s_free_clk {
 112                                                 #clock-cells = <0>;
 113                                                 compatible = "fixed-clock";
 114                                         };
 115
 116                                         osc1: osc1 {
 117                                                 #clock-cells = <0>;
 118                                                 compatible = "fixed-clock";
 119                                         };
 120
 121                                         main_pll: main_pll@40 {
 122                                                 #address-cells = <1>;
 123                                                 #size-cells = <0>;
 124                                                 #clock-cells = <0>;
 125                                                 compatible = "altr,socfpga-a10-pll-clock";
 126                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 127                                                          <&f2s_free_clk>;
 128                                                 reg = <0x40>;
 129
 130                                                 main_mpu_base_clk: main_mpu_base_clk {
 131                                                         #clock-cells = <0>;
 132                                                         compatible = "altr,socfpga-a10-perip-clk";
 133                                                         clocks = <&main_pll>;
 134                                                         div-reg = <0x140 0 11>;
 135                                                 };
 136
 137                                                 main_noc_base_clk: main_noc_base_clk {
 138                                                         #clock-cells = <0>;
 139                                                         compatible = "altr,socfpga-a10-perip-clk";
 140                                                         clocks = <&main_pll>;
 141                                                         div-reg = <0x144 0 11>;
 142                                                 };
 143
 144                                                 main_emaca_clk: main_emaca_clk@68 {
 145                                                         #clock-cells = <0>;
 146                                                         compatible = "altr,socfpga-a10-perip-clk";
 147                                                         clocks = <&main_pll>;
 148                                                         reg = <0x68>;
 149                                                 };
 150
 151                                                 main_emacb_clk: main_emacb_clk@6c {
 152                                                         #clock-cells = <0>;
 153                                                         compatible = "altr,socfpga-a10-perip-clk";
 154                                                         clocks = <&main_pll>;
 155                                                         reg = <0x6C>;
 156                                                 };
 157
 158                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
 159                                                         #clock-cells = <0>;
 160                                                         compatible = "altr,socfpga-a10-perip-clk";
 161                                                         clocks = <&main_pll>;
 162                                                         reg = <0x70>;
 163                                                 };
 164
 165                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
 166                                                         #clock-cells = <0>;
 167                                                         compatible = "altr,socfpga-a10-perip-clk";
 168                                                         clocks = <&main_pll>;
 169                                                         reg = <0x74>;
 170                                                 };
 171
 172                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
 173                                                         #clock-cells = <0>;
 174                                                         compatible = "altr,socfpga-a10-perip-clk"
 175 ;
 176                                                         clocks = <&main_pll>;
 177                                                         reg = <0x78>;
 178                                                 };
 179
 180                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
 181                                                         #clock-cells = <0>;
 182                                                         compatible = "altr,socfpga-a10-perip-clk";
 183                                                         clocks = <&main_pll>;
 184                                                         reg = <0x7C>;
 185                                                 };
 186
 187                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
 188                                                         #clock-cells = <0>;
 189                                                         compatible = "altr,socfpga-a10-perip-clk";
 190                                                         clocks = <&main_pll>;
 191                                                         reg = <0x80>;
 192                                                 };
 193
 194                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
 195                                                         #clock-cells = <0>;
 196                                                         compatible = "altr,socfpga-a10-perip-clk";
 197                                                         clocks = <&main_pll>;
 198                                                         reg = <0x84>;
 199                                                 };
 200
 201                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
 202                                                         #clock-cells = <0>;
 203                                                         compatible = "altr,socfpga-a10-perip-clk";
 204                                                         clocks = <&main_pll>;
 205                                                         reg = <0x9C>;
 206                                                 };
 207                                         };
 208
 209                                         periph_pll: periph_pll@c0 {
 210                                                 #address-cells = <1>;
 211                                                 #size-cells = <0>;
 212                                                 #clock-cells = <0>;
 213                                                 compatible = "altr,socfpga-a10-pll-clock";
 214                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 215                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 216                                                 reg = <0xC0>;
 217
 218                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 219                                                         #clock-cells = <0>;
 220                                                         compatible = "altr,socfpga-a10-perip-clk";
 221                                                         clocks = <&periph_pll>;
 222                                                         div-reg = <0x140 16 11>;
 223                                                 };
 224
 225                                                 peri_noc_base_clk: peri_noc_base_clk {
 226                                                         #clock-cells = <0>;
 227                                                         compatible = "altr,socfpga-a10-perip-clk";
 228                                                         clocks = <&periph_pll>;
 229                                                         div-reg = <0x144 16 11>;
 230                                                 };
 231
 232                                                 peri_emaca_clk: peri_emaca_clk@e8 {
 233                                                         #clock-cells = <0>;
 234                                                         compatible = "altr,socfpga-a10-perip-clk";
 235                                                         clocks = <&periph_pll>;
 236                                                         reg = <0xE8>;
 237                                                 };
 238
 239                                                 peri_emacb_clk: peri_emacb_clk@ec {
 240                                                         #clock-cells = <0>;
 241                                                         compatible = "altr,socfpga-a10-perip-clk";
 242                                                         clocks = <&periph_pll>;
 243                                                         reg = <0xEC>;
 244                                                 };
 245
 246                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
 247                                                         #clock-cells = <0>;
 248                                                         compatible = "altr,socfpga-a10-perip-clk";
 249                                                         clocks = <&periph_pll>;
 250                                                         reg = <0xF0>;
 251                                                 };
 252
 253                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
 254                                                         #clock-cells = <0>;
 255                                                         compatible = "altr,socfpga-a10-perip-clk";
 256                                                         clocks = <&periph_pll>;
 257                                                         reg = <0xF4>;
 258                                                 };
 259
 260                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
 261                                                         #clock-cells = <0>;
 262                                                         compatible = "altr,socfpga-a10-perip-clk";
 263                                                         clocks = <&periph_pll>;
 264                                                         reg = <0xF8>;
 265                                                 };
 266
 267                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
 268                                                         #clock-cells = <0>;
 269                                                         compatible = "altr,socfpga-a10-perip-clk";
 270                                                         clocks = <&periph_pll>;
 271                                                         reg = <0xFC>;
 272                                                 };
 273
 274                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
 275                                                         #clock-cells = <0>;
 276                                                         compatible = "altr,socfpga-a10-perip-clk";
 277                                                         clocks = <&periph_pll>;
 278                                                         reg = <0x100>;
 279                                                 };
 280
 281                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
 282                                                         #clock-cells = <0>;
 283                                                         compatible = "altr,socfpga-a10-perip-clk";
 284                                                         clocks = <&periph_pll>;
 285                                                         reg = <0x104>;
 286                                                 };
 287                                         };
 288
 289                                         mpu_free_clk: mpu_free_clk@60 {
 290                                                 #clock-cells = <0>;
 291                                                 compatible = "altr,socfpga-a10-perip-clk";
 292                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 293                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 294                                                          <&f2s_free_clk>;
 295                                                 reg = <0x60>;
 296                                         };
 297
 298                                         noc_free_clk: noc_free_clk@64 {
 299                                                 #clock-cells = <0>;
 300                                                 compatible = "altr,socfpga-a10-perip-clk";
 301                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 302                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 303                                                          <&f2s_free_clk>;
 304                                                 reg = <0x64>;
 305                                         };
 306
 307                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
 308                                                 #clock-cells = <0>;
 309                                                 compatible = "altr,socfpga-a10-perip-clk";
 310                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 311                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 312                                                          <&f2s_free_clk>;
 313                                                 reg = <0x104>;
 314                                         };
 315
 316                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
 317                                                 #clock-cells = <0>;
 318                                                 compatible = "altr,socfpga-a10-perip-clk";
 319                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 320                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 321                                                          <&f2s_free_clk>;
 322                                                 fixed-divider = <4>;
 323                                                 reg = <0xF8>;
 324                                         };
 325
 326                                         l4_sys_free_clk: l4_sys_free_clk {
 327                                                 #clock-cells = <0>;
 328                                                 compatible = "altr,socfpga-a10-perip-clk";
 329                                                 clocks = <&noc_free_clk>;
 330                                                 fixed-divider = <4>;
 331                                         };
 332
 333                                         l4_main_clk: l4_main_clk {
 334                                                 #clock-cells = <0>;
 335                                                 compatible = "altr,socfpga-a10-gate-clk";
 336                                                 clocks = <&noc_free_clk>;
 337                                                 div-reg = <0xA8 0 2>;
 338                                                 clk-gate = <0x48 1>;
 339                                         };
 340
 341                                         l4_mp_clk: l4_mp_clk {
 342                                                 #clock-cells = <0>;
 343                                                 compatible = "altr,socfpga-a10-gate-clk";
 344                                                 clocks = <&noc_free_clk>;
 345                                                 div-reg = <0xA8 8 2>;
 346                                                 clk-gate = <0x48 2>;
 347                                         };
 348
 349                                         l4_sp_clk: l4_sp_clk {
 350                                                 #clock-cells = <0>;
 351                                                 compatible = "altr,socfpga-a10-gate-clk";
 352                                                 clocks = <&noc_free_clk>;
 353                                                 div-reg = <0xA8 16 2>;
 354                                                 clk-gate = <0x48 3>;
 355                                         };
 356
 357                                         mpu_periph_clk: mpu_periph_clk {
 358                                                 #clock-cells = <0>;
 359                                                 compatible = "altr,socfpga-a10-gate-clk";
 360                                                 clocks = <&mpu_free_clk>;
 361                                                 fixed-divider = <4>;
 362                                                 clk-gate = <0x48 0>;
 363                                         };
 364
 365                                         sdmmc_clk: sdmmc_clk {
 366                                                 #clock-cells = <0>;
 367                                                 compatible = "altr,socfpga-a10-gate-clk";
 368                                                 clocks = <&sdmmc_free_clk>;
 369                                                 clk-gate = <0xC8 5>;
 370                                                 clk-phase = <0 135>;
 371                                         };
 372
 373                                         qspi_clk: qspi_clk {
 374                                                 #clock-cells = <0>;
 375                                                 compatible = "altr,socfpga-a10-gate-clk";
 376                                                 clocks = <&l4_main_clk>;
 377                                                 clk-gate = <0xC8 11>;
 378                                         };
 379
 380                                         nand_x_clk: nand_x_clk {
 381                                                 #clock-cells = <0>;
 382                                                 compatible = "altr,socfpga-a10-gate-clk";
 383                                                 clocks = <&l4_mp_clk>;
 384                                                 clk-gate = <0xC8 10>;
 385                                         };
 386
 387                                         nand_ecc_clk: nand_ecc_clk {
 388                                                 #clock-cells = <0>;
 389                                                 compatible = "altr,socfpga-a10-gate-clk";
 390                                                 clocks = <&nand_x_clk>;
 391                                                 clk-gate = <0xC8 10>;
 392                                         };
 393
 394                                         nand_clk: nand_clk {
 395                                                 #clock-cells = <0>;
 396                                                 compatible = "altr,socfpga-a10-gate-clk";
 397                                                 clocks = <&nand_x_clk>;
 398                                                 fixed-divider = <4>;
 399                                                 clk-gate = <0xC8 10>;
 400                                         };
 401
 402                                         spi_m_clk: spi_m_clk {
 403                                                 #clock-cells = <0>;
 404                                                 compatible = "altr,socfpga-a10-gate-clk";
 405                                                 clocks = <&l4_main_clk>;
 406                                                 clk-gate = <0xC8 9>;
 407                                         };
 408
 409                                         usb_clk: usb_clk {
 410                                                 #clock-cells = <0>;
 411                                                 compatible = "altr,socfpga-a10-gate-clk";
 412                                                 clocks = <&l4_mp_clk>;
 413                                                 clk-gate = <0xC8 8>;
 414                                         };
 415
 416                                         s2f_usr1_clk: s2f_usr1_clk {
 417                                                 #clock-cells = <0>;
 418                                                 compatible = "altr,socfpga-a10-gate-clk";
 419                                                 clocks = <&peri_s2f_usr1_clk>;
 420                                                 clk-gate = <0xC8 6>;
 421                                         };
 422                                 };
 423                 };
 424
 425                 socfpga_axi_setup: stmmac-axi-config {
 426                         snps,wr_osr_lmt = <0xf>;
 427                         snps,rd_osr_lmt = <0xf>;
 428                         snps,blen = <0 0 0 0 16 0 0>;
 429                 };
 430
 431                 gmac0: ethernet@ff800000 {
 432                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 433                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 434                         reg = <0xff800000 0x2000>;
 435                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 436                         interrupt-names = "macirq";
 437                         /* Filled in by bootloader */
 438                         mac-address = [00 00 00 00 00 00];
 439                         snps,multicast-filter-bins = <256>;
 440                         snps,perfect-filter-entries = <128>;
 441                         tx-fifo-depth = <4096>;
 442                         rx-fifo-depth = <16384>;
 443                         clocks = <&l4_mp_clk>;
 444                         clock-names = "stmmaceth";
 445                         resets = <&rst EMAC0_RESET>;
 446                         reset-names = "stmmaceth";
 447                         snps,axi-config = <&socfpga_axi_setup>;
 448                         status = "disabled";
 449                 };
 450
 451                 gmac1: ethernet@ff802000 {
 452                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 453                         altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 454                         reg = <0xff802000 0x2000>;
 455                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 456                         interrupt-names = "macirq";
 457                         /* Filled in by bootloader */
 458                         mac-address = [00 00 00 00 00 00];
 459                         snps,multicast-filter-bins = <256>;
 460                         snps,perfect-filter-entries = <128>;
 461                         tx-fifo-depth = <4096>;
 462                         rx-fifo-depth = <16384>;
 463                         clocks = <&l4_mp_clk>;
 464                         clock-names = "stmmaceth";
 465                         resets = <&rst EMAC1_RESET>;
 466                         reset-names = "stmmaceth";
 467                         snps,axi-config = <&socfpga_axi_setup>;
 468                         status = "disabled";
 469                 };
 470
 471                 gmac2: ethernet@ff804000 {
 472                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 473                         altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
 474                         reg = <0xff804000 0x2000>;
 475                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 476                         interrupt-names = "macirq";
 477                         /* Filled in by bootloader */
 478                         mac-address = [00 00 00 00 00 00];
 479                         snps,multicast-filter-bins = <256>;
 480                         snps,perfect-filter-entries = <128>;
 481                         tx-fifo-depth = <4096>;
 482                         rx-fifo-depth = <16384>;
 483                         clocks = <&l4_mp_clk>;
 484                         clock-names = "stmmaceth";
 485                         snps,axi-config = <&socfpga_axi_setup>;
 486                         status = "disabled";
 487                 };
 488
 489                 gpio0: gpio@ffc02900 {
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         compatible = "snps,dw-apb-gpio";
 493                         reg = <0xffc02900 0x100>;
 494                         status = "disabled";
 495
 496                         porta: gpio-controller@0 {
 497                                 compatible = "snps,dw-apb-gpio-port";
 498                                 gpio-controller;
 499                                 #gpio-cells = <2>;
 500                                 snps,nr-gpios = <29>;
 501                                 reg = <0>;
 502                                 interrupt-controller;
 503                                 #interrupt-cells = <2>;
 504                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 505                         };
 506                 };
 507
 508                 gpio1: gpio@ffc02a00 {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         compatible = "snps,dw-apb-gpio";
 512                         reg = <0xffc02a00 0x100>;
 513                         status = "disabled";
 514
 515                         portb: gpio-controller@0 {
 516                                 compatible = "snps,dw-apb-gpio-port";
 517                                 gpio-controller;
 518                                 #gpio-cells = <2>;
 519                                 snps,nr-gpios = <29>;
 520                                 reg = <0>;
 521                                 interrupt-controller;
 522                                 #interrupt-cells = <2>;
 523                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 524                         };
 525                 };
 526
 527                 gpio2: gpio@ffc02b00 {
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         compatible = "snps,dw-apb-gpio";
 531                         reg = <0xffc02b00 0x100>;
 532                         status = "disabled";
 533
 534                         portc: gpio-controller@0 {
 535                                 compatible = "snps,dw-apb-gpio-port";
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 snps,nr-gpios = <27>;
 539                                 reg = <0>;
 540                                 interrupt-controller;
 541                                 #interrupt-cells = <2>;
 542                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 543                         };
 544                 };
 545
 546                 fpga_mgr: fpga-mgr@ffd03000 {
 547                         compatible = "altr,socfpga-a10-fpga-mgr";
 548                         reg = <0xffd03000 0x100
 549                                0xffcfe400 0x20>;
 550                         clocks = <&l4_mp_clk>;
 551                         resets = <&rst FPGAMGR_RESET>;
 552                         reset-names = "fpgamgr";
 553                 };
 554
 555                 i2c0: i2c@ffc02200 {
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         compatible = "snps,designware-i2c";
 559                         reg = <0xffc02200 0x100>;
 560                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 561                         clocks = <&l4_sp_clk>;
 562                         status = "disabled";
 563                 };
 564
 565                 i2c1: i2c@ffc02300 {
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         compatible = "snps,designware-i2c";
 569                         reg = <0xffc02300 0x100>;
 570                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&l4_sp_clk>;
 572                         status = "disabled";
 573                 };
 574
 575                 i2c2: i2c@ffc02400 {
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         compatible = "snps,designware-i2c";
 579                         reg = <0xffc02400 0x100>;
 580                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 581                         clocks = <&l4_sp_clk>;
 582                         status = "disabled";
 583                 };
 584
 585                 i2c3: i2c@ffc02500 {
 586                         #address-cells = <1>;
 587                         #size-cells = <0>;
 588                         compatible = "snps,designware-i2c";
 589                         reg = <0xffc02500 0x100>;
 590                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&l4_sp_clk>;
 592                         status = "disabled";
 593                 };
 594
 595                 i2c4: i2c@ffc02600 {
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         compatible = "snps,designware-i2c";
 599                         reg = <0xffc02600 0x100>;
 600                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&l4_sp_clk>;
 602                         status = "disabled";
 603                 };
 604
 605                 spi0: spi@ffda4000 {
 606                         compatible = "snps,dw-apb-ssi";
 607                         #address-cells = <1>;
 608                         #size-cells = <0>;
 609                         reg = <0xffda4000 0x100>;
 610                         interrupts = <0 101 4>;
 611                         num-cs = <4>;
 612                         /*32bit_access;*/
 613                         clocks = <&spi_m_clk>;
 614                         status = "disabled";
 615                 };
 616
 617                 spi1: spi@ffda5000 {
 618                         compatible = "snps,dw-apb-ssi";
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         reg = <0xffda5000 0x100>;
 622                         interrupts = <0 102 4>;
 623                         num-cs = <4>;
 624                         /*32bit_access;*/
 625                         tx-dma-channel = <&pdma 16>;
 626                         rx-dma-channel = <&pdma 17>;
 627                         clocks = <&spi_m_clk>;
 628                         status = "disabled";
 629                 };
 630
 631                 sdr: sdr@ffcfb100 {
 632                         compatible = "altr,sdr-ctl", "syscon";
 633                         reg = <0xffcfb100 0x80>;
 634                 };
 635
 636                 L2: l2-cache@fffff000 {
 637                         compatible = "arm,pl310-cache";
 638                         reg = <0xfffff000 0x1000>;
 639                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 640                         cache-unified;
 641                         cache-level = <2>;
 642                         prefetch-data = <1>;
 643                         prefetch-instr = <1>;
 644                         arm,shared-override;
 645                 };
 646
 647                 mmc: dwmmc0@ff808000 {
 648                         #address-cells = <1>;
 649                         #size-cells = <0>;
 650                         compatible = "altr,socfpga-dw-mshc";
 651                         reg = <0xff808000 0x1000>;
 652                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 653                         fifo-depth = <0x400>;
 654                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 655                         clock-names = "biu", "ciu";
 656                         status = "disabled";
 657                 };
 658
 659                 nand: nand@ffb90000 {
 660                         #address-cells = <1>;
 661                         #size-cells = <1>;
 662                         compatible = "altr,socfpga-denali-nand";
 663                         reg = <0xffb90000 0x72000>,
 664                               <0xffb80000 0x10000>;
 665                         reg-names = "nand_data", "denali_reg";
 666                         interrupts = <0 99 4>;
 667                         dma-mask = <0xffffffff>;
 668                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 669                         clock-names = "nand", "nand_x", "ecc";
 670                         status = "disabled";
 671                 };
 672
 673                 ocram: sram@ffe00000 {
 674                         compatible = "mmio-sram";
 675                         reg = <0xffe00000 0x40000>;
 676                 };
 677
 678                 eccmgr: eccmgr {
 679                         compatible = "altr,socfpga-a10-ecc-manager";
 680                         altr,sysmgr-syscon = <&sysmgr>;
 681                         #address-cells = <1>;
 682                         #size-cells = <1>;
 683                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 685                         interrupt-controller;
 686                         #interrupt-cells = <2>;
 687                         ranges;
 688
 689                         sdramedac {
 690                                 compatible = "altr,sdram-edac-a10";
 691                                 altr,sdr-syscon = <&sdr>;
 692                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
 693                                              <49 IRQ_TYPE_LEVEL_HIGH>;
 694                         };
 695
 696                         l2-ecc@ffd06010 {
 697                                 compatible = "altr,socfpga-a10-l2-ecc";
 698                                 reg = <0xffd06010 0x4>;
 699                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
 700                                              <32 IRQ_TYPE_LEVEL_HIGH>;
 701                         };
 702
 703                         ocram-ecc@ff8c3000 {
 704                                 compatible = "altr,socfpga-a10-ocram-ecc";
 705                                 reg = <0xff8c3000 0x400>;
 706                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 707                                              <33 IRQ_TYPE_LEVEL_HIGH>;
 708                         };
 709
 710                         emac0-rx-ecc@ff8c0800 {
 711                                 compatible = "altr,socfpga-eth-mac-ecc";
 712                                 reg = <0xff8c0800 0x400>;
 713                                 altr,ecc-parent = <&gmac0>;
 714                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 715                                              <36 IRQ_TYPE_LEVEL_HIGH>;
 716                         };
 717
 718                         emac0-tx-ecc@ff8c0c00 {
 719                                 compatible = "altr,socfpga-eth-mac-ecc";
 720                                 reg = <0xff8c0c00 0x400>;
 721                                 altr,ecc-parent = <&gmac0>;
 722                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 723                                              <37 IRQ_TYPE_LEVEL_HIGH>;
 724                         };
 725
 726                         dma-ecc@ff8c8000 {
 727                                 compatible = "altr,socfpga-dma-ecc";
 728                                 reg = <0xff8c8000 0x400>;
 729                                 altr,ecc-parent = <&pdma>;
 730                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
 731                                              <42 IRQ_TYPE_LEVEL_HIGH>;
 732                         };
 733
 734                         usb0-ecc@ff8c8800 {
 735                                 compatible = "altr,socfpga-usb-ecc";
 736                                 reg = <0xff8c8800 0x400>;
 737                                 altr,ecc-parent = <&usb0>;
 738                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
 739                                              <34 IRQ_TYPE_LEVEL_HIGH>;
 740                         };
 741                 };
 742
 743                 qspi: spi@ff809000 {
 744                         compatible = "cdns,qspi-nor";
 745                         #address-cells = <1>;
 746                         #size-cells = <0>;
 747                         reg = <0xff809000 0x100>,
 748                               <0xffa00000 0x100000>;
 749                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 750                         cdns,fifo-depth = <128>;
 751                         cdns,fifo-width = <4>;
 752                         cdns,trigger-address = <0x00000000>;
 753                         clocks = <&qspi_clk>;
 754                         status = "disabled";
 755                 };
 756
 757                 rst: rstmgr@ffd05000 {
 758                         #reset-cells = <1>;
 759                         compatible = "altr,rst-mgr";
 760                         reg = <0xffd05000 0x100>;
 761                         altr,modrst-offset = <0x20>;
 762                 };
 763
 764                 scu: snoop-control-unit@ffffc000 {
 765                         compatible = "arm,cortex-a9-scu";
 766                         reg = <0xffffc000 0x100>;
 767                 };
 768
 769                 sysmgr: sysmgr@ffd06000 {
 770                         compatible = "altr,sys-mgr", "syscon";
 771                         reg = <0xffd06000 0x300>;
 772                         cpu1-start-addr = <0xffd06230>;
 773                 };
 774
 775                 /* Local timer */
 776                 timer@ffffc600 {
 777                         compatible = "arm,cortex-a9-twd-timer";
 778                         reg = <0xffffc600 0x100>;
 779                         interrupts = <1 13 0xf01>;
 780                         clocks = <&mpu_periph_clk>;
 781                 };
 782
 783                 timer0: timer0@ffc02700 {
 784                         compatible = "snps,dw-apb-timer";
 785                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 786                         reg = <0xffc02700 0x100>;
 787                         clocks = <&l4_sp_clk>;
 788                         clock-names = "timer";
 789                         resets = <&rst SPTIMER0_RESET>;
 790                         reset-names = "timer";
 791                 };
 792
 793                 timer1: timer1@ffc02800 {
 794                         compatible = "snps,dw-apb-timer";
 795                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 796                         reg = <0xffc02800 0x100>;
 797                         clocks = <&l4_sp_clk>;
 798                         clock-names = "timer";
 799                         resets = <&rst SPTIMER1_RESET>;
 800                         reset-names = "timer";
 801                 };
 802
 803                 timer2: timer2@ffd00000 {
 804                         compatible = "snps,dw-apb-timer";
 805                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 806                         reg = <0xffd00000 0x100>;
 807                         clocks = <&l4_sys_free_clk>;
 808                         clock-names = "timer";
 809                         resets = <&rst L4SYSTIMER0_RESET>;
 810                         reset-names = "timer";
 811                 };
 812
 813                 timer3: timer3@ffd00100 {
 814                         compatible = "snps,dw-apb-timer";
 815                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 816                         reg = <0xffd01000 0x100>;
 817                         clocks = <&l4_sys_free_clk>;
 818                         clock-names = "timer";
 819                         resets = <&rst L4SYSTIMER1_RESET>;
 820                         reset-names = "timer";
 821                 };
 822
 823                 uart0: serial0@ffc02000 {
 824                         compatible = "snps,dw-apb-uart";
 825                         reg = <0xffc02000 0x100>;
 826                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 827                         reg-shift = <2>;
 828                         reg-io-width = <4>;
 829                         clocks = <&l4_sp_clk>;
 830                         status = "disabled";
 831                 };
 832
 833                 uart1: serial1@ffc02100 {
 834                         compatible = "snps,dw-apb-uart";
 835                         reg = <0xffc02100 0x100>;
 836                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 837                         reg-shift = <2>;
 838                         reg-io-width = <4>;
 839                         clocks = <&l4_sp_clk>;
 840                         status = "disabled";
 841                 };
 842
 843                 usbphy0: usbphy {
 844                         #phy-cells = <0>;
 845                         compatible = "usb-nop-xceiv";
 846                         status = "okay";
 847                 };
 848
 849                 usb0: usb@ffb00000 {
 850                         compatible = "snps,dwc2";
 851                         reg = <0xffb00000 0xffff>;
 852                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 853                         clocks = <&usb_clk>;
 854                         clock-names = "otg";
 855                         resets = <&rst USB0_RESET>;
 856                         reset-names = "dwc2";
 857                         phys = <&usbphy0>;
 858                         phy-names = "usb2-phy";
 859                         status = "disabled";
 860                 };
 861
 862                 usb1: usb@ffb40000 {
 863                         compatible = "snps,dwc2";
 864                         reg = <0xffb40000 0xffff>;
 865                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 866                         clocks = <&usb_clk>;
 867                         clock-names = "otg";
 868                         resets = <&rst USB1_RESET>;
 869                         reset-names = "dwc2";
 870                         phys = <&usbphy0>;
 871                         phy-names = "usb2-phy";
 872                         status = "disabled";
 873                 };
 874
 875                 watchdog0: watchdog@ffd00200 {
 876                         compatible = "snps,dw-wdt";
 877                         reg = <0xffd00200 0x100>;
 878                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 879                         clocks = <&l4_sys_free_clk>;
 880                         status = "disabled";
 881                 };
 882
 883                 watchdog1: watchdog@ffd00300 {
 884                         compatible = "snps,dw-wdt";
 885                         reg = <0xffd00300 0x100>;
 886                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 887                         clocks = <&l4_sys_free_clk>;
 888                         status = "disabled";
 889                 };
 890         };
 891 };