arch/arm/boot/dts/socfpga.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Altera <www.altera.com>
   4  */
   5
   6 #include <dt-bindings/reset/altr,rst-mgr.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 timer0 = &timer0;
  16                 timer1 = &timer1;
  17                 timer2 = &timer2;
  18                 timer3 = &timer3;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "altr,socfpga-smp";
  25
  26                 cpu0: cpu@0 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         reg = <0>;
  30                         next-level-cache = <&L2>;
  31                 };
  32                 cpu1: cpu@1 {
  33                         compatible = "arm,cortex-a9";
  34                         device_type = "cpu";
  35                         reg = <1>;
  36                         next-level-cache = <&L2>;
  37                 };
  38         };
  39
  40         pmu: pmu@ff111000 {
  41                 compatible = "arm,cortex-a9-pmu";
  42                 interrupt-parent = <&intc>;
  43                 interrupts = <0 176 4>, <0 177 4>;
  44                 interrupt-affinity = <&cpu0>, <&cpu1>;
  45                 reg = <0xff111000 0x1000>,
  46                       <0xff113000 0x1000>;
  47         };
  48
  49         intc: intc@fffed000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0xfffed000 0x1000>,
  54                       <0xfffec100 0x100>;
  55         };
  56
  57         soc {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 compatible = "simple-bus";
  61                 device_type = "soc";
  62                 interrupt-parent = <&intc>;
  63                 ranges;
  64
  65                 amba {
  66                         compatible = "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         ranges;
  70
  71                         pdma: pdma@ffe01000 {
  72                                 compatible = "arm,pl330", "arm,primecell";
  73                                 reg = <0xffe01000 0x1000>;
  74                                 interrupts = <0 104 4>,
  75                                              <0 105 4>,
  76                                              <0 106 4>,
  77                                              <0 107 4>,
  78                                              <0 108 4>,
  79                                              <0 109 4>,
  80                                              <0 110 4>,
  81                                              <0 111 4>;
  82                                 #dma-cells = <1>;
  83                                 #dma-channels = <8>;
  84                                 #dma-requests = <32>;
  85                                 clocks = <&l4_main_clk>;
  86                                 clock-names = "apb_pclk";
  87                                 resets = <&rst DMA_RESET>;
  88                         };
  89                 };
  90
  91                 base_fpga_region {
  92                         compatible = "fpga-region";
  93                         fpga-mgr = <&fpgamgr0>;
  94
  95                         #address-cells = <0x1>;
  96                         #size-cells = <0x1>;
  97                 };
  98
  99                 can0: can@ffc00000 {
 100                         compatible = "bosch,d_can";
 101                         reg = <0xffc00000 0x1000>;
 102                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
 103                         clocks = <&can0_clk>;
 104                         resets = <&rst CAN0_RESET>;
 105                         status = "disabled";
 106                 };
 107
 108                 can1: can@ffc01000 {
 109                         compatible = "bosch,d_can";
 110                         reg = <0xffc01000 0x1000>;
 111                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 112                         clocks = <&can1_clk>;
 113                         resets = <&rst CAN1_RESET>;
 114                         status = "disabled";
 115                 };
 116
 117                 clkmgr@ffd04000 {
 118                                 compatible = "altr,clk-mgr";
 119                                 reg = <0xffd04000 0x1000>;
 120
 121                                 clocks {
 122                                         #address-cells = <1>;
 123                                         #size-cells = <0>;
 124
 125                                         osc1: osc1 {
 126                                                 #clock-cells = <0>;
 127                                                 compatible = "fixed-clock";
 128                                         };
 129
 130                                         osc2: osc2 {
 131                                                 #clock-cells = <0>;
 132                                                 compatible = "fixed-clock";
 133                                         };
 134
 135                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 136                                                 #clock-cells = <0>;
 137                                                 compatible = "fixed-clock";
 138                                         };
 139
 140                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 141                                                 #clock-cells = <0>;
 142                                                 compatible = "fixed-clock";
 143                                         };
 144
 145                                         main_pll: main_pll@40 {
 146                                                 #address-cells = <1>;
 147                                                 #size-cells = <0>;
 148                                                 #clock-cells = <0>;
 149                                                 compatible = "altr,socfpga-pll-clock";
 150                                                 clocks = <&osc1>;
 151                                                 reg = <0x40>;
 152
 153                                                 mpuclk: mpuclk@48 {
 154                                                         #clock-cells = <0>;
 155                                                         compatible = "altr,socfpga-perip-clk";
 156                                                         clocks = <&main_pll>;
 157                                                         div-reg = <0xe0 0 9>;
 158                                                         reg = <0x48>;
 159                                                 };
 160
 161                                                 mainclk: mainclk@4c {
 162                                                         #clock-cells = <0>;
 163                                                         compatible = "altr,socfpga-perip-clk";
 164                                                         clocks = <&main_pll>;
 165                                                         div-reg = <0xe4 0 9>;
 166                                                         reg = <0x4C>;
 167                                                 };
 168
 169                                                 dbg_base_clk: dbg_base_clk@50 {
 170                                                         #clock-cells = <0>;
 171                                                         compatible = "altr,socfpga-perip-clk";
 172                                                         clocks = <&main_pll>, <&osc1>;
 173                                                         div-reg = <0xe8 0 9>;
 174                                                         reg = <0x50>;
 175                                                 };
 176
 177                                                 main_qspi_clk: main_qspi_clk@54 {
 178                                                         #clock-cells = <0>;
 179                                                         compatible = "altr,socfpga-perip-clk";
 180                                                         clocks = <&main_pll>;
 181                                                         reg = <0x54>;
 182                                                 };
 183
 184                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
 185                                                         #clock-cells = <0>;
 186                                                         compatible = "altr,socfpga-perip-clk";
 187                                                         clocks = <&main_pll>;
 188                                                         reg = <0x58>;
 189                                                 };
 190
 191                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
 192                                                         #clock-cells = <0>;
 193                                                         compatible = "altr,socfpga-perip-clk";
 194                                                         clocks = <&main_pll>;
 195                                                         reg = <0x5C>;
 196                                                 };
 197                                         };
 198
 199                                         periph_pll: periph_pll@80 {
 200                                                 #address-cells = <1>;
 201                                                 #size-cells = <0>;
 202                                                 #clock-cells = <0>;
 203                                                 compatible = "altr,socfpga-pll-clock";
 204                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 205                                                 reg = <0x80>;
 206
 207                                                 emac0_clk: emac0_clk@88 {
 208                                                         #clock-cells = <0>;
 209                                                         compatible = "altr,socfpga-perip-clk";
 210                                                         clocks = <&periph_pll>;
 211                                                         reg = <0x88>;
 212                                                 };
 213
 214                                                 emac1_clk: emac1_clk@8c {
 215                                                         #clock-cells = <0>;
 216                                                         compatible = "altr,socfpga-perip-clk";
 217                                                         clocks = <&periph_pll>;
 218                                                         reg = <0x8C>;
 219                                                 };
 220
 221                                                 per_qspi_clk: per_qsi_clk@90 {
 222                                                         #clock-cells = <0>;
 223                                                         compatible = "altr,socfpga-perip-clk";
 224                                                         clocks = <&periph_pll>;
 225                                                         reg = <0x90>;
 226                                                 };
 227
 228                                                 per_nand_mmc_clk: per_nand_mmc_clk@94 {
 229                                                         #clock-cells = <0>;
 230                                                         compatible = "altr,socfpga-perip-clk";
 231                                                         clocks = <&periph_pll>;
 232                                                         reg = <0x94>;
 233                                                 };
 234
 235                                                 per_base_clk: per_base_clk@98 {
 236                                                         #clock-cells = <0>;
 237                                                         compatible = "altr,socfpga-perip-clk";
 238                                                         clocks = <&periph_pll>;
 239                                                         reg = <0x98>;
 240                                                 };
 241
 242                                                 h2f_usr1_clk: h2f_usr1_clk@9c {
 243                                                         #clock-cells = <0>;
 244                                                         compatible = "altr,socfpga-perip-clk";
 245                                                         clocks = <&periph_pll>;
 246                                                         reg = <0x9C>;
 247                                                 };
 248                                         };
 249
 250                                         sdram_pll: sdram_pll@c0 {
 251                                                 #address-cells = <1>;
 252                                                 #size-cells = <0>;
 253                                                 #clock-cells = <0>;
 254                                                 compatible = "altr,socfpga-pll-clock";
 255                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 256                                                 reg = <0xC0>;
 257
 258                                                 ddr_dqs_clk: ddr_dqs_clk@c8 {
 259                                                         #clock-cells = <0>;
 260                                                         compatible = "altr,socfpga-perip-clk";
 261                                                         clocks = <&sdram_pll>;
 262                                                         reg = <0xC8>;
 263                                                 };
 264
 265                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
 266                                                         #clock-cells = <0>;
 267                                                         compatible = "altr,socfpga-perip-clk";
 268                                                         clocks = <&sdram_pll>;
 269                                                         reg = <0xCC>;
 270                                                 };
 271
 272                                                 ddr_dq_clk: ddr_dq_clk@d0 {
 273                                                         #clock-cells = <0>;
 274                                                         compatible = "altr,socfpga-perip-clk";
 275                                                         clocks = <&sdram_pll>;
 276                                                         reg = <0xD0>;
 277                                                 };
 278
 279                                                 h2f_usr2_clk: h2f_usr2_clk@d4 {
 280                                                         #clock-cells = <0>;
 281                                                         compatible = "altr,socfpga-perip-clk";
 282                                                         clocks = <&sdram_pll>;
 283                                                         reg = <0xD4>;
 284                                                 };
 285                                         };
 286
 287                                         mpu_periph_clk: mpu_periph_clk {
 288                                                 #clock-cells = <0>;
 289                                                 compatible = "altr,socfpga-perip-clk";
 290                                                 clocks = <&mpuclk>;
 291                                                 fixed-divider = <4>;
 292                                         };
 293
 294                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 295                                                 #clock-cells = <0>;
 296                                                 compatible = "altr,socfpga-perip-clk";
 297                                                 clocks = <&mpuclk>;
 298                                                 fixed-divider = <2>;
 299                                         };
 300
 301                                         l4_main_clk: l4_main_clk {
 302                                                 #clock-cells = <0>;
 303                                                 compatible = "altr,socfpga-gate-clk";
 304                                                 clocks = <&mainclk>;
 305                                                 clk-gate = <0x60 0>;
 306                                         };
 307
 308                                         l3_main_clk: l3_main_clk {
 309                                                 #clock-cells = <0>;
 310                                                 compatible = "altr,socfpga-perip-clk";
 311                                                 clocks = <&mainclk>;
 312                                                 fixed-divider = <1>;
 313                                         };
 314
 315                                         l3_mp_clk: l3_mp_clk {
 316                                                 #clock-cells = <0>;
 317                                                 compatible = "altr,socfpga-gate-clk";
 318                                                 clocks = <&mainclk>;
 319                                                 div-reg = <0x64 0 2>;
 320                                                 clk-gate = <0x60 1>;
 321                                         };
 322
 323                                         l3_sp_clk: l3_sp_clk {
 324                                                 #clock-cells = <0>;
 325                                                 compatible = "altr,socfpga-gate-clk";
 326                                                 clocks = <&l3_mp_clk>;
 327                                                 div-reg = <0x64 2 2>;
 328                                         };
 329
 330                                         l4_mp_clk: l4_mp_clk {
 331                                                 #clock-cells = <0>;
 332                                                 compatible = "altr,socfpga-gate-clk";
 333                                                 clocks = <&mainclk>, <&per_base_clk>;
 334                                                 div-reg = <0x64 4 3>;
 335                                                 clk-gate = <0x60 2>;
 336                                         };
 337
 338                                         l4_sp_clk: l4_sp_clk {
 339                                                 #clock-cells = <0>;
 340                                                 compatible = "altr,socfpga-gate-clk";
 341                                                 clocks = <&mainclk>, <&per_base_clk>;
 342                                                 div-reg = <0x64 7 3>;
 343                                                 clk-gate = <0x60 3>;
 344                                         };
 345
 346                                         dbg_at_clk: dbg_at_clk {
 347                                                 #clock-cells = <0>;
 348                                                 compatible = "altr,socfpga-gate-clk";
 349                                                 clocks = <&dbg_base_clk>;
 350                                                 div-reg = <0x68 0 2>;
 351                                                 clk-gate = <0x60 4>;
 352                                         };
 353
 354                                         dbg_clk: dbg_clk {
 355                                                 #clock-cells = <0>;
 356                                                 compatible = "altr,socfpga-gate-clk";
 357                                                 clocks = <&dbg_at_clk>;
 358                                                 div-reg = <0x68 2 2>;
 359                                                 clk-gate = <0x60 5>;
 360                                         };
 361
 362                                         dbg_trace_clk: dbg_trace_clk {
 363                                                 #clock-cells = <0>;
 364                                                 compatible = "altr,socfpga-gate-clk";
 365                                                 clocks = <&dbg_base_clk>;
 366                                                 div-reg = <0x6C 0 3>;
 367                                                 clk-gate = <0x60 6>;
 368                                         };
 369
 370                                         dbg_timer_clk: dbg_timer_clk {
 371                                                 #clock-cells = <0>;
 372                                                 compatible = "altr,socfpga-gate-clk";
 373                                                 clocks = <&dbg_base_clk>;
 374                                                 clk-gate = <0x60 7>;
 375                                         };
 376
 377                                         cfg_clk: cfg_clk {
 378                                                 #clock-cells = <0>;
 379                                                 compatible = "altr,socfpga-gate-clk";
 380                                                 clocks = <&cfg_h2f_usr0_clk>;
 381                                                 clk-gate = <0x60 8>;
 382                                         };
 383
 384                                         h2f_user0_clk: h2f_user0_clk {
 385                                                 #clock-cells = <0>;
 386                                                 compatible = "altr,socfpga-gate-clk";
 387                                                 clocks = <&cfg_h2f_usr0_clk>;
 388                                                 clk-gate = <0x60 9>;
 389                                         };
 390
 391                                         emac_0_clk: emac_0_clk {
 392                                                 #clock-cells = <0>;
 393                                                 compatible = "altr,socfpga-gate-clk";
 394                                                 clocks = <&emac0_clk>;
 395                                                 clk-gate = <0xa0 0>;
 396                                         };
 397
 398                                         emac_1_clk: emac_1_clk {
 399                                                 #clock-cells = <0>;
 400                                                 compatible = "altr,socfpga-gate-clk";
 401                                                 clocks = <&emac1_clk>;
 402                                                 clk-gate = <0xa0 1>;
 403                                         };
 404
 405                                         usb_mp_clk: usb_mp_clk {
 406                                                 #clock-cells = <0>;
 407                                                 compatible = "altr,socfpga-gate-clk";
 408                                                 clocks = <&per_base_clk>;
 409                                                 clk-gate = <0xa0 2>;
 410                                                 div-reg = <0xa4 0 3>;
 411                                         };
 412
 413                                         spi_m_clk: spi_m_clk {
 414                                                 #clock-cells = <0>;
 415                                                 compatible = "altr,socfpga-gate-clk";
 416                                                 clocks = <&per_base_clk>;
 417                                                 clk-gate = <0xa0 3>;
 418                                                 div-reg = <0xa4 3 3>;
 419                                         };
 420
 421                                         can0_clk: can0_clk {
 422                                                 #clock-cells = <0>;
 423                                                 compatible = "altr,socfpga-gate-clk";
 424                                                 clocks = <&per_base_clk>;
 425                                                 clk-gate = <0xa0 4>;
 426                                                 div-reg = <0xa4 6 3>;
 427                                         };
 428
 429                                         can1_clk: can1_clk {
 430                                                 #clock-cells = <0>;
 431                                                 compatible = "altr,socfpga-gate-clk";
 432                                                 clocks = <&per_base_clk>;
 433                                                 clk-gate = <0xa0 5>;
 434                                                 div-reg = <0xa4 9 3>;
 435                                         };
 436
 437                                         gpio_db_clk: gpio_db_clk {
 438                                                 #clock-cells = <0>;
 439                                                 compatible = "altr,socfpga-gate-clk";
 440                                                 clocks = <&per_base_clk>;
 441                                                 clk-gate = <0xa0 6>;
 442                                                 div-reg = <0xa8 0 24>;
 443                                         };
 444
 445                                         h2f_user1_clk: h2f_user1_clk {
 446                                                 #clock-cells = <0>;
 447                                                 compatible = "altr,socfpga-gate-clk";
 448                                                 clocks = <&h2f_usr1_clk>;
 449                                                 clk-gate = <0xa0 7>;
 450                                         };
 451
 452                                         sdmmc_clk: sdmmc_clk {
 453                                                 #clock-cells = <0>;
 454                                                 compatible = "altr,socfpga-gate-clk";
 455                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 456                                                 clk-gate = <0xa0 8>;
 457                                                 clk-phase = <0 135>;
 458                                         };
 459
 460                                         sdmmc_clk_divided: sdmmc_clk_divided {
 461                                                 #clock-cells = <0>;
 462                                                 compatible = "altr,socfpga-gate-clk";
 463                                                 clocks = <&sdmmc_clk>;
 464                                                 clk-gate = <0xa0 8>;
 465                                                 fixed-divider = <4>;
 466                                         };
 467
 468                                         nand_x_clk: nand_x_clk {
 469                                                 #clock-cells = <0>;
 470                                                 compatible = "altr,socfpga-gate-clk";
 471                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 472                                                 clk-gate = <0xa0 9>;
 473                                         };
 474
 475                                         nand_ecc_clk: nand_ecc_clk {
 476                                                 #clock-cells = <0>;
 477                                                 compatible = "altr,socfpga-gate-clk";
 478                                                 clocks = <&nand_x_clk>;
 479                                                 clk-gate = <0xa0 9>;
 480                                         };
 481
 482                                         nand_clk: nand_clk {
 483                                                 #clock-cells = <0>;
 484                                                 compatible = "altr,socfpga-gate-clk";
 485                                                 clocks = <&nand_x_clk>;
 486                                                 clk-gate = <0xa0 10>;
 487                                                 fixed-divider = <4>;
 488                                         };
 489
 490                                         qspi_clk: qspi_clk {
 491                                                 #clock-cells = <0>;
 492                                                 compatible = "altr,socfpga-gate-clk";
 493                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 494                                                 clk-gate = <0xa0 11>;
 495                                         };
 496
 497                                         ddr_dqs_clk_gate: ddr_dqs_clk_gate {
 498                                                 #clock-cells = <0>;
 499                                                 compatible = "altr,socfpga-gate-clk";
 500                                                 clocks = <&ddr_dqs_clk>;
 501                                                 clk-gate = <0xd8 0>;
 502                                         };
 503
 504                                         ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
 505                                                 #clock-cells = <0>;
 506                                                 compatible = "altr,socfpga-gate-clk";
 507                                                 clocks = <&ddr_2x_dqs_clk>;
 508                                                 clk-gate = <0xd8 1>;
 509                                         };
 510
 511                                         ddr_dq_clk_gate: ddr_dq_clk_gate {
 512                                                 #clock-cells = <0>;
 513                                                 compatible = "altr,socfpga-gate-clk";
 514                                                 clocks = <&ddr_dq_clk>;
 515                                                 clk-gate = <0xd8 2>;
 516                                         };
 517
 518                                         h2f_user2_clk: h2f_user2_clk {
 519                                                 #clock-cells = <0>;
 520                                                 compatible = "altr,socfpga-gate-clk";
 521                                                 clocks = <&h2f_usr2_clk>;
 522                                                 clk-gate = <0xd8 3>;
 523                                         };
 524
 525                                 };
 526                 };
 527
 528                 fpga_bridge0: fpga_bridge@ff400000 {
 529                         compatible = "altr,socfpga-lwhps2fpga-bridge";
 530                         reg = <0xff400000 0x100000>;
 531                         resets = <&rst LWHPS2FPGA_RESET>;
 532                         clocks = <&l4_main_clk>;
 533                 };
 534
 535                 fpga_bridge1: fpga_bridge@ff500000 {
 536                         compatible = "altr,socfpga-hps2fpga-bridge";
 537                         reg = <0xff500000 0x10000>;
 538                         resets = <&rst HPS2FPGA_RESET>;
 539                         clocks = <&l4_main_clk>;
 540                 };
 541
 542                 fpgamgr0: fpgamgr@ff706000 {
 543                         compatible = "altr,socfpga-fpga-mgr";
 544                         reg = <0xff706000 0x1000
 545                                0xffb90000 0x4>;
 546                         interrupts = <0 175 4>;
 547                 };
 548
 549                 gmac0: ethernet@ff700000 {
 550                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 551                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 552                         reg = <0xff700000 0x2000>;
 553                         interrupts = <0 115 4>;
 554                         interrupt-names = "macirq";
 555                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 556                         clocks = <&emac_0_clk>;
 557                         clock-names = "stmmaceth";
 558                         resets = <&rst EMAC0_RESET>;
 559                         reset-names = "stmmaceth";
 560                         snps,multicast-filter-bins = <256>;
 561                         snps,perfect-filter-entries = <128>;
 562                         tx-fifo-depth = <4096>;
 563                         rx-fifo-depth = <4096>;
 564                         status = "disabled";
 565                 };
 566
 567                 gmac1: ethernet@ff702000 {
 568                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 569                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 570                         reg = <0xff702000 0x2000>;
 571                         interrupts = <0 120 4>;
 572                         interrupt-names = "macirq";
 573                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 574                         clocks = <&emac_1_clk>;
 575                         clock-names = "stmmaceth";
 576                         resets = <&rst EMAC1_RESET>;
 577                         reset-names = "stmmaceth";
 578                         snps,multicast-filter-bins = <256>;
 579                         snps,perfect-filter-entries = <128>;
 580                         tx-fifo-depth = <4096>;
 581                         rx-fifo-depth = <4096>;
 582                         status = "disabled";
 583                 };
 584
 585                 gpio0: gpio@ff708000 {
 586                         #address-cells = <1>;
 587                         #size-cells = <0>;
 588                         compatible = "snps,dw-apb-gpio";
 589                         reg = <0xff708000 0x1000>;
 590                         clocks = <&l4_mp_clk>;
 591                         resets = <&rst GPIO0_RESET>;
 592                         status = "disabled";
 593
 594                         porta: gpio-controller@0 {
 595                                 compatible = "snps,dw-apb-gpio-port";
 596                                 gpio-controller;
 597                                 #gpio-cells = <2>;
 598                                 snps,nr-gpios = <29>;
 599                                 reg = <0>;
 600                                 interrupt-controller;
 601                                 #interrupt-cells = <2>;
 602                                 interrupts = <0 164 4>;
 603                         };
 604                 };
 605
 606                 gpio1: gpio@ff709000 {
 607                         #address-cells = <1>;
 608                         #size-cells = <0>;
 609                         compatible = "snps,dw-apb-gpio";
 610                         reg = <0xff709000 0x1000>;
 611                         clocks = <&l4_mp_clk>;
 612                         resets = <&rst GPIO1_RESET>;
 613                         status = "disabled";
 614
 615                         portb: gpio-controller@0 {
 616                                 compatible = "snps,dw-apb-gpio-port";
 617                                 gpio-controller;
 618                                 #gpio-cells = <2>;
 619                                 snps,nr-gpios = <29>;
 620                                 reg = <0>;
 621                                 interrupt-controller;
 622                                 #interrupt-cells = <2>;
 623                                 interrupts = <0 165 4>;
 624                         };
 625                 };
 626
 627                 gpio2: gpio@ff70a000 {
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630                         compatible = "snps,dw-apb-gpio";
 631                         reg = <0xff70a000 0x1000>;
 632                         clocks = <&l4_mp_clk>;
 633                         resets = <&rst GPIO2_RESET>;
 634                         status = "disabled";
 635
 636                         portc: gpio-controller@0 {
 637                                 compatible = "snps,dw-apb-gpio-port";
 638                                 gpio-controller;
 639                                 #gpio-cells = <2>;
 640                                 snps,nr-gpios = <27>;
 641                                 reg = <0>;
 642                                 interrupt-controller;
 643                                 #interrupt-cells = <2>;
 644                                 interrupts = <0 166 4>;
 645                         };
 646                 };
 647
 648                 i2c0: i2c@ffc04000 {
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         compatible = "snps,designware-i2c";
 652                         reg = <0xffc04000 0x1000>;
 653                         resets = <&rst I2C0_RESET>;
 654                         clocks = <&l4_sp_clk>;
 655                         interrupts = <0 158 0x4>;
 656                         status = "disabled";
 657                 };
 658
 659                 i2c1: i2c@ffc05000 {
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         compatible = "snps,designware-i2c";
 663                         reg = <0xffc05000 0x1000>;
 664                         resets = <&rst I2C1_RESET>;
 665                         clocks = <&l4_sp_clk>;
 666                         interrupts = <0 159 0x4>;
 667                         status = "disabled";
 668                 };
 669
 670                 i2c2: i2c@ffc06000 {
 671                         #address-cells = <1>;
 672                         #size-cells = <0>;
 673                         compatible = "snps,designware-i2c";
 674                         reg = <0xffc06000 0x1000>;
 675                         resets = <&rst I2C2_RESET>;
 676                         clocks = <&l4_sp_clk>;
 677                         interrupts = <0 160 0x4>;
 678                         status = "disabled";
 679                 };
 680
 681                 i2c3: i2c@ffc07000 {
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684                         compatible = "snps,designware-i2c";
 685                         reg = <0xffc07000 0x1000>;
 686                         resets = <&rst I2C3_RESET>;
 687                         clocks = <&l4_sp_clk>;
 688                         interrupts = <0 161 0x4>;
 689                         status = "disabled";
 690                 };
 691
 692                 eccmgr: eccmgr {
 693                         compatible = "altr,socfpga-ecc-manager";
 694                         #address-cells = <1>;
 695                         #size-cells = <1>;
 696                         ranges;
 697
 698                         l2-ecc@ffd08140 {
 699                                 compatible = "altr,socfpga-l2-ecc";
 700                                 reg = <0xffd08140 0x4>;
 701                                 interrupts = <0 36 1>, <0 37 1>;
 702                         };
 703
 704                         ocram-ecc@ffd08144 {
 705                                 compatible = "altr,socfpga-ocram-ecc";
 706                                 reg = <0xffd08144 0x4>;
 707                                 iram = <&ocram>;
 708                                 interrupts = <0 178 1>, <0 179 1>;
 709                         };
 710                 };
 711
 712                 L2: l2-cache@fffef000 {
 713                         compatible = "arm,pl310-cache";
 714                         reg = <0xfffef000 0x1000>;
 715                         interrupts = <0 38 0x04>;
 716                         cache-unified;
 717                         cache-level = <2>;
 718                         arm,tag-latency = <1 1 1>;
 719                         arm,data-latency = <2 1 1>;
 720                         prefetch-data = <1>;
 721                         prefetch-instr = <1>;
 722                         arm,shared-override;
 723                         arm,double-linefill = <1>;
 724                         arm,double-linefill-incr = <0>;
 725                         arm,double-linefill-wrap = <1>;
 726                         arm,prefetch-drop = <0>;
 727                         arm,prefetch-offset = <7>;
 728                 };
 729
 730                 l3regs@0xff800000 {
 731                         compatible = "altr,l3regs", "syscon";
 732                         reg = <0xff800000 0x1000>;
 733                 };
 734
 735                 mmc: dwmmc0@ff704000 {
 736                         compatible = "altr,socfpga-dw-mshc";
 737                         reg = <0xff704000 0x1000>;
 738                         interrupts = <0 139 4>;
 739                         fifo-depth = <0x400>;
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                         clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
 743                         clock-names = "biu", "ciu";
 744                         resets = <&rst SDMMC_RESET>;
 745                         status = "disabled";
 746                 };
 747
 748                 nand0: nand@ff900000 {
 749                         #address-cells = <0x1>;
 750                         #size-cells = <0x1>;
 751                         compatible = "altr,socfpga-denali-nand";
 752                         reg = <0xff900000 0x100000>,
 753                               <0xffb80000 0x10000>;
 754                         reg-names = "nand_data", "denali_reg";
 755                         interrupts = <0x0 0x90 0x4>;
 756                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 757                         clock-names = "nand", "nand_x", "ecc";
 758                         resets = <&rst NAND_RESET>;
 759                         status = "disabled";
 760                 };
 761
 762                 ocram: sram@ffff0000 {
 763                         compatible = "mmio-sram";
 764                         reg = <0xffff0000 0x10000>;
 765                 };
 766
 767                 qspi: spi@ff705000 {
 768                         compatible = "cdns,qspi-nor";
 769                         #address-cells = <1>;
 770                         #size-cells = <0>;
 771                         reg = <0xff705000 0x1000>,
 772                               <0xffa00000 0x1000>;
 773                         interrupts = <0 151 4>;
 774                         cdns,fifo-depth = <128>;
 775                         cdns,fifo-width = <4>;
 776                         cdns,trigger-address = <0x00000000>;
 777                         clocks = <&qspi_clk>;
 778                         resets = <&rst QSPI_RESET>;
 779                         status = "disabled";
 780                 };
 781
 782                 rst: rstmgr@ffd05000 {
 783                         #reset-cells = <1>;
 784                         compatible = "altr,rst-mgr";
 785                         reg = <0xffd05000 0x1000>;
 786                         altr,modrst-offset = <0x10>;
 787                 };
 788
 789                 scu: snoop-control-unit@fffec000 {
 790                         compatible = "arm,cortex-a9-scu";
 791                         reg = <0xfffec000 0x100>;
 792                 };
 793
 794                 sdr: sdr@ffc25000 {
 795                         compatible = "altr,sdr-ctl", "syscon";
 796                         reg = <0xffc25000 0x1000>;
 797                         resets = <&rst SDR_RESET>;
 798                 };
 799
 800                 sdramedac {
 801                         compatible = "altr,sdram-edac";
 802                         altr,sdr-syscon = <&sdr>;
 803                         interrupts = <0 39 4>;
 804                 };
 805
 806                 spi0: spi@fff00000 {
 807                         compatible = "snps,dw-apb-ssi";
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810                         reg = <0xfff00000 0x1000>;
 811                         interrupts = <0 154 4>;
 812                         num-cs = <4>;
 813                         clocks = <&spi_m_clk>;
 814                         resets = <&rst SPIM0_RESET>;
 815                         status = "disabled";
 816                 };
 817
 818                 spi1: spi@fff01000 {
 819                         compatible = "snps,dw-apb-ssi";
 820                         #address-cells = <1>;
 821                         #size-cells = <0>;
 822                         reg = <0xfff01000 0x1000>;
 823                         interrupts = <0 155 4>;
 824                         num-cs = <4>;
 825                         clocks = <&spi_m_clk>;
 826                         resets = <&rst SPIM1_RESET>;
 827                         status = "disabled";
 828                 };
 829
 830                 sysmgr: sysmgr@ffd08000 {
 831                         compatible = "altr,sys-mgr", "syscon";
 832                         reg = <0xffd08000 0x4000>;
 833                 };
 834
 835                 /* Local timer */
 836                 timer@fffec600 {
 837                         compatible = "arm,cortex-a9-twd-timer";
 838                         reg = <0xfffec600 0x100>;
 839                         interrupts = <1 13 0xf01>;
 840                         clocks = <&mpu_periph_clk>;
 841                 };
 842
 843                 timer0: timer0@ffc08000 {
 844                         compatible = "snps,dw-apb-timer";
 845                         interrupts = <0 167 4>;
 846                         reg = <0xffc08000 0x1000>;
 847                         clocks = <&l4_sp_clk>;
 848                         clock-names = "timer";
 849                         resets = <&rst SPTIMER0_RESET>;
 850                         reset-names = "timer";
 851                 };
 852
 853                 timer1: timer1@ffc09000 {
 854                         compatible = "snps,dw-apb-timer";
 855                         interrupts = <0 168 4>;
 856                         reg = <0xffc09000 0x1000>;
 857                         clocks = <&l4_sp_clk>;
 858                         clock-names = "timer";
 859                         resets = <&rst SPTIMER1_RESET>;
 860                         reset-names = "timer";
 861                 };
 862
 863                 timer2: timer2@ffd00000 {
 864                         compatible = "snps,dw-apb-timer";
 865                         interrupts = <0 169 4>;
 866                         reg = <0xffd00000 0x1000>;
 867                         clocks = <&osc1>;
 868                         clock-names = "timer";
 869                         resets = <&rst OSC1TIMER0_RESET>;
 870                         reset-names = "timer";
 871                 };
 872
 873                 timer3: timer3@ffd01000 {
 874                         compatible = "snps,dw-apb-timer";
 875                         interrupts = <0 170 4>;
 876                         reg = <0xffd01000 0x1000>;
 877                         clocks = <&osc1>;
 878                         clock-names = "timer";
 879                         resets = <&rst OSC1TIMER1_RESET>;
 880                         reset-names = "timer";
 881                 };
 882
 883                 uart0: serial0@ffc02000 {
 884                         compatible = "snps,dw-apb-uart";
 885                         reg = <0xffc02000 0x1000>;
 886                         interrupts = <0 162 4>;
 887                         reg-shift = <2>;
 888                         reg-io-width = <4>;
 889                         clocks = <&l4_sp_clk>;
 890                         dmas = <&pdma 28>,
 891                                <&pdma 29>;
 892                         dma-names = "tx", "rx";
 893                         resets = <&rst UART0_RESET>;
 894                 };
 895
 896                 uart1: serial1@ffc03000 {
 897                         compatible = "snps,dw-apb-uart";
 898                         reg = <0xffc03000 0x1000>;
 899                         interrupts = <0 163 4>;
 900                         reg-shift = <2>;
 901                         reg-io-width = <4>;
 902                         clocks = <&l4_sp_clk>;
 903                         dmas = <&pdma 30>,
 904                                <&pdma 31>;
 905                         dma-names = "tx", "rx";
 906                         resets = <&rst UART1_RESET>;
 907                 };
 908
 909                 usbphy0: usbphy {
 910                         #phy-cells = <0>;
 911                         compatible = "usb-nop-xceiv";
 912                         status = "okay";
 913                 };
 914
 915                 usb0: usb@ffb00000 {
 916                         compatible = "snps,dwc2";
 917                         reg = <0xffb00000 0xffff>;
 918                         interrupts = <0 125 4>;
 919                         clocks = <&usb_mp_clk>;
 920                         clock-names = "otg";
 921                         resets = <&rst USB0_RESET>;
 922                         reset-names = "dwc2";
 923                         phys = <&usbphy0>;
 924                         phy-names = "usb2-phy";
 925                         status = "disabled";
 926                 };
 927
 928                 usb1: usb@ffb40000 {
 929                         compatible = "snps,dwc2";
 930                         reg = <0xffb40000 0xffff>;
 931                         interrupts = <0 128 4>;
 932                         clocks = <&usb_mp_clk>;
 933                         clock-names = "otg";
 934                         resets = <&rst USB1_RESET>;
 935                         reset-names = "dwc2";
 936                         phys = <&usbphy0>;
 937                         phy-names = "usb2-phy";
 938                         status = "disabled";
 939                 };
 940
 941                 watchdog0: watchdog@ffd02000 {
 942                         compatible = "snps,dw-wdt";
 943                         reg = <0xffd02000 0x1000>;
 944                         interrupts = <0 171 4>;
 945                         clocks = <&osc1>;
 946                         resets = <&rst L4WD0_RESET>;
 947                         status = "disabled";
 948                 };
 949
 950                 watchdog1: watchdog@ffd03000 {
 951                         compatible = "snps,dw-wdt";
 952                         reg = <0xffd03000 0x1000>;
 953                         interrupts = <0 172 4>;
 954                         clocks = <&osc1>;
 955                         resets = <&rst L4WD1_RESET>;
 956                         status = "disabled";
 957                 };
 958         };
 959 };