arch/arm/boot/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &gmac0;
  26                 ethernet1 = &gmac1;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 timer0 = &timer0;
  30                 timer1 = &timer1;
  31                 timer2 = &timer2;
  32                 timer3 = &timer3;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         compatible = "arm,cortex-a9";
  41                         device_type = "cpu";
  42                         reg = <0>;
  43                         next-level-cache = <&L2>;
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         reg = <1>;
  49                         next-level-cache = <&L2>;
  50                 };
  51         };
  52
  53         intc: intc@fffed000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 #interrupt-cells = <3>;
  56                 interrupt-controller;
  57                 reg = <0xfffed000 0x1000>,
  58                       <0xfffec100 0x100>;
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "simple-bus";
  65                 device_type = "soc";
  66                 interrupt-parent = <&intc>;
  67                 ranges;
  68
  69                 amba {
  70                         compatible = "arm,amba-bus";
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         ranges;
  74
  75                         pdma: pdma@ffe01000 {
  76                                 compatible = "arm,pl330", "arm,primecell";
  77                                 reg = <0xffe01000 0x1000>;
  78                                 interrupts = <0 180 4>;
  79                                 #dma-cells = <1>;
  80                                 #dma-channels = <8>;
  81                                 #dma-requests = <32>;
  82                                 clocks = <&l4_main_clk>;
  83                                 clock-names = "apb_pclk";
  84                         };
  85                 };
  86
  87                 clkmgr@ffd04000 {
  88                                 compatible = "altr,clk-mgr";
  89                                 reg = <0xffd04000 0x1000>;
  90
  91                                 clocks {
  92                                         #address-cells = <1>;
  93                                         #size-cells = <0>;
  94
  95                                         osc1: osc1 {
  96                                                 #clock-cells = <0>;
  97                                                 compatible = "fixed-clock";
  98                                         };
  99
 100                                         osc2: osc2 {
 101                                                 #clock-cells = <0>;
 102                                                 compatible = "fixed-clock";
 103                                         };
 104
 105                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 106                                                 #clock-cells = <0>;
 107                                                 compatible = "fixed-clock";
 108                                         };
 109
 110                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 111                                                 #clock-cells = <0>;
 112                                                 compatible = "fixed-clock";
 113                                         };
 114
 115                                         main_pll: main_pll {
 116                                                 #address-cells = <1>;
 117                                                 #size-cells = <0>;
 118                                                 #clock-cells = <0>;
 119                                                 compatible = "altr,socfpga-pll-clock";
 120                                                 clocks = <&osc1>;
 121                                                 reg = <0x40>;
 122
 123                                                 mpuclk: mpuclk {
 124                                                         #clock-cells = <0>;
 125                                                         compatible = "altr,socfpga-perip-clk";
 126                                                         clocks = <&main_pll>;
 127                                                         fixed-divider = <2>;
 128                                                         reg = <0x48>;
 129                                                 };
 130
 131                                                 mainclk: mainclk {
 132                                                         #clock-cells = <0>;
 133                                                         compatible = "altr,socfpga-perip-clk";
 134                                                         clocks = <&main_pll>;
 135                                                         fixed-divider = <4>;
 136                                                         reg = <0x4C>;
 137                                                 };
 138
 139                                                 dbg_base_clk: dbg_base_clk {
 140                                                         #clock-cells = <0>;
 141                                                         compatible = "altr,socfpga-perip-clk";
 142                                                         clocks = <&main_pll>;
 143                                                         fixed-divider = <4>;
 144                                                         reg = <0x50>;
 145                                                 };
 146
 147                                                 main_qspi_clk: main_qspi_clk {
 148                                                         #clock-cells = <0>;
 149                                                         compatible = "altr,socfpga-perip-clk";
 150                                                         clocks = <&main_pll>;
 151                                                         reg = <0x54>;
 152                                                 };
 153
 154                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
 155                                                         #clock-cells = <0>;
 156                                                         compatible = "altr,socfpga-perip-clk";
 157                                                         clocks = <&main_pll>;
 158                                                         reg = <0x58>;
 159                                                 };
 160
 161                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
 162                                                         #clock-cells = <0>;
 163                                                         compatible = "altr,socfpga-perip-clk";
 164                                                         clocks = <&main_pll>;
 165                                                         reg = <0x5C>;
 166                                                 };
 167                                         };
 168
 169                                         periph_pll: periph_pll {
 170                                                 #address-cells = <1>;
 171                                                 #size-cells = <0>;
 172                                                 #clock-cells = <0>;
 173                                                 compatible = "altr,socfpga-pll-clock";
 174                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 175                                                 reg = <0x80>;
 176
 177                                                 emac0_clk: emac0_clk {
 178                                                         #clock-cells = <0>;
 179                                                         compatible = "altr,socfpga-perip-clk";
 180                                                         clocks = <&periph_pll>;
 181                                                         reg = <0x88>;
 182                                                 };
 183
 184                                                 emac1_clk: emac1_clk {
 185                                                         #clock-cells = <0>;
 186                                                         compatible = "altr,socfpga-perip-clk";
 187                                                         clocks = <&periph_pll>;
 188                                                         reg = <0x8C>;
 189                                                 };
 190
 191                                                 per_qspi_clk: per_qsi_clk {
 192                                                         #clock-cells = <0>;
 193                                                         compatible = "altr,socfpga-perip-clk";
 194                                                         clocks = <&periph_pll>;
 195                                                         reg = <0x90>;
 196                                                 };
 197
 198                                                 per_nand_mmc_clk: per_nand_mmc_clk {
 199                                                         #clock-cells = <0>;
 200                                                         compatible = "altr,socfpga-perip-clk";
 201                                                         clocks = <&periph_pll>;
 202                                                         reg = <0x94>;
 203                                                 };
 204
 205                                                 per_base_clk: per_base_clk {
 206                                                         #clock-cells = <0>;
 207                                                         compatible = "altr,socfpga-perip-clk";
 208                                                         clocks = <&periph_pll>;
 209                                                         reg = <0x98>;
 210                                                 };
 211
 212                                                 h2f_usr1_clk: h2f_usr1_clk {
 213                                                         #clock-cells = <0>;
 214                                                         compatible = "altr,socfpga-perip-clk";
 215                                                         clocks = <&periph_pll>;
 216                                                         reg = <0x9C>;
 217                                                 };
 218                                         };
 219
 220                                         sdram_pll: sdram_pll {
 221                                                 #address-cells = <1>;
 222                                                 #size-cells = <0>;
 223                                                 #clock-cells = <0>;
 224                                                 compatible = "altr,socfpga-pll-clock";
 225                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 226                                                 reg = <0xC0>;
 227
 228                                                 ddr_dqs_clk: ddr_dqs_clk {
 229                                                         #clock-cells = <0>;
 230                                                         compatible = "altr,socfpga-perip-clk";
 231                                                         clocks = <&sdram_pll>;
 232                                                         reg = <0xC8>;
 233                                                 };
 234
 235                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
 236                                                         #clock-cells = <0>;
 237                                                         compatible = "altr,socfpga-perip-clk";
 238                                                         clocks = <&sdram_pll>;
 239                                                         reg = <0xCC>;
 240                                                 };
 241
 242                                                 ddr_dq_clk: ddr_dq_clk {
 243                                                         #clock-cells = <0>;
 244                                                         compatible = "altr,socfpga-perip-clk";
 245                                                         clocks = <&sdram_pll>;
 246                                                         reg = <0xD0>;
 247                                                 };
 248
 249                                                 h2f_usr2_clk: h2f_usr2_clk {
 250                                                         #clock-cells = <0>;
 251                                                         compatible = "altr,socfpga-perip-clk";
 252                                                         clocks = <&sdram_pll>;
 253                                                         reg = <0xD4>;
 254                                                 };
 255                                         };
 256
 257                                         mpu_periph_clk: mpu_periph_clk {
 258                                                 #clock-cells = <0>;
 259                                                 compatible = "altr,socfpga-perip-clk";
 260                                                 clocks = <&mpuclk>;
 261                                                 fixed-divider = <4>;
 262                                         };
 263
 264                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 265                                                 #clock-cells = <0>;
 266                                                 compatible = "altr,socfpga-perip-clk";
 267                                                 clocks = <&mpuclk>;
 268                                                 fixed-divider = <2>;
 269                                         };
 270
 271                                         l4_main_clk: l4_main_clk {
 272                                                 #clock-cells = <0>;
 273                                                 compatible = "altr,socfpga-gate-clk";
 274                                                 clocks = <&mainclk>;
 275                                                 clk-gate = <0x60 0>;
 276                                         };
 277
 278                                         l3_main_clk: l3_main_clk {
 279                                                 #clock-cells = <0>;
 280                                                 compatible = "altr,socfpga-perip-clk";
 281                                                 clocks = <&mainclk>;
 282                                                 fixed-divider = <1>;
 283                                         };
 284
 285                                         l3_mp_clk: l3_mp_clk {
 286                                                 #clock-cells = <0>;
 287                                                 compatible = "altr,socfpga-gate-clk";
 288                                                 clocks = <&mainclk>;
 289                                                 div-reg = <0x64 0 2>;
 290                                                 clk-gate = <0x60 1>;
 291                                         };
 292
 293                                         l3_sp_clk: l3_sp_clk {
 294                                                 #clock-cells = <0>;
 295                                                 compatible = "altr,socfpga-gate-clk";
 296                                                 clocks = <&mainclk>;
 297                                                 div-reg = <0x64 2 2>;
 298                                         };
 299
 300                                         l4_mp_clk: l4_mp_clk {
 301                                                 #clock-cells = <0>;
 302                                                 compatible = "altr,socfpga-gate-clk";
 303                                                 clocks = <&mainclk>, <&per_base_clk>;
 304                                                 div-reg = <0x64 4 3>;
 305                                                 clk-gate = <0x60 2>;
 306                                         };
 307
 308                                         l4_sp_clk: l4_sp_clk {
 309                                                 #clock-cells = <0>;
 310                                                 compatible = "altr,socfpga-gate-clk";
 311                                                 clocks = <&mainclk>, <&per_base_clk>;
 312                                                 div-reg = <0x64 7 3>;
 313                                                 clk-gate = <0x60 3>;
 314                                         };
 315
 316                                         dbg_at_clk: dbg_at_clk {
 317                                                 #clock-cells = <0>;
 318                                                 compatible = "altr,socfpga-gate-clk";
 319                                                 clocks = <&dbg_base_clk>;
 320                                                 div-reg = <0x68 0 2>;
 321                                                 clk-gate = <0x60 4>;
 322                                         };
 323
 324                                         dbg_clk: dbg_clk {
 325                                                 #clock-cells = <0>;
 326                                                 compatible = "altr,socfpga-gate-clk";
 327                                                 clocks = <&dbg_base_clk>;
 328                                                 div-reg = <0x68 2 2>;
 329                                                 clk-gate = <0x60 5>;
 330                                         };
 331
 332                                         dbg_trace_clk: dbg_trace_clk {
 333                                                 #clock-cells = <0>;
 334                                                 compatible = "altr,socfpga-gate-clk";
 335                                                 clocks = <&dbg_base_clk>;
 336                                                 div-reg = <0x6C 0 3>;
 337                                                 clk-gate = <0x60 6>;
 338                                         };
 339
 340                                         dbg_timer_clk: dbg_timer_clk {
 341                                                 #clock-cells = <0>;
 342                                                 compatible = "altr,socfpga-gate-clk";
 343                                                 clocks = <&dbg_base_clk>;
 344                                                 clk-gate = <0x60 7>;
 345                                         };
 346
 347                                         cfg_clk: cfg_clk {
 348                                                 #clock-cells = <0>;
 349                                                 compatible = "altr,socfpga-gate-clk";
 350                                                 clocks = <&cfg_h2f_usr0_clk>;
 351                                                 clk-gate = <0x60 8>;
 352                                         };
 353
 354                                         h2f_user0_clk: h2f_user0_clk {
 355                                                 #clock-cells = <0>;
 356                                                 compatible = "altr,socfpga-gate-clk";
 357                                                 clocks = <&cfg_h2f_usr0_clk>;
 358                                                 clk-gate = <0x60 9>;
 359                                         };
 360
 361                                         emac_0_clk: emac_0_clk {
 362                                                 #clock-cells = <0>;
 363                                                 compatible = "altr,socfpga-gate-clk";
 364                                                 clocks = <&emac0_clk>;
 365                                                 clk-gate = <0xa0 0>;
 366                                         };
 367
 368                                         emac_1_clk: emac_1_clk {
 369                                                 #clock-cells = <0>;
 370                                                 compatible = "altr,socfpga-gate-clk";
 371                                                 clocks = <&emac1_clk>;
 372                                                 clk-gate = <0xa0 1>;
 373                                         };
 374
 375                                         usb_mp_clk: usb_mp_clk {
 376                                                 #clock-cells = <0>;
 377                                                 compatible = "altr,socfpga-gate-clk";
 378                                                 clocks = <&per_base_clk>;
 379                                                 clk-gate = <0xa0 2>;
 380                                                 div-reg = <0xa4 0 3>;
 381                                         };
 382
 383                                         spi_m_clk: spi_m_clk {
 384                                                 #clock-cells = <0>;
 385                                                 compatible = "altr,socfpga-gate-clk";
 386                                                 clocks = <&per_base_clk>;
 387                                                 clk-gate = <0xa0 3>;
 388                                                 div-reg = <0xa4 3 3>;
 389                                         };
 390
 391                                         can0_clk: can0_clk {
 392                                                 #clock-cells = <0>;
 393                                                 compatible = "altr,socfpga-gate-clk";
 394                                                 clocks = <&per_base_clk>;
 395                                                 clk-gate = <0xa0 4>;
 396                                                 div-reg = <0xa4 6 3>;
 397                                         };
 398
 399                                         can1_clk: can1_clk {
 400                                                 #clock-cells = <0>;
 401                                                 compatible = "altr,socfpga-gate-clk";
 402                                                 clocks = <&per_base_clk>;
 403                                                 clk-gate = <0xa0 5>;
 404                                                 div-reg = <0xa4 9 3>;
 405                                         };
 406
 407                                         gpio_db_clk: gpio_db_clk {
 408                                                 #clock-cells = <0>;
 409                                                 compatible = "altr,socfpga-gate-clk";
 410                                                 clocks = <&per_base_clk>;
 411                                                 clk-gate = <0xa0 6>;
 412                                                 div-reg = <0xa8 0 24>;
 413                                         };
 414
 415                                         h2f_user1_clk: h2f_user1_clk {
 416                                                 #clock-cells = <0>;
 417                                                 compatible = "altr,socfpga-gate-clk";
 418                                                 clocks = <&h2f_usr1_clk>;
 419                                                 clk-gate = <0xa0 7>;
 420                                         };
 421
 422                                         sdmmc_clk: sdmmc_clk {
 423                                                 #clock-cells = <0>;
 424                                                 compatible = "altr,socfpga-gate-clk";
 425                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 426                                                 clk-gate = <0xa0 8>;
 427                                                 clk-phase = <0 135>;
 428                                         };
 429
 430                                         nand_x_clk: nand_x_clk {
 431                                                 #clock-cells = <0>;
 432                                                 compatible = "altr,socfpga-gate-clk";
 433                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 434                                                 clk-gate = <0xa0 9>;
 435                                         };
 436
 437                                         nand_clk: nand_clk {
 438                                                 #clock-cells = <0>;
 439                                                 compatible = "altr,socfpga-gate-clk";
 440                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 441                                                 clk-gate = <0xa0 10>;
 442                                                 fixed-divider = <4>;
 443                                         };
 444
 445                                         qspi_clk: qspi_clk {
 446                                                 #clock-cells = <0>;
 447                                                 compatible = "altr,socfpga-gate-clk";
 448                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 449                                                 clk-gate = <0xa0 11>;
 450                                         };
 451                                 };
 452                         };
 453
 454                 gmac0: ethernet@ff700000 {
 455                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 456                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 457                         reg = <0xff700000 0x2000>;
 458                         interrupts = <0 115 4>;
 459                         interrupt-names = "macirq";
 460                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 461                         clocks = <&emac0_clk>;
 462                         clock-names = "stmmaceth";
 463                         status = "disabled";
 464                 };
 465
 466                 gmac1: ethernet@ff702000 {
 467                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 468                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 469                         reg = <0xff702000 0x2000>;
 470                         interrupts = <0 120 4>;
 471                         interrupt-names = "macirq";
 472                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 473                         clocks = <&emac1_clk>;
 474                         clock-names = "stmmaceth";
 475                         status = "disabled";
 476                 };
 477
 478                 L2: l2-cache@fffef000 {
 479                         compatible = "arm,pl310-cache";
 480                         reg = <0xfffef000 0x1000>;
 481                         interrupts = <0 38 0x04>;
 482                         cache-unified;
 483                         cache-level = <2>;
 484                         arm,tag-latency = <1 1 1>;
 485                         arm,data-latency = <2 1 1>;
 486                 };
 487
 488                 mmc: dwmmc0@ff704000 {
 489                         compatible = "altr,socfpga-dw-mshc";
 490                         reg = <0xff704000 0x1000>;
 491                         interrupts = <0 139 4>;
 492                         fifo-depth = <0x400>;
 493                         #address-cells = <1>;
 494                         #size-cells = <0>;
 495                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 496                         clock-names = "biu", "ciu";
 497                 };
 498
 499                 /* Local timer */
 500                 timer@fffec600 {
 501                         compatible = "arm,cortex-a9-twd-timer";
 502                         reg = <0xfffec600 0x100>;
 503                         interrupts = <1 13 0xf04>;
 504                         clocks = <&mpu_periph_clk>;
 505                 };
 506
 507                 timer0: timer0@ffc08000 {
 508                         compatible = "snps,dw-apb-timer";
 509                         interrupts = <0 167 4>;
 510                         reg = <0xffc08000 0x1000>;
 511                 };
 512
 513                 timer1: timer1@ffc09000 {
 514                         compatible = "snps,dw-apb-timer";
 515                         interrupts = <0 168 4>;
 516                         reg = <0xffc09000 0x1000>;
 517                 };
 518
 519                 timer2: timer2@ffd00000 {
 520                         compatible = "snps,dw-apb-timer";
 521                         interrupts = <0 169 4>;
 522                         reg = <0xffd00000 0x1000>;
 523                 };
 524
 525                 timer3: timer3@ffd01000 {
 526                         compatible = "snps,dw-apb-timer";
 527                         interrupts = <0 170 4>;
 528                         reg = <0xffd01000 0x1000>;
 529                 };
 530
 531                 uart0: serial0@ffc02000 {
 532                         compatible = "snps,dw-apb-uart";
 533                         reg = <0xffc02000 0x1000>;
 534                         interrupts = <0 162 4>;
 535                         reg-shift = <2>;
 536                         reg-io-width = <4>;
 537                 };
 538
 539                 uart1: serial1@ffc03000 {
 540                         compatible = "snps,dw-apb-uart";
 541                         reg = <0xffc03000 0x1000>;
 542                         interrupts = <0 163 4>;
 543                         reg-shift = <2>;
 544                         reg-io-width = <4>;
 545                 };
 546
 547                 rstmgr@ffd05000 {
 548                         compatible = "altr,rst-mgr";
 549                         reg = <0xffd05000 0x1000>;
 550                 };
 551
 552                 sysmgr: sysmgr@ffd08000 {
 553                         compatible = "altr,sys-mgr", "syscon";
 554                         reg = <0xffd08000 0x4000>;
 555                 };
 556         };
 557 };