arch/arm/boot/dts/sh73a0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
   4  *
   5  * Copyright (C) 2012 Renesas Solutions Corp.
   6  */
   7
   8 #include <dt-bindings/clock/sh73a0-clock.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         compatible = "renesas,sh73a0";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a9";
  25                         reg = <0>;
  26                         clock-frequency = <1196000000>;
  27                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
  28                         power-domains = <&pd_a2sl>;
  29                         next-level-cache = <&L2>;
  30                 };
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clock-frequency = <1196000000>;
  36                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
  37                         power-domains = <&pd_a2sl>;
  38                         next-level-cache = <&L2>;
  39                 };
  40         };
  41
  42         timer@f0000200 {
  43                 compatible = "arm,cortex-a9-global-timer";
  44                 reg = <0xf0000200 0x100>;
  45                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  46                 clocks = <&periph_clk>;
  47         };
  48
  49         timer@f0000600 {
  50                 compatible = "arm,cortex-a9-twd-timer";
  51                 reg = <0xf0000600 0x20>;
  52                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  53                 clocks = <&periph_clk>;
  54         };
  55
  56         gic: interrupt-controller@f0001000 {
  57                 compatible = "arm,cortex-a9-gic";
  58                 #interrupt-cells = <3>;
  59                 interrupt-controller;
  60                 reg = <0xf0001000 0x1000>,
  61                       <0xf0000100 0x100>;
  62         };
  63
  64         L2: cache-controller@f0100000 {
  65                 compatible = "arm,pl310-cache";
  66                 reg = <0xf0100000 0x1000>;
  67                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  68                 power-domains = <&pd_a3sm>;
  69                 arm,data-latency = <3 3 3>;
  70                 arm,tag-latency = <2 2 2>;
  71                 arm,shared-override;
  72                 cache-unified;
  73                 cache-level = <2>;
  74         };
  75
  76         sbsc2: memory-controller@fb400000 {
  77                 compatible = "renesas,sbsc-sh73a0";
  78                 reg = <0xfb400000 0x400>;
  79                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  81                 interrupt-names = "sec", "temp";
  82                 power-domains = <&pd_a4bc1>;
  83         };
  84
  85         sbsc1: memory-controller@fe400000 {
  86                 compatible = "renesas,sbsc-sh73a0";
  87                 reg = <0xfe400000 0x400>;
  88                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  89                              <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  90                 interrupt-names = "sec", "temp";
  91                 power-domains = <&pd_a4bc0>;
  92         };
  93
  94         pmu {
  95                 compatible = "arm,cortex-a9-pmu";
  96                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  97                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  98                 interrupt-affinity = <&cpu0>, <&cpu1>;
  99         };
 100
 101         cmt1: timer@e6138000 {
 102                 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
 103                 reg = <0xe6138000 0x200>;
 104                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 105                 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
 106                 clock-names = "fck";
 107                 power-domains = <&pd_c5>;
 108                 status = "disabled";
 109         };
 110
 111         irqpin0: interrupt-controller@e6900000 {
 112                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115                 reg = <0xe6900000 4>,
 116                         <0xe6900010 4>,
 117                         <0xe6900020 1>,
 118                         <0xe6900040 1>,
 119                         <0xe6900060 1>;
 120                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 123                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 126                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 127                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 128                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 129                 power-domains = <&pd_a4s>;
 130                 control-parent;
 131         };
 132
 133         irqpin1: interrupt-controller@e6900004 {
 134                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 135                 #interrupt-cells = <2>;
 136                 interrupt-controller;
 137                 reg = <0xe6900004 4>,
 138                         <0xe6900014 4>,
 139                         <0xe6900024 1>,
 140                         <0xe6900044 1>,
 141                         <0xe6900064 1>;
 142                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 151                 power-domains = <&pd_a4s>;
 152                 control-parent;
 153         };
 154
 155         irqpin2: interrupt-controller@e6900008 {
 156                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 157                 #interrupt-cells = <2>;
 158                 interrupt-controller;
 159                 reg = <0xe6900008 4>,
 160                         <0xe6900018 4>,
 161                         <0xe6900028 1>,
 162                         <0xe6900048 1>,
 163                         <0xe6900068 1>;
 164                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 172                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 173                 power-domains = <&pd_a4s>;
 174                 control-parent;
 175         };
 176
 177         irqpin3: interrupt-controller@e690000c {
 178                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 179                 #interrupt-cells = <2>;
 180                 interrupt-controller;
 181                 reg = <0xe690000c 4>,
 182                         <0xe690001c 4>,
 183                         <0xe690002c 1>,
 184                         <0xe690004c 1>,
 185                         <0xe690006c 1>;
 186                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 195                 power-domains = <&pd_a4s>;
 196                 control-parent;
 197         };
 198
 199         i2c0: i2c@e6820000 {
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 203                 reg = <0xe6820000 0x425>;
 204                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 208                 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
 209                 power-domains = <&pd_a3sp>;
 210                 status = "disabled";
 211         };
 212
 213         i2c1: i2c@e6822000 {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 217                 reg = <0xe6822000 0x425>;
 218                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
 223                 power-domains = <&pd_a3sp>;
 224                 status = "disabled";
 225         };
 226
 227         i2c2: i2c@e6824000 {
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 231                 reg = <0xe6824000 0x425>;
 232                 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
 237                 power-domains = <&pd_a3sp>;
 238                 status = "disabled";
 239         };
 240
 241         i2c3: i2c@e6826000 {
 242                 #address-cells = <1>;
 243                 #size-cells = <0>;
 244                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 245                 reg = <0xe6826000 0x425>;
 246                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 250                 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
 251                 power-domains = <&pd_a3sp>;
 252                 status = "disabled";
 253         };
 254
 255         i2c4: i2c@e6828000 {
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 259                 reg = <0xe6828000 0x425>;
 260                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
 265                 power-domains = <&pd_c5>;
 266                 status = "disabled";
 267         };
 268
 269         mmcif: mmc@e6bd0000 {
 270                 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
 271                 reg = <0xe6bd0000 0x100>;
 272                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
 275                 power-domains = <&pd_a3sp>;
 276                 reg-io-width = <4>;
 277                 status = "disabled";
 278         };
 279
 280         msiof0: spi@e6e20000 {
 281                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 282                 reg = <0xe6e20000 0x0064>;
 283                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
 285                 power-domains = <&pd_a3sp>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 status = "disabled";
 289         };
 290
 291         msiof1: spi@e6e10000 {
 292                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 293                 reg = <0xe6e10000 0x0064>;
 294                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
 296                 power-domains = <&pd_a3sp>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 status = "disabled";
 300         };
 301
 302         msiof2: spi@e6e00000 {
 303                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 304                 reg = <0xe6e00000 0x0064>;
 305                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
 307                 power-domains = <&pd_a3sp>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 status = "disabled";
 311         };
 312
 313         msiof3: spi@e6c90000 {
 314                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 315                 reg = <0xe6c90000 0x0064>;
 316                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
 318                 power-domains = <&pd_a3sp>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 status = "disabled";
 322         };
 323
 324         sdhi0: sd@ee100000 {
 325                 compatible = "renesas,sdhi-sh73a0";
 326                 reg = <0xee100000 0x100>;
 327                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
 331                 power-domains = <&pd_a3sp>;
 332                 cap-sd-highspeed;
 333                 status = "disabled";
 334         };
 335
 336         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
 337         sdhi1: sd@ee120000 {
 338                 compatible = "renesas,sdhi-sh73a0";
 339                 reg = <0xee120000 0x100>;
 340                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
 343                 power-domains = <&pd_a3sp>;
 344                 disable-wp;
 345                 cap-sd-highspeed;
 346                 status = "disabled";
 347         };
 348
 349         sdhi2: sd@ee140000 {
 350                 compatible = "renesas,sdhi-sh73a0";
 351                 reg = <0xee140000 0x100>;
 352                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
 355                 power-domains = <&pd_a3sp>;
 356                 disable-wp;
 357                 cap-sd-highspeed;
 358                 status = "disabled";
 359         };
 360
 361         scifa0: serial@e6c40000 {
 362                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 363                 reg = <0xe6c40000 0x100>;
 364                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
 366                 clock-names = "fck";
 367                 power-domains = <&pd_a3sp>;
 368                 status = "disabled";
 369         };
 370
 371         scifa1: serial@e6c50000 {
 372                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 373                 reg = <0xe6c50000 0x100>;
 374                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
 376                 clock-names = "fck";
 377                 power-domains = <&pd_a3sp>;
 378                 status = "disabled";
 379         };
 380
 381         scifa2: serial@e6c60000 {
 382                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 383                 reg = <0xe6c60000 0x100>;
 384                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 385                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
 386                 clock-names = "fck";
 387                 power-domains = <&pd_a3sp>;
 388                 status = "disabled";
 389         };
 390
 391         scifa3: serial@e6c70000 {
 392                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 393                 reg = <0xe6c70000 0x100>;
 394                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
 396                 clock-names = "fck";
 397                 power-domains = <&pd_a3sp>;
 398                 status = "disabled";
 399         };
 400
 401         scifa4: serial@e6c80000 {
 402                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 403                 reg = <0xe6c80000 0x100>;
 404                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
 406                 clock-names = "fck";
 407                 power-domains = <&pd_a3sp>;
 408                 status = "disabled";
 409         };
 410
 411         scifa5: serial@e6cb0000 {
 412                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 413                 reg = <0xe6cb0000 0x100>;
 414                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
 416                 clock-names = "fck";
 417                 power-domains = <&pd_a3sp>;
 418                 status = "disabled";
 419         };
 420
 421         scifa6: serial@e6cc0000 {
 422                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 423                 reg = <0xe6cc0000 0x100>;
 424                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
 426                 clock-names = "fck";
 427                 power-domains = <&pd_a3sp>;
 428                 status = "disabled";
 429         };
 430
 431         scifa7: serial@e6cd0000 {
 432                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 433                 reg = <0xe6cd0000 0x100>;
 434                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
 436                 clock-names = "fck";
 437                 power-domains = <&pd_a3sp>;
 438                 status = "disabled";
 439         };
 440
 441         scifb: serial@e6c30000 {
 442                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
 443                 reg = <0xe6c30000 0x100>;
 444                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 445                 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
 446                 clock-names = "fck";
 447                 power-domains = <&pd_a3sp>;
 448                 status = "disabled";
 449         };
 450
 451         pfc: pin-controller@e6050000 {
 452                 compatible = "renesas,pfc-sh73a0";
 453                 reg = <0xe6050000 0x8000>,
 454                       <0xe605801c 0x1c>;
 455                 gpio-controller;
 456                 #gpio-cells = <2>;
 457                 gpio-ranges =
 458                         <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
 459                         <&pfc 288 288 22>;
 460                 interrupts-extended =
 461                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 462                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 463                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 464                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 465                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 466                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 467                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 468                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 469                 power-domains = <&pd_c5>;
 470         };
 471
 472         sysc: system-controller@e6180000 {
 473                 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
 474                 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
 475
 476                 pm-domains {
 477                         pd_c5: c5 {
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480                                 #power-domain-cells = <0>;
 481
 482                                 pd_c4: c4@0 {
 483                                         reg = <0>;
 484                                         #power-domain-cells = <0>;
 485                                 };
 486
 487                                 pd_d4: d4@1 {
 488                                         reg = <1>;
 489                                         #power-domain-cells = <0>;
 490                                 };
 491
 492                                 pd_a4bc0: a4bc0@4 {
 493                                         reg = <4>;
 494                                         #power-domain-cells = <0>;
 495                                 };
 496
 497                                 pd_a4bc1: a4bc1@5 {
 498                                         reg = <5>;
 499                                         #power-domain-cells = <0>;
 500                                 };
 501
 502                                 pd_a4lc0: a4lc0@6 {
 503                                         reg = <6>;
 504                                         #power-domain-cells = <0>;
 505                                 };
 506
 507                                 pd_a4lc1: a4lc1@7 {
 508                                         reg = <7>;
 509                                         #power-domain-cells = <0>;
 510                                 };
 511
 512                                 pd_a4mp: a4mp@8 {
 513                                         reg = <8>;
 514                                         #address-cells = <1>;
 515                                         #size-cells = <0>;
 516                                         #power-domain-cells = <0>;
 517
 518                                         pd_a3mp: a3mp@9 {
 519                                                 reg = <9>;
 520                                                 #power-domain-cells = <0>;
 521                                         };
 522
 523                                         pd_a3vc: a3vc@10 {
 524                                                 reg = <10>;
 525                                                 #power-domain-cells = <0>;
 526                                         };
 527                                 };
 528
 529                                 pd_a4rm: a4rm@12 {
 530                                         reg = <12>;
 531                                         #address-cells = <1>;
 532                                         #size-cells = <0>;
 533                                         #power-domain-cells = <0>;
 534
 535                                         pd_a3r: a3r@13 {
 536                                                 reg = <13>;
 537                                                 #address-cells = <1>;
 538                                                 #size-cells = <0>;
 539                                                 #power-domain-cells = <0>;
 540
 541                                                 pd_a2rv: a2rv@14 {
 542                                                         reg = <14>;
 543                                                         #address-cells = <1>;
 544                                                         #size-cells = <0>;
 545                                                         #power-domain-cells = <0>;
 546                                                 };
 547                                         };
 548                                 };
 549
 550                                 pd_a4s: a4s@16 {
 551                                         reg = <16>;
 552                                         #address-cells = <1>;
 553                                         #size-cells = <0>;
 554                                         #power-domain-cells = <0>;
 555
 556                                         pd_a3sp: a3sp@17 {
 557                                                 reg = <17>;
 558                                                 #power-domain-cells = <0>;
 559                                         };
 560
 561                                         pd_a3sg: a3sg@18 {
 562                                                 reg = <18>;
 563                                                 #power-domain-cells = <0>;
 564                                         };
 565
 566                                         pd_a3sm: a3sm@19 {
 567                                                 reg = <19>;
 568                                                 #address-cells = <1>;
 569                                                 #size-cells = <0>;
 570                                                 #power-domain-cells = <0>;
 571
 572                                                 pd_a2sl: a2sl@20 {
 573                                                         reg = <20>;
 574                                                         #power-domain-cells = <0>;
 575                                                 };
 576                                         };
 577                                 };
 578                         };
 579                 };
 580         };
 581
 582         sh_fsi2: sound@ec230000 {
 583                 #sound-dai-cells = <1>;
 584                 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 585                 reg = <0xec230000 0x400>;
 586                 interrupts = <GIC_SPI 146 0x4>;
 587                 power-domains = <&pd_a4mp>;
 588                 status = "disabled";
 589         };
 590
 591         bsc: bus@fec10000 {
 592                 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
 593                              "simple-pm-bus";
 594                 #address-cells = <1>;
 595                 #size-cells = <1>;
 596                 ranges = <0 0 0x20000000>;
 597                 reg = <0xfec10000 0x400>;
 598                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 599                 clocks = <&zb_clk>;
 600                 power-domains = <&pd_a4s>;
 601         };
 602
 603         clocks {
 604                 #address-cells = <1>;
 605                 #size-cells = <1>;
 606                 ranges;
 607
 608                 /* External root clocks */
 609                 extalr_clk: extalr {
 610                         compatible = "fixed-clock";
 611                         #clock-cells = <0>;
 612                         clock-frequency = <32768>;
 613                 };
 614                 extal1_clk: extal1 {
 615                         compatible = "fixed-clock";
 616                         #clock-cells = <0>;
 617                         clock-frequency = <26000000>;
 618                 };
 619                 extal2_clk: extal2 {
 620                         compatible = "fixed-clock";
 621                         #clock-cells = <0>;
 622                         /* This value must be overridden by the board. */
 623                         clock-frequency = <0>;
 624                 };
 625                 extcki_clk: extcki {
 626                         compatible = "fixed-clock";
 627                         #clock-cells = <0>;
 628                         /* This value can be overridden by the board. */
 629                         clock-frequency = <0>;
 630                 };
 631                 fsiack_clk: fsiack {
 632                         compatible = "fixed-clock";
 633                         #clock-cells = <0>;
 634                         /* This value can be overridden by the board. */
 635                         clock-frequency = <0>;
 636                 };
 637                 fsibck_clk: fsibck {
 638                         compatible = "fixed-clock";
 639                         #clock-cells = <0>;
 640                         /* This value can be overridden by the board. */
 641                         clock-frequency = <0>;
 642                 };
 643
 644                 /* Special CPG clocks */
 645                 cpg_clocks: cpg_clocks@e6150000 {
 646                         compatible = "renesas,sh73a0-cpg-clocks";
 647                         reg = <0xe6150000 0x10000>;
 648                         clocks = <&extal1_clk>, <&extal2_clk>;
 649                         #clock-cells = <1>;
 650                         clock-output-names = "main", "pll0", "pll1", "pll2",
 651                                              "pll3", "dsi0phy", "dsi1phy",
 652                                              "zg", "m3", "b", "m1", "m2",
 653                                              "z", "zx", "hp";
 654                 };
 655
 656                 /* Variable factor clocks (DIV6) */
 657                 vclk1_clk: vclk1@e6150008 {
 658                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 659                         reg = <0xe6150008 4>;
 660                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 661                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 662                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 663                                  <0>;
 664                         #clock-cells = <0>;
 665                 };
 666                 vclk2_clk: vclk2@e615000c {
 667                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 668                         reg = <0xe615000c 4>;
 669                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 670                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 671                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 672                                  <0>;
 673                         #clock-cells = <0>;
 674                 };
 675                 vclk3_clk: vclk3@e615001c {
 676                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 677                         reg = <0xe615001c 4>;
 678                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 679                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 680                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 681                                  <0>;
 682                         #clock-cells = <0>;
 683                 };
 684                 zb_clk: zb_clk@e6150010 {
 685                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 686                         reg = <0xe6150010 4>;
 687                         clocks = <&pll1_div2_clk>, <0>,
 688                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 689                         #clock-cells = <0>;
 690                         clock-output-names = "zb";
 691                 };
 692                 flctl_clk: flctlck@e6150014 {
 693                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 694                         reg = <0xe6150014 4>;
 695                         clocks = <&pll1_div2_clk>, <0>,
 696                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 697                         #clock-cells = <0>;
 698                 };
 699                 sdhi0_clk: sdhi0ck@e6150074 {
 700                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 701                         reg = <0xe6150074 4>;
 702                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 703                                  <&pll1_div13_clk>, <0>;
 704                         #clock-cells = <0>;
 705                 };
 706                 sdhi1_clk: sdhi1ck@e6150078 {
 707                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 708                         reg = <0xe6150078 4>;
 709                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 710                                  <&pll1_div13_clk>, <0>;
 711                         #clock-cells = <0>;
 712                 };
 713                 sdhi2_clk: sdhi2ck@e615007c {
 714                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 715                         reg = <0xe615007c 4>;
 716                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 717                                  <&pll1_div13_clk>, <0>;
 718                         #clock-cells = <0>;
 719                 };
 720                 fsia_clk: fsia@e6150018 {
 721                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 722                         reg = <0xe6150018 4>;
 723                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 724                                  <&fsiack_clk>, <&fsiack_clk>;
 725                         #clock-cells = <0>;
 726                 };
 727                 fsib_clk: fsib@e6150090 {
 728                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 729                         reg = <0xe6150090 4>;
 730                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 731                                  <&fsibck_clk>, <&fsibck_clk>;
 732                         #clock-cells = <0>;
 733                 };
 734                 sub_clk: sub@e6150080 {
 735                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 736                         reg = <0xe6150080 4>;
 737                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 738                                  <&extal2_clk>, <&extal2_clk>;
 739                         #clock-cells = <0>;
 740                 };
 741                 spua_clk: spua@e6150084 {
 742                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 743                         reg = <0xe6150084 4>;
 744                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 745                                  <&extal2_clk>, <&extal2_clk>;
 746                         #clock-cells = <0>;
 747                 };
 748                 spuv_clk: spuv@e6150094 {
 749                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 750                         reg = <0xe6150094 4>;
 751                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 752                                  <&extal2_clk>, <&extal2_clk>;
 753                         #clock-cells = <0>;
 754                 };
 755                 msu_clk: msu@e6150088 {
 756                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 757                         reg = <0xe6150088 4>;
 758                         clocks = <&pll1_div2_clk>, <0>,
 759                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 760                         #clock-cells = <0>;
 761                 };
 762                 hsi_clk: hsi@e615008c {
 763                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 764                         reg = <0xe615008c 4>;
 765                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 766                                  <&pll1_div7_clk>, <0>;
 767                         #clock-cells = <0>;
 768                 };
 769                 mfg1_clk: mfg1@e6150098 {
 770                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 771                         reg = <0xe6150098 4>;
 772                         clocks = <&pll1_div2_clk>, <0>,
 773                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 774                         #clock-cells = <0>;
 775                 };
 776                 mfg2_clk: mfg2@e615009c {
 777                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 778                         reg = <0xe615009c 4>;
 779                         clocks = <&pll1_div2_clk>, <0>,
 780                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 781                         #clock-cells = <0>;
 782                 };
 783                 dsit_clk: dsit@e6150060 {
 784                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 785                         reg = <0xe6150060 4>;
 786                         clocks = <&pll1_div2_clk>, <0>,
 787                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 788                         #clock-cells = <0>;
 789                 };
 790                 dsi0p_clk: dsi0pck@e6150064 {
 791                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 792                         reg = <0xe6150064 4>;
 793                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 794                                  <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
 795                                  <&extcki_clk>, <0>, <0>, <0>;
 796                         #clock-cells = <0>;
 797                 };
 798
 799                 /* Fixed factor clocks */
 800                 main_div2_clk: main_div2 {
 801                         compatible = "fixed-factor-clock";
 802                         clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
 803                         #clock-cells = <0>;
 804                         clock-div = <2>;
 805                         clock-mult = <1>;
 806                 };
 807                 pll1_div2_clk: pll1_div2 {
 808                         compatible = "fixed-factor-clock";
 809                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 810                         #clock-cells = <0>;
 811                         clock-div = <2>;
 812                         clock-mult = <1>;
 813                 };
 814                 pll1_div7_clk: pll1_div7 {
 815                         compatible = "fixed-factor-clock";
 816                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 817                         #clock-cells = <0>;
 818                         clock-div = <7>;
 819                         clock-mult = <1>;
 820                 };
 821                 pll1_div13_clk: pll1_div13 {
 822                         compatible = "fixed-factor-clock";
 823                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 824                         #clock-cells = <0>;
 825                         clock-div = <13>;
 826                         clock-mult = <1>;
 827                 };
 828                 periph_clk: periph {
 829                         compatible = "fixed-factor-clock";
 830                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
 831                         #clock-cells = <0>;
 832                         clock-div = <4>;
 833                         clock-mult = <1>;
 834                 };
 835
 836                 /* Gate clocks */
 837                 mstp0_clks: mstp0_clks@e6150130 {
 838                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 839                         reg = <0xe6150130 4>, <0xe6150030 4>;
 840                         clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
 841                         #clock-cells = <1>;
 842                         clock-indices = <
 843                                 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
 844                         >;
 845                         clock-output-names =
 846                                 "iic2", "msiof0";
 847                 };
 848                 mstp1_clks: mstp1_clks@e6150134 {
 849                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 850                         reg = <0xe6150134 4>, <0xe6150038 4>;
 851                         clocks = <&cpg_clocks SH73A0_CLK_B>,
 852                                  <&cpg_clocks SH73A0_CLK_B>,
 853                                  <&cpg_clocks SH73A0_CLK_B>,
 854                                  <&cpg_clocks SH73A0_CLK_B>,
 855                                  <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
 856                                  <&cpg_clocks SH73A0_CLK_HP>,
 857                                  <&cpg_clocks SH73A0_CLK_ZG>,
 858                                  <&cpg_clocks SH73A0_CLK_B>;
 859                         #clock-cells = <1>;
 860                         clock-indices = <
 861                                 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
 862                                 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
 863                                 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
 864                                 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
 865                                 SH73A0_CLK_LCDC0
 866                         >;
 867                         clock-output-names =
 868                                 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
 869                                 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
 870                 };
 871                 mstp2_clks: mstp2_clks@e6150138 {
 872                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 873                         reg = <0xe6150138 4>, <0xe6150040 4>;
 874                         clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
 875                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 876                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 877                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 878                                  <&sub_clk>, <&sub_clk>, <&sub_clk>;
 879                         #clock-cells = <1>;
 880                         clock-indices = <
 881                                 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
 882                                 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
 883                                 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
 884                                 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
 885                                 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
 886                                 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
 887                                 SH73A0_CLK_SCIFA4
 888                         >;
 889                         clock-output-names =
 890                                 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
 891                                 "msiof1", "scifa5", "scifb", "msiof2",
 892                                 "scifa0", "scifa1", "scifa2", "scifa3",
 893                                 "scifa4";
 894                 };
 895                 mstp3_clks: mstp3_clks@e615013c {
 896                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 897                         reg = <0xe615013c 4>, <0xe6150048 4>;
 898                         clocks = <&sub_clk>, <&extalr_clk>,
 899                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 900                                  <&cpg_clocks SH73A0_CLK_HP>,
 901                                  <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
 902                                  <&sdhi0_clk>, <&sdhi1_clk>,
 903                                  <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
 904                                  <&main_div2_clk>, <&main_div2_clk>,
 905                                  <&main_div2_clk>, <&main_div2_clk>,
 906                                  <&main_div2_clk>;
 907                         #clock-cells = <1>;
 908                         clock-indices = <
 909                                 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
 910                                 SH73A0_CLK_FSI SH73A0_CLK_IRDA
 911                                 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
 912                                 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
 913                                 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
 914                                 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
 915                                 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
 916                                 SH73A0_CLK_TPU4
 917                         >;
 918                         clock-output-names =
 919                                 "scifa6", "cmt1", "fsi", "irda", "iic1",
 920                                 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
 921                                 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
 922                 };
 923                 mstp4_clks: mstp4_clks@e6150140 {
 924                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 925                         reg = <0xe6150140 4>, <0xe615004c 4>;
 926                         clocks = <&cpg_clocks SH73A0_CLK_HP>,
 927                                  <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
 928                         #clock-cells = <1>;
 929                         clock-indices = <
 930                                 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
 931                                 SH73A0_CLK_KEYSC
 932                         >;
 933                         clock-output-names =
 934                                 "iic3", "iic4", "keysc";
 935                 };
 936                 mstp5_clks: mstp5_clks@e6150144 {
 937                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 938                         reg = <0xe6150144 4>, <0xe615003c 4>;
 939                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 940                         #clock-cells = <1>;
 941                         clock-indices = <
 942                                 SH73A0_CLK_INTCA0
 943                         >;
 944                         clock-output-names =
 945                                 "intca0";
 946                 };
 947         };
 948 };