arch/arm/boot/dts/sh73a0.dtsi

   1 /*
   2  * Device Tree Source for the SH73A0 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 #include <dt-bindings/clock/sh73a0-clock.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,sh73a0";
  18         interrupt-parent = <&gic>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         reg = <0>;
  28                         clock-frequency = <1196000000>;
  29                 };
  30                 cpu@1 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <1>;
  34                         clock-frequency = <1196000000>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@f0001000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xf0001000 0x1000>,
  43                       <0xf0000100 0x100>;
  44         };
  45
  46         sbsc2: memory-controller@fb400000 {
  47                 compatible = "renesas,sbsc-sh73a0";
  48                 reg = <0xfb400000 0x400>;
  49                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
  50                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
  51                 interrupt-names = "sec", "temp";
  52         };
  53
  54         sbsc1: memory-controller@fe400000 {
  55                 compatible = "renesas,sbsc-sh73a0";
  56                 reg = <0xfe400000 0x400>;
  57                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
  58                              <0 36 IRQ_TYPE_LEVEL_HIGH>;
  59                 interrupt-names = "sec", "temp";
  60         };
  61
  62         pmu {
  63                 compatible = "arm,cortex-a9-pmu";
  64                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
  65                              <0 56 IRQ_TYPE_LEVEL_HIGH>;
  66         };
  67
  68         cmt1: timer@e6138000 {
  69                 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
  70                 reg = <0xe6138000 0x200>;
  71                 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
  72
  73                 renesas,channels-mask = <0x3f>;
  74
  75                 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
  76                 clock-names = "fck";
  77                 status = "disabled";
  78         };
  79
  80         irqpin0: irqpin@e6900000 {
  81                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
  82                 #interrupt-cells = <2>;
  83                 interrupt-controller;
  84                 reg = <0xe6900000 4>,
  85                         <0xe6900010 4>,
  86                         <0xe6900020 1>,
  87                         <0xe6900040 1>,
  88                         <0xe6900060 1>;
  89                 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
  90                               0 2 IRQ_TYPE_LEVEL_HIGH
  91                               0 3 IRQ_TYPE_LEVEL_HIGH
  92                               0 4 IRQ_TYPE_LEVEL_HIGH
  93                               0 5 IRQ_TYPE_LEVEL_HIGH
  94                               0 6 IRQ_TYPE_LEVEL_HIGH
  95                               0 7 IRQ_TYPE_LEVEL_HIGH
  96                               0 8 IRQ_TYPE_LEVEL_HIGH>;
  97         };
  98
  99         irqpin1: irqpin@e6900004 {
 100                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 101                 #interrupt-cells = <2>;
 102                 interrupt-controller;
 103                 reg = <0xe6900004 4>,
 104                         <0xe6900014 4>,
 105                         <0xe6900024 1>,
 106                         <0xe6900044 1>,
 107                         <0xe6900064 1>;
 108                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
 109                               0 10 IRQ_TYPE_LEVEL_HIGH
 110                               0 11 IRQ_TYPE_LEVEL_HIGH
 111                               0 12 IRQ_TYPE_LEVEL_HIGH
 112                               0 13 IRQ_TYPE_LEVEL_HIGH
 113                               0 14 IRQ_TYPE_LEVEL_HIGH
 114                               0 15 IRQ_TYPE_LEVEL_HIGH
 115                               0 16 IRQ_TYPE_LEVEL_HIGH>;
 116                 control-parent;
 117         };
 118
 119         irqpin2: irqpin@e6900008 {
 120                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123                 reg = <0xe6900008 4>,
 124                         <0xe6900018 4>,
 125                         <0xe6900028 1>,
 126                         <0xe6900048 1>,
 127                         <0xe6900068 1>;
 128                 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
 129                               0 18 IRQ_TYPE_LEVEL_HIGH
 130                               0 19 IRQ_TYPE_LEVEL_HIGH
 131                               0 20 IRQ_TYPE_LEVEL_HIGH
 132                               0 21 IRQ_TYPE_LEVEL_HIGH
 133                               0 22 IRQ_TYPE_LEVEL_HIGH
 134                               0 23 IRQ_TYPE_LEVEL_HIGH
 135                               0 24 IRQ_TYPE_LEVEL_HIGH>;
 136         };
 137
 138         irqpin3: irqpin@e690000c {
 139                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 140                 #interrupt-cells = <2>;
 141                 interrupt-controller;
 142                 reg = <0xe690000c 4>,
 143                         <0xe690001c 4>,
 144                         <0xe690002c 1>,
 145                         <0xe690004c 1>,
 146                         <0xe690006c 1>;
 147                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
 148                               0 26 IRQ_TYPE_LEVEL_HIGH
 149                               0 27 IRQ_TYPE_LEVEL_HIGH
 150                               0 28 IRQ_TYPE_LEVEL_HIGH
 151                               0 29 IRQ_TYPE_LEVEL_HIGH
 152                               0 30 IRQ_TYPE_LEVEL_HIGH
 153                               0 31 IRQ_TYPE_LEVEL_HIGH
 154                               0 32 IRQ_TYPE_LEVEL_HIGH>;
 155         };
 156
 157         i2c0: i2c@e6820000 {
 158                 #address-cells = <1>;
 159                 #size-cells = <0>;
 160                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 161                 reg = <0xe6820000 0x425>;
 162                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
 163                               0 168 IRQ_TYPE_LEVEL_HIGH
 164                               0 169 IRQ_TYPE_LEVEL_HIGH
 165                               0 170 IRQ_TYPE_LEVEL_HIGH>;
 166                 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
 167                 status = "disabled";
 168         };
 169
 170         i2c1: i2c@e6822000 {
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 174                 reg = <0xe6822000 0x425>;
 175                 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
 176                               0 52 IRQ_TYPE_LEVEL_HIGH
 177                               0 53 IRQ_TYPE_LEVEL_HIGH
 178                               0 54 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
 180                 status = "disabled";
 181         };
 182
 183         i2c2: i2c@e6824000 {
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 187                 reg = <0xe6824000 0x425>;
 188                 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
 189                               0 172 IRQ_TYPE_LEVEL_HIGH
 190                               0 173 IRQ_TYPE_LEVEL_HIGH
 191                               0 174 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
 193                 status = "disabled";
 194         };
 195
 196         i2c3: i2c@e6826000 {
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 200                 reg = <0xe6826000 0x425>;
 201                 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
 202                               0 184 IRQ_TYPE_LEVEL_HIGH
 203                               0 185 IRQ_TYPE_LEVEL_HIGH
 204                               0 186 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
 206                 status = "disabled";
 207         };
 208
 209         i2c4: i2c@e6828000 {
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 213                 reg = <0xe6828000 0x425>;
 214                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
 215                               0 188 IRQ_TYPE_LEVEL_HIGH
 216                               0 189 IRQ_TYPE_LEVEL_HIGH
 217                               0 190 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
 219                 status = "disabled";
 220         };
 221
 222         mmcif: mmc@e6bd0000 {
 223                 compatible = "renesas,sh-mmcif";
 224                 reg = <0xe6bd0000 0x100>;
 225                 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
 226                               0 141 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
 228                 reg-io-width = <4>;
 229                 status = "disabled";
 230         };
 231
 232         sdhi0: sd@ee100000 {
 233                 compatible = "renesas,sdhi-sh73a0";
 234                 reg = <0xee100000 0x100>;
 235                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
 236                               0 84 IRQ_TYPE_LEVEL_HIGH
 237                               0 85 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
 239                 cap-sd-highspeed;
 240                 status = "disabled";
 241         };
 242
 243         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
 244         sdhi1: sd@ee120000 {
 245                 compatible = "renesas,sdhi-sh73a0";
 246                 reg = <0xee120000 0x100>;
 247                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
 248                               0 89 IRQ_TYPE_LEVEL_HIGH>;
 249                 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
 250                 toshiba,mmc-wrprotect-disable;
 251                 cap-sd-highspeed;
 252                 status = "disabled";
 253         };
 254
 255         sdhi2: sd@ee140000 {
 256                 compatible = "renesas,sdhi-sh73a0";
 257                 reg = <0xee140000 0x100>;
 258                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
 259                               0 105 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
 261                 toshiba,mmc-wrprotect-disable;
 262                 cap-sd-highspeed;
 263                 status = "disabled";
 264         };
 265
 266         scifa0: serial@e6c40000 {
 267                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 268                 reg = <0xe6c40000 0x100>;
 269                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
 271                 clock-names = "sci_ick";
 272                 status = "disabled";
 273         };
 274
 275         scifa1: serial@e6c50000 {
 276                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 277                 reg = <0xe6c50000 0x100>;
 278                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
 280                 clock-names = "sci_ick";
 281                 status = "disabled";
 282         };
 283
 284         scifa2: serial@e6c60000 {
 285                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 286                 reg = <0xe6c60000 0x100>;
 287                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
 289                 clock-names = "sci_ick";
 290                 status = "disabled";
 291         };
 292
 293         scifa3: serial@e6c70000 {
 294                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 295                 reg = <0xe6c70000 0x100>;
 296                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
 298                 clock-names = "sci_ick";
 299                 status = "disabled";
 300         };
 301
 302         scifa4: serial@e6c80000 {
 303                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 304                 reg = <0xe6c80000 0x100>;
 305                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
 307                 clock-names = "sci_ick";
 308                 status = "disabled";
 309         };
 310
 311         scifa5: serial@e6cb0000 {
 312                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 313                 reg = <0xe6cb0000 0x100>;
 314                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
 316                 clock-names = "sci_ick";
 317                 status = "disabled";
 318         };
 319
 320         scifa6: serial@e6cc0000 {
 321                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 322                 reg = <0xe6cc0000 0x100>;
 323                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
 325                 clock-names = "sci_ick";
 326                 status = "disabled";
 327         };
 328
 329         scifa7: serial@e6cd0000 {
 330                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 331                 reg = <0xe6cd0000 0x100>;
 332                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
 334                 clock-names = "sci_ick";
 335                 status = "disabled";
 336         };
 337
 338         scifb8: serial@e6c30000 {
 339                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
 340                 reg = <0xe6c30000 0x100>;
 341                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
 343                 clock-names = "sci_ick";
 344                 status = "disabled";
 345         };
 346
 347         pfc: pfc@e6050000 {
 348                 compatible = "renesas,pfc-sh73a0";
 349                 reg = <0xe6050000 0x8000>,
 350                       <0xe605801c 0x1c>;
 351                 gpio-controller;
 352                 #gpio-cells = <2>;
 353                 interrupts-extended =
 354                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 355                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 356                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 357                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 358                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 359                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 360                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 361                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 362         };
 363
 364         sh_fsi2: sound@ec230000 {
 365                 #sound-dai-cells = <1>;
 366                 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 367                 reg = <0xec230000 0x400>;
 368                 interrupts = <0 146 0x4>;
 369                 status = "disabled";
 370         };
 371
 372         clocks {
 373                 #address-cells = <1>;
 374                 #size-cells = <1>;
 375                 ranges;
 376
 377                 /* External root clocks */
 378                 extalr_clk: extalr_clk {
 379                         compatible = "fixed-clock";
 380                         #clock-cells = <0>;
 381                         clock-frequency = <32768>;
 382                         clock-output-names = "extalr";
 383                 };
 384                 extal1_clk: extal1_clk {
 385                         compatible = "fixed-clock";
 386                         #clock-cells = <0>;
 387                         clock-frequency = <26000000>;
 388                         clock-output-names = "extal1";
 389                 };
 390                 extal2_clk: extal2_clk {
 391                         compatible = "fixed-clock";
 392                         #clock-cells = <0>;
 393                         clock-output-names = "extal2";
 394                 };
 395                 extcki_clk: extcki_clk {
 396                         compatible = "fixed-clock";
 397                         #clock-cells = <0>;
 398                         clock-output-names = "extcki";
 399                 };
 400                 fsiack_clk: fsiack_clk {
 401                         compatible = "fixed-clock";
 402                         #clock-cells = <0>;
 403                         clock-frequency = <0>;
 404                         clock-output-names = "fsiack";
 405                 };
 406                 fsibck_clk: fsibck_clk {
 407                         compatible = "fixed-clock";
 408                         #clock-cells = <0>;
 409                         clock-frequency = <0>;
 410                         clock-output-names = "fsibck";
 411                 };
 412
 413                 /* Special CPG clocks */
 414                 cpg_clocks: cpg_clocks@e6150000 {
 415                         compatible = "renesas,sh73a0-cpg-clocks";
 416                         reg = <0xe6150000 0x10000>;
 417                         clocks = <&extal1_clk>, <&extal2_clk>;
 418                         #clock-cells = <1>;
 419                         clock-output-names = "main", "pll0", "pll1", "pll2",
 420                                              "pll3", "dsi0phy", "dsi1phy",
 421                                              "zg", "m3", "b", "m1", "m2",
 422                                              "z", "zx", "hp";
 423                 };
 424
 425                 /* Variable factor clocks (DIV6) */
 426                 vclk1_clk: vclk1_clk@e6150008 {
 427                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 428                         reg = <0xe6150008 4>;
 429                         clocks = <&pll1_div2_clk>;
 430                         #clock-cells = <0>;
 431                         clock-output-names = "vclk1";
 432                 };
 433                 vclk2_clk: vclk2_clk@e615000c {
 434                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 435                         reg = <0xe615000c 4>;
 436                         clocks = <&pll1_div2_clk>;
 437                         #clock-cells = <0>;
 438                         clock-output-names = "vclk2";
 439                 };
 440                 vclk3_clk: vclk3_clk@e615001c {
 441                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 442                         reg = <0xe615001c 4>;
 443                         clocks = <&pll1_div2_clk>;
 444                         #clock-cells = <0>;
 445                         clock-output-names = "vclk3";
 446                 };
 447                 zb_clk: zb_clk@e6150010 {
 448                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 449                         reg = <0xe6150010 4>;
 450                         clocks = <&pll1_div2_clk>;
 451                         #clock-cells = <0>;
 452                         clock-output-names = "zb";
 453                 };
 454                 flctl_clk: flctl_clk@e6150014 {
 455                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 456                         reg = <0xe6150014 4>;
 457                         clocks = <&pll1_div2_clk>;
 458                         #clock-cells = <0>;
 459                         clock-output-names = "flctlck";
 460                 };
 461                 sdhi0_clk: sdhi0_clk@e6150074 {
 462                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 463                         reg = <0xe6150074 4>;
 464                         clocks = <&pll1_div2_clk>;
 465                         #clock-cells = <0>;
 466                         clock-output-names = "sdhi0ck";
 467                 };
 468                 sdhi1_clk: sdhi1_clk@e6150078 {
 469                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 470                         reg = <0xe6150078 4>;
 471                         clocks = <&pll1_div2_clk>;
 472                         #clock-cells = <0>;
 473                         clock-output-names = "sdhi1ck";
 474                 };
 475                 sdhi2_clk: sdhi2_clk@e615007c {
 476                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 477                         reg = <0xe615007c 4>;
 478                         clocks = <&pll1_div2_clk>;
 479                         #clock-cells = <0>;
 480                         clock-output-names = "sdhi2ck";
 481                 };
 482                 fsia_clk: fsia_clk@e6150018 {
 483                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 484                         reg = <0xe6150018 4>;
 485                         clocks = <&pll1_div2_clk>;
 486                         #clock-cells = <0>;
 487                         clock-output-names = "fsia";
 488                 };
 489                 fsib_clk: fsib_clk@e6150090 {
 490                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 491                         reg = <0xe6150090 4>;
 492                         clocks = <&pll1_div2_clk>;
 493                         #clock-cells = <0>;
 494                         clock-output-names = "fsib";
 495                 };
 496                 sub_clk: sub_clk@e6150080 {
 497                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 498                         reg = <0xe6150080 4>;
 499                         clocks = <&extal2_clk>;
 500                         #clock-cells = <0>;
 501                         clock-output-names = "sub";
 502                 };
 503                 spua_clk: spua_clk@e6150084 {
 504                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 505                         reg = <0xe6150084 4>;
 506                         clocks = <&pll1_div2_clk>;
 507                         #clock-cells = <0>;
 508                         clock-output-names = "spua";
 509                 };
 510                 spuv_clk: spuv_clk@e6150094 {
 511                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 512                         reg = <0xe6150094 4>;
 513                         clocks = <&pll1_div2_clk>;
 514                         #clock-cells = <0>;
 515                         clock-output-names = "spuv";
 516                 };
 517                 msu_clk: msu_clk@e6150088 {
 518                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 519                         reg = <0xe6150088 4>;
 520                         clocks = <&pll1_div2_clk>;
 521                         #clock-cells = <0>;
 522                         clock-output-names = "msu";
 523                 };
 524                 hsi_clk: hsi_clk@e615008c {
 525                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 526                         reg = <0xe615008c 4>;
 527                         clocks = <&pll1_div2_clk>;
 528                         #clock-cells = <0>;
 529                         clock-output-names = "hsi";
 530                 };
 531                 mfg1_clk: mfg1_clk@e6150098 {
 532                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 533                         reg = <0xe6150098 4>;
 534                         clocks = <&pll1_div2_clk>;
 535                         #clock-cells = <0>;
 536                         clock-output-names = "mfg1";
 537                 };
 538                 mfg2_clk: mfg2_clk@e615009c {
 539                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 540                         reg = <0xe615009c 4>;
 541                         clocks = <&pll1_div2_clk>;
 542                         #clock-cells = <0>;
 543                         clock-output-names = "mfg2";
 544                 };
 545                 dsit_clk: dsit_clk@e6150060 {
 546                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 547                         reg = <0xe6150060 4>;
 548                         clocks = <&pll1_div2_clk>;
 549                         #clock-cells = <0>;
 550                         clock-output-names = "dsit";
 551                 };
 552                 dsi0p_clk: dsi0p_clk@e6150064 {
 553                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 554                         reg = <0xe6150064 4>;
 555                         clocks = <&pll1_div2_clk>;
 556                         #clock-cells = <0>;
 557                         clock-output-names = "dsi0pck";
 558                 };
 559
 560                 /* Fixed factor clocks */
 561                 main_div2_clk: main_div2_clk {
 562                         compatible = "fixed-factor-clock";
 563                         clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
 564                         #clock-cells = <0>;
 565                         clock-div = <2>;
 566                         clock-mult = <1>;
 567                         clock-output-names = "main_div2";
 568                 };
 569                 pll1_div2_clk: pll1_div2_clk {
 570                         compatible = "fixed-factor-clock";
 571                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 572                         #clock-cells = <0>;
 573                         clock-div = <2>;
 574                         clock-mult = <1>;
 575                         clock-output-names = "pll1_div2";
 576                 };
 577                 pll1_div7_clk: pll1_div7_clk {
 578                         compatible = "fixed-factor-clock";
 579                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 580                         #clock-cells = <0>;
 581                         clock-div = <7>;
 582                         clock-mult = <1>;
 583                         clock-output-names = "pll1_div7";
 584                 };
 585                 pll1_div13_clk: pll1_div13_clk {
 586                         compatible = "fixed-factor-clock";
 587                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 588                         #clock-cells = <0>;
 589                         clock-div = <13>;
 590                         clock-mult = <1>;
 591                         clock-output-names = "pll1_div13";
 592                 };
 593                 twd_clk: twd_clk {
 594                         compatible = "fixed-factor-clock";
 595                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
 596                         #clock-cells = <0>;
 597                         clock-div = <4>;
 598                         clock-mult = <1>;
 599                         clock-output-names = "twd";
 600                 };
 601
 602                 /* Gate clocks */
 603                 mstp0_clks: mstp0_clks@e6150130 {
 604                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 605                         reg = <0xe6150130 4>, <0xe6150030 4>;
 606                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 607                         #clock-cells = <1>;
 608                         clock-indices = <
 609                                 SH73A0_CLK_IIC2
 610                         >;
 611                         clock-output-names =
 612                                 "iic2";
 613                 };
 614                 mstp1_clks: mstp1_clks@e6150134 {
 615                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 616                         reg = <0xe6150134 4>, <0xe6150038 4>;
 617                         clocks = <&cpg_clocks SH73A0_CLK_B>,
 618                                  <&cpg_clocks SH73A0_CLK_B>,
 619                                  <&cpg_clocks SH73A0_CLK_B>,
 620                                  <&cpg_clocks SH73A0_CLK_B>,
 621                                  <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
 622                                  <&cpg_clocks SH73A0_CLK_HP>,
 623                                  <&cpg_clocks SH73A0_CLK_ZG>,
 624                                  <&cpg_clocks SH73A0_CLK_B>;
 625                         #clock-cells = <1>;
 626                         clock-indices = <
 627                                 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
 628                                 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
 629                                 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
 630                                 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
 631                                 SH73A0_CLK_LCDC0
 632                         >;
 633                         clock-output-names =
 634                                 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
 635                                 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
 636                 };
 637                 mstp2_clks: mstp2_clks@e6150138 {
 638                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 639                         reg = <0xe6150138 4>, <0xe6150040 4>;
 640                         clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
 641                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 642                                  <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
 643                                  <&sub_clk>, <&sub_clk>;
 644                         #clock-cells = <1>;
 645                         clock-indices = <
 646                                 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
 647                                 SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
 648                                 SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
 649                                 SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
 650                                 SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
 651                         >;
 652                         clock-output-names =
 653                                 "scifa7", "sy_dmac", "mp_dmac", "scifa5",
 654                                 "scifb", "scifa0", "scifa1", "scifa2",
 655                                 "scifa3", "scifa4";
 656                 };
 657                 mstp3_clks: mstp3_clks@e615013c {
 658                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 659                         reg = <0xe615013c 4>, <0xe6150048 4>;
 660                         clocks = <&sub_clk>, <&extalr_clk>,
 661                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 662                                  <&cpg_clocks SH73A0_CLK_HP>,
 663                                  <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
 664                                  <&sdhi0_clk>, <&sdhi1_clk>,
 665                                  <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
 666                                  <&main_div2_clk>, <&main_div2_clk>,
 667                                  <&main_div2_clk>, <&main_div2_clk>,
 668                                  <&main_div2_clk>;
 669                         #clock-cells = <1>;
 670                         clock-indices = <
 671                                 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
 672                                 SH73A0_CLK_FSI SH73A0_CLK_IRDA
 673                                 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
 674                                 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
 675                                 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
 676                                 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
 677                                 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
 678                                 SH73A0_CLK_TPU4
 679                         >;
 680                         clock-output-names =
 681                                 "scifa6", "cmt1", "fsi", "irda", "iic1",
 682                                 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
 683                                 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
 684                 };
 685                 mstp4_clks: mstp4_clks@e6150140 {
 686                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 687                         reg = <0xe6150140 4>, <0xe615004c 4>;
 688                         clocks = <&cpg_clocks SH73A0_CLK_HP>,
 689                                  <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
 690                         #clock-cells = <1>;
 691                         clock-indices = <
 692                                 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
 693                                 SH73A0_CLK_KEYSC
 694                         >;
 695                         clock-output-names =
 696                                 "iic3", "iic4", "keysc";
 697                 };
 698         };
 699 };