arch/arm/boot/dts/sama5d2.dtsi

   1 /*
   2  * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
   3  *
   4  *  Copyright (C) 2015 Atmel,
   5  *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/dma/at91.h>
  48 #include <dt-bindings/interrupt-controller/irq.h>
  49 #include <dt-bindings/clock/at91.h>
  50
  51 / {
  52         model = "Atmel SAMA5D2 family SoC";
  53         compatible = "atmel,sama5d2";
  54         interrupt-parent = <&aic>;
  55
  56         aliases {
  57                 serial0 = &uart1;
  58                 serial1 = &uart3;
  59                 tcb0 = &tcb0;
  60                 tcb1 = &tcb1;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a5";
  70                         reg = <0>;
  71                         next-level-cache = <&L2>;
  72                 };
  73         };
  74
  75         pmu {
  76                 compatible = "arm,cortex-a5-pmu";
  77                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
  78         };
  79
  80         etb {
  81                 compatible = "arm,coresight-etb10", "arm,primecell";
  82                 reg = <0x740000 0x1000>;
  83
  84                 clocks = <&mck>;
  85                 clock-names = "apb_pclk";
  86
  87                 port {
  88                         etb_in: endpoint {
  89                                 slave-mode;
  90                                 remote-endpoint = <&etm_out>;
  91                         };
  92                 };
  93         };
  94
  95         etm {
  96                 compatible = "arm,coresight-etm3x", "arm,primecell";
  97                 reg = <0x73C000 0x1000>;
  98
  99                 clocks = <&mck>;
 100                 clock-names = "apb_pclk";
 101
 102                 port {
 103                         etm_out: endpoint {
 104                                 remote-endpoint = <&etb_in>;
 105                         };
 106                 };
 107         };
 108
 109         memory {
 110                 reg = <0x20000000 0x20000000>;
 111         };
 112
 113         clocks {
 114                 slow_xtal: slow_xtal {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                 };
 119
 120                 main_xtal: main_xtal {
 121                         compatible = "fixed-clock";
 122                         #clock-cells = <0>;
 123                         clock-frequency = <0>;
 124                 };
 125         };
 126
 127         ns_sram: sram@00200000 {
 128                 compatible = "mmio-sram";
 129                 reg = <0x00200000 0x20000>;
 130         };
 131
 132         ahb {
 133                 compatible = "simple-bus";
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 ranges;
 137
 138                 nfc_sram: sram@00100000 {
 139                         compatible = "mmio-sram";
 140                         no-memory-wc;
 141                         reg = <0x00100000 0x2400>;
 142                 };
 143
 144                 usb0: gadget@00300000 {
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         compatible = "atmel,sama5d3-udc";
 148                         reg = <0x00300000 0x100000
 149                                0xfc02c000 0x400>;
 150                         interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
 151                         clocks = <&udphs_clk>, <&utmi>;
 152                         clock-names = "pclk", "hclk";
 153                         status = "disabled";
 154
 155                         ep@0 {
 156                                 reg = <0>;
 157                                 atmel,fifo-size = <64>;
 158                                 atmel,nb-banks = <1>;
 159                         };
 160
 161                         ep@1 {
 162                                 reg = <1>;
 163                                 atmel,fifo-size = <1024>;
 164                                 atmel,nb-banks = <3>;
 165                                 atmel,can-dma;
 166                                 atmel,can-isoc;
 167                         };
 168
 169                         ep@2 {
 170                                 reg = <2>;
 171                                 atmel,fifo-size = <1024>;
 172                                 atmel,nb-banks = <3>;
 173                                 atmel,can-dma;
 174                                 atmel,can-isoc;
 175                         };
 176
 177                         ep@3 {
 178                                 reg = <3>;
 179                                 atmel,fifo-size = <1024>;
 180                                 atmel,nb-banks = <2>;
 181                                 atmel,can-dma;
 182                                 atmel,can-isoc;
 183                         };
 184
 185                         ep@4 {
 186                                 reg = <4>;
 187                                 atmel,fifo-size = <1024>;
 188                                 atmel,nb-banks = <2>;
 189                                 atmel,can-dma;
 190                                 atmel,can-isoc;
 191                         };
 192
 193                         ep@5 {
 194                                 reg = <5>;
 195                                 atmel,fifo-size = <1024>;
 196                                 atmel,nb-banks = <2>;
 197                                 atmel,can-dma;
 198                                 atmel,can-isoc;
 199                         };
 200
 201                         ep@6 {
 202                                 reg = <6>;
 203                                 atmel,fifo-size = <1024>;
 204                                 atmel,nb-banks = <2>;
 205                                 atmel,can-dma;
 206                                 atmel,can-isoc;
 207                         };
 208
 209                         ep@7 {
 210                                 reg = <7>;
 211                                 atmel,fifo-size = <1024>;
 212                                 atmel,nb-banks = <2>;
 213                                 atmel,can-dma;
 214                                 atmel,can-isoc;
 215                         };
 216
 217                         ep@8 {
 218                                 reg = <8>;
 219                                 atmel,fifo-size = <1024>;
 220                                 atmel,nb-banks = <2>;
 221                                 atmel,can-isoc;
 222                         };
 223
 224                         ep@9 {
 225                                 reg = <9>;
 226                                 atmel,fifo-size = <1024>;
 227                                 atmel,nb-banks = <2>;
 228                                 atmel,can-isoc;
 229                         };
 230
 231                         ep@10 {
 232                                 reg = <10>;
 233                                 atmel,fifo-size = <1024>;
 234                                 atmel,nb-banks = <2>;
 235                                 atmel,can-isoc;
 236                         };
 237
 238                         ep@11 {
 239                                 reg = <11>;
 240                                 atmel,fifo-size = <1024>;
 241                                 atmel,nb-banks = <2>;
 242                                 atmel,can-isoc;
 243                         };
 244
 245                         ep@12 {
 246                                 reg = <12>;
 247                                 atmel,fifo-size = <1024>;
 248                                 atmel,nb-banks = <2>;
 249                                 atmel,can-isoc;
 250                         };
 251
 252                         ep@13 {
 253                                 reg = <13>;
 254                                 atmel,fifo-size = <1024>;
 255                                 atmel,nb-banks = <2>;
 256                                 atmel,can-isoc;
 257                         };
 258
 259                         ep@14 {
 260                                 reg = <14>;
 261                                 atmel,fifo-size = <1024>;
 262                                 atmel,nb-banks = <2>;
 263                                 atmel,can-isoc;
 264                         };
 265
 266                         ep@15 {
 267                                 reg = <15>;
 268                                 atmel,fifo-size = <1024>;
 269                                 atmel,nb-banks = <2>;
 270                                 atmel,can-isoc;
 271                         };
 272                 };
 273
 274                 usb1: ohci@00400000 {
 275                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 276                         reg = <0x00400000 0x100000>;
 277                         interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
 278                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
 279                         clock-names = "ohci_clk", "hclk", "uhpck";
 280                         status = "disabled";
 281                 };
 282
 283                 usb2: ehci@00500000 {
 284                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 285                         reg = <0x00500000 0x100000>;
 286                         interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
 287                         clocks = <&utmi>, <&uhphs_clk>;
 288                         clock-names = "usb_clk", "ehci_clk";
 289                         status = "disabled";
 290                 };
 291
 292                 L2: cache-controller@00a00000 {
 293                         compatible = "arm,pl310-cache";
 294                         reg = <0x00a00000 0x1000>;
 295                         interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
 296                         cache-unified;
 297                         cache-level = <2>;
 298                 };
 299
 300                 ebi: ebi@10000000 {
 301                         compatible = "atmel,sama5d3-ebi";
 302                         #address-cells = <2>;
 303                         #size-cells = <1>;
 304                         atmel,smc = <&hsmc>;
 305                         reg = <0x10000000 0x10000000
 306                                0x40000000 0x30000000>;
 307                         ranges = <0x0 0x0 0x10000000 0x10000000
 308                                   0x1 0x0 0x60000000 0x10000000
 309                                   0x2 0x0 0x70000000 0x10000000
 310                                   0x3 0x0 0x80000000 0x10000000>;
 311                         clocks = <&mck>;
 312                         status = "disabled";
 313
 314                         nand_controller: nand-controller {
 315                                 compatible = "atmel,sama5d3-nand-controller";
 316                                 atmel,nfc-sram = <&nfc_sram>;
 317                                 atmel,nfc-io = <&nfc_io>;
 318                                 ecc-engine = <&pmecc>;
 319                                 #address-cells = <2>;
 320                                 #size-cells = <1>;
 321                                 ranges;
 322                                 status = "disabled";
 323                         };
 324                 };
 325
 326                 nand0: nand@80000000 {
 327                         compatible = "atmel,sama5d2-nand";
 328                         #address-cells = <1>;
 329                         #size-cells = <1>;
 330                         ranges;
 331                         reg = < /* EBI CS3 */
 332                                 0x80000000 0x08000000
 333                                 /* SMC PMECC regs */
 334                                 0xf8014070 0x00000490
 335                                 /* SMC PMECC Error Location regs */
 336                                 0xf8014500 0x00000200
 337                                 /* ROM Galois tables */
 338                                 0x00040000 0x00018000
 339                                 >;
 340                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
 341                         atmel,nand-addr-offset = <21>;
 342                         atmel,nand-cmd-offset = <22>;
 343                         atmel,nand-has-dma;
 344                         atmel,has-pmecc;
 345                         atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
 346                         status = "disabled";
 347
 348                         nfc@c0000000 {
 349                                 compatible = "atmel,sama5d3-nfc";
 350                                 #address-cells = <1>;
 351                                 #size-cells = <1>;
 352                                 reg = < /* NFC Command Registers */
 353                                         0xc0000000 0x08000000
 354                                         /* NFC HSMC regs */
 355                                         0xf8014000 0x00000070
 356                                         /* NFC SRAM banks */
 357                                         0x00100000 0x00100000
 358                                         >;
 359                                 clocks = <&hsmc_clk>;
 360                                 atmel,write-by-sram;
 361                         };
 362                 };
 363
 364                 sdmmc0: sdio-host@a0000000 {
 365                         compatible = "atmel,sama5d2-sdhci";
 366                         reg = <0xa0000000 0x300>;
 367                         interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
 368                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
 369                         clock-names = "hclock", "multclk", "baseclk";
 370                         status = "disabled";
 371                 };
 372
 373                 sdmmc1: sdio-host@b0000000 {
 374                         compatible = "atmel,sama5d2-sdhci";
 375                         reg = <0xb0000000 0x300>;
 376                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
 377                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
 378                         clock-names = "hclock", "multclk", "baseclk";
 379                         status = "disabled";
 380                 };
 381
 382                 nfc_io: nfc-io@c0000000 {
 383                         compatible = "atmel,sama5d3-nfc-io", "syscon";
 384                         reg = <0xc0000000 0x8000000>;
 385                 };
 386
 387                 apb {
 388                         compatible = "simple-bus";
 389                         #address-cells = <1>;
 390                         #size-cells = <1>;
 391                         ranges;
 392
 393                         hlcdc: hlcdc@f0000000 {
 394                                 compatible = "atmel,sama5d2-hlcdc";
 395                                 reg = <0xf0000000 0x2000>;
 396                                 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
 397                                 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
 398                                 clock-names = "periph_clk","sys_clk", "slow_clk";
 399                                 status = "disabled";
 400
 401                                 hlcdc-display-controller {
 402                                         compatible = "atmel,hlcdc-display-controller";
 403                                         #address-cells = <1>;
 404                                         #size-cells = <0>;
 405
 406                                         port@0 {
 407                                                 #address-cells = <1>;
 408                                                 #size-cells = <0>;
 409                                                 reg = <0>;
 410                                         };
 411                                 };
 412
 413                                 hlcdc_pwm: hlcdc-pwm {
 414                                         compatible = "atmel,hlcdc-pwm";
 415                                         #pwm-cells = <3>;
 416                                 };
 417                         };
 418
 419                         ramc0: ramc@f000c000 {
 420                                 compatible = "atmel,sama5d3-ddramc";
 421                                 reg = <0xf000c000 0x200>;
 422                                 clocks = <&ddrck>, <&mpddr_clk>;
 423                                 clock-names = "ddrck", "mpddr";
 424                         };
 425
 426                         dma0: dma-controller@f0010000 {
 427                                 compatible = "atmel,sama5d4-dma";
 428                                 reg = <0xf0010000 0x1000>;
 429                                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
 430                                 #dma-cells = <1>;
 431                                 clocks = <&dma0_clk>;
 432                                 clock-names = "dma_clk";
 433                         };
 434
 435                         /* Place dma1 here despite its address */
 436                         dma1: dma-controller@f0004000 {
 437                                 compatible = "atmel,sama5d4-dma";
 438                                 reg = <0xf0004000 0x1000>;
 439                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
 440                                 #dma-cells = <1>;
 441                                 clocks = <&dma1_clk>;
 442                                 clock-names = "dma_clk";
 443                         };
 444
 445                         pmc: pmc@f0014000 {
 446                                 compatible = "atmel,sama5d2-pmc", "syscon";
 447                                 reg = <0xf0014000 0x160>;
 448                                 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
 449                                 interrupt-controller;
 450                                 #address-cells = <1>;
 451                                 #size-cells = <0>;
 452                                 #interrupt-cells = <1>;
 453
 454                                 main_rc_osc: main_rc_osc {
 455                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 456                                         #clock-cells = <0>;
 457                                         interrupt-parent = <&pmc>;
 458                                         interrupts = <AT91_PMC_MOSCRCS>;
 459                                         clock-frequency = <12000000>;
 460                                         clock-accuracy = <100000000>;
 461                                 };
 462
 463                                 main_osc: main_osc {
 464                                         compatible = "atmel,at91rm9200-clk-main-osc";
 465                                         #clock-cells = <0>;
 466                                         interrupt-parent = <&pmc>;
 467                                         interrupts = <AT91_PMC_MOSCS>;
 468                                         clocks = <&main_xtal>;
 469                                 };
 470
 471                                 main: mainck {
 472                                         compatible = "atmel,at91sam9x5-clk-main";
 473                                         #clock-cells = <0>;
 474                                         interrupt-parent = <&pmc>;
 475                                         interrupts = <AT91_PMC_MOSCSELS>;
 476                                         clocks = <&main_rc_osc &main_osc>;
 477                                 };
 478
 479                                 plla: pllack {
 480                                         compatible = "atmel,sama5d3-clk-pll";
 481                                         #clock-cells = <0>;
 482                                         interrupt-parent = <&pmc>;
 483                                         interrupts = <AT91_PMC_LOCKA>;
 484                                         clocks = <&main>;
 485                                         reg = <0>;
 486                                         atmel,clk-input-range = <12000000 12000000>;
 487                                         #atmel,pll-clk-output-range-cells = <4>;
 488                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 489                                 };
 490
 491                                 plladiv: plladivck {
 492                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 493                                         #clock-cells = <0>;
 494                                         clocks = <&plla>;
 495                                 };
 496
 497                                 utmi: utmick {
 498                                         compatible = "atmel,at91sam9x5-clk-utmi";
 499                                         #clock-cells = <0>;
 500                                         interrupt-parent = <&pmc>;
 501                                         interrupts = <AT91_PMC_LOCKU>;
 502                                         clocks = <&main>;
 503                                 };
 504
 505                                 mck: masterck {
 506                                         compatible = "atmel,at91sam9x5-clk-master";
 507                                         #clock-cells = <0>;
 508                                         interrupt-parent = <&pmc>;
 509                                         interrupts = <AT91_PMC_MCKRDY>;
 510                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 511                                         atmel,clk-output-range = <124000000 166000000>;
 512                                         atmel,clk-divisors = <1 2 4 3>;
 513                                 };
 514
 515                                 h32ck: h32mxck {
 516                                         #clock-cells = <0>;
 517                                         compatible = "atmel,sama5d4-clk-h32mx";
 518                                         clocks = <&mck>;
 519                                 };
 520
 521                                 usb: usbck {
 522                                         compatible = "atmel,at91sam9x5-clk-usb";
 523                                         #clock-cells = <0>;
 524                                         clocks = <&plladiv>, <&utmi>;
 525                                 };
 526
 527                                 prog: progck {
 528                                         compatible = "atmel,at91sam9x5-clk-programmable";
 529                                         #address-cells = <1>;
 530                                         #size-cells = <0>;
 531                                         interrupt-parent = <&pmc>;
 532                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 533
 534                                         prog0: prog0 {
 535                                                 #clock-cells = <0>;
 536                                                 reg = <0>;
 537                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 538                                         };
 539
 540                                         prog1: prog1 {
 541                                                 #clock-cells = <0>;
 542                                                 reg = <1>;
 543                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 544                                         };
 545
 546                                         prog2: prog2 {
 547                                                 #clock-cells = <0>;
 548                                                 reg = <2>;
 549                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 550                                         };
 551                                 };
 552
 553                                 systemck {
 554                                         compatible = "atmel,at91rm9200-clk-system";
 555                                         #address-cells = <1>;
 556                                         #size-cells = <0>;
 557
 558                                         ddrck: ddrck {
 559                                                 #clock-cells = <0>;
 560                                                 reg = <2>;
 561                                                 clocks = <&mck>;
 562                                         };
 563
 564                                         lcdck: lcdck {
 565                                                 #clock-cells = <0>;
 566                                                 reg = <3>;
 567                                                 clocks = <&mck>;
 568                                         };
 569
 570                                         uhpck: uhpck {
 571                                                 #clock-cells = <0>;
 572                                                 reg = <6>;
 573                                                 clocks = <&usb>;
 574                                         };
 575
 576                                         udpck: udpck {
 577                                                 #clock-cells = <0>;
 578                                                 reg = <7>;
 579                                                 clocks = <&usb>;
 580                                         };
 581
 582                                         pck0: pck0 {
 583                                                 #clock-cells = <0>;
 584                                                 reg = <8>;
 585                                                 clocks = <&prog0>;
 586                                         };
 587
 588                                         pck1: pck1 {
 589                                                 #clock-cells = <0>;
 590                                                 reg = <9>;
 591                                                 clocks = <&prog1>;
 592                                         };
 593
 594                                         pck2: pck2 {
 595                                                 #clock-cells = <0>;
 596                                                 reg = <10>;
 597                                                 clocks = <&prog2>;
 598                                         };
 599
 600                                         iscck: iscck {
 601                                                 #clock-cells = <0>;
 602                                                 reg = <18>;
 603                                                 clocks = <&mck>;
 604                                         };
 605                                 };
 606
 607                                 periph32ck {
 608                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 609                                         #address-cells = <1>;
 610                                         #size-cells = <0>;
 611                                         clocks = <&h32ck>;
 612
 613                                         macb0_clk: macb0_clk {
 614                                                 #clock-cells = <0>;
 615                                                 reg = <5>;
 616                                                 atmel,clk-output-range = <0 83000000>;
 617                                         };
 618
 619                                         tdes_clk: tdes_clk {
 620                                                 #clock-cells = <0>;
 621                                                 reg = <11>;
 622                                                 atmel,clk-output-range = <0 83000000>;
 623                                         };
 624
 625                                         matrix1_clk: matrix1_clk {
 626                                                 #clock-cells = <0>;
 627                                                 reg = <14>;
 628                                         };
 629
 630                                         hsmc_clk: hsmc_clk {
 631                                                 #clock-cells = <0>;
 632                                                 reg = <17>;
 633                                         };
 634
 635                                         pioA_clk: pioA_clk {
 636                                                 #clock-cells = <0>;
 637                                                 reg = <18>;
 638                                                 atmel,clk-output-range = <0 83000000>;
 639                                         };
 640
 641                                         flx0_clk: flx0_clk {
 642                                                 #clock-cells = <0>;
 643                                                 reg = <19>;
 644                                                 atmel,clk-output-range = <0 83000000>;
 645                                         };
 646
 647                                         flx1_clk: flx1_clk {
 648                                                 #clock-cells = <0>;
 649                                                 reg = <20>;
 650                                                 atmel,clk-output-range = <0 83000000>;
 651                                         };
 652
 653                                         flx2_clk: flx2_clk {
 654                                                 #clock-cells = <0>;
 655                                                 reg = <21>;
 656                                                 atmel,clk-output-range = <0 83000000>;
 657                                         };
 658
 659                                         flx3_clk: flx3_clk {
 660                                                 #clock-cells = <0>;
 661                                                 reg = <22>;
 662                                                 atmel,clk-output-range = <0 83000000>;
 663                                         };
 664
 665                                         flx4_clk: flx4_clk {
 666                                                 #clock-cells = <0>;
 667                                                 reg = <23>;
 668                                                 atmel,clk-output-range = <0 83000000>;
 669                                         };
 670
 671                                         uart0_clk: uart0_clk {
 672                                                 #clock-cells = <0>;
 673                                                 reg = <24>;
 674                                                 atmel,clk-output-range = <0 83000000>;
 675                                         };
 676
 677                                         uart1_clk: uart1_clk {
 678                                                 #clock-cells = <0>;
 679                                                 reg = <25>;
 680                                                 atmel,clk-output-range = <0 83000000>;
 681                                         };
 682
 683                                         uart2_clk: uart2_clk {
 684                                                 #clock-cells = <0>;
 685                                                 reg = <26>;
 686                                                 atmel,clk-output-range = <0 83000000>;
 687                                         };
 688
 689                                         uart3_clk: uart3_clk {
 690                                                 #clock-cells = <0>;
 691                                                 reg = <27>;
 692                                                 atmel,clk-output-range = <0 83000000>;
 693                                         };
 694
 695                                         uart4_clk: uart4_clk {
 696                                                 #clock-cells = <0>;
 697                                                 reg = <28>;
 698                                                 atmel,clk-output-range = <0 83000000>;
 699                                         };
 700
 701                                         twi0_clk: twi0_clk {
 702                                                 reg = <29>;
 703                                                 #clock-cells = <0>;
 704                                                 atmel,clk-output-range = <0 83000000>;
 705                                         };
 706
 707                                         twi1_clk: twi1_clk {
 708                                                 #clock-cells = <0>;
 709                                                 reg = <30>;
 710                                                 atmel,clk-output-range = <0 83000000>;
 711                                         };
 712
 713                                         spi0_clk: spi0_clk {
 714                                                 #clock-cells = <0>;
 715                                                 reg = <33>;
 716                                                 atmel,clk-output-range = <0 83000000>;
 717                                         };
 718
 719                                         spi1_clk: spi1_clk {
 720                                                 #clock-cells = <0>;
 721                                                 reg = <34>;
 722                                                 atmel,clk-output-range = <0 83000000>;
 723                                         };
 724
 725                                         tcb0_clk: tcb0_clk {
 726                                                 #clock-cells = <0>;
 727                                                 reg = <35>;
 728                                                 atmel,clk-output-range = <0 83000000>;
 729                                         };
 730
 731                                         tcb1_clk: tcb1_clk {
 732                                                 #clock-cells = <0>;
 733                                                 reg = <36>;
 734                                                 atmel,clk-output-range = <0 83000000>;
 735                                         };
 736
 737                                         pwm_clk: pwm_clk {
 738                                                 #clock-cells = <0>;
 739                                                 reg = <38>;
 740                                                 atmel,clk-output-range = <0 83000000>;
 741                                         };
 742
 743                                         adc_clk: adc_clk {
 744                                                 #clock-cells = <0>;
 745                                                 reg = <40>;
 746                                                 atmel,clk-output-range = <0 83000000>;
 747                                         };
 748
 749                                         uhphs_clk: uhphs_clk {
 750                                                 #clock-cells = <0>;
 751                                                 reg = <41>;
 752                                                 atmel,clk-output-range = <0 83000000>;
 753                                         };
 754
 755                                         udphs_clk: udphs_clk {
 756                                                 #clock-cells = <0>;
 757                                                 reg = <42>;
 758                                                 atmel,clk-output-range = <0 83000000>;
 759                                         };
 760
 761                                         ssc0_clk: ssc0_clk {
 762                                                 #clock-cells = <0>;
 763                                                 reg = <43>;
 764                                                 atmel,clk-output-range = <0 83000000>;
 765                                         };
 766
 767                                         ssc1_clk: ssc1_clk {
 768                                                 #clock-cells = <0>;
 769                                                 reg = <44>;
 770                                                 atmel,clk-output-range = <0 83000000>;
 771                                         };
 772
 773                                         trng_clk: trng_clk {
 774                                                 #clock-cells = <0>;
 775                                                 reg = <47>;
 776                                                 atmel,clk-output-range = <0 83000000>;
 777                                         };
 778
 779                                         pdmic_clk: pdmic_clk {
 780                                                 #clock-cells = <0>;
 781                                                 reg = <48>;
 782                                                 atmel,clk-output-range = <0 83000000>;
 783                                         };
 784
 785                                         securam_clk: securam_clk {
 786                                                 #clock-cells = <0>;
 787                                                 reg = <51>;
 788                                         };
 789
 790                                         i2s0_clk: i2s0_clk {
 791                                                 #clock-cells = <0>;
 792                                                 reg = <54>;
 793                                                 atmel,clk-output-range = <0 83000000>;
 794                                         };
 795
 796                                         i2s1_clk: i2s1_clk {
 797                                                 #clock-cells = <0>;
 798                                                 reg = <55>;
 799                                                 atmel,clk-output-range = <0 83000000>;
 800                                         };
 801
 802                                         can0_clk: can0_clk {
 803                                                 #clock-cells = <0>;
 804                                                 reg = <56>;
 805                                                 atmel,clk-output-range = <0 83000000>;
 806                                         };
 807
 808                                         can1_clk: can1_clk {
 809                                                 #clock-cells = <0>;
 810                                                 reg = <57>;
 811                                                 atmel,clk-output-range = <0 83000000>;
 812                                         };
 813
 814                                         classd_clk: classd_clk {
 815                                                 #clock-cells = <0>;
 816                                                 reg = <59>;
 817                                                 atmel,clk-output-range = <0 83000000>;
 818                                         };
 819                                 };
 820
 821                                 periph64ck {
 822                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 823                                         #address-cells = <1>;
 824                                         #size-cells = <0>;
 825                                         clocks = <&mck>;
 826
 827                                         dma0_clk: dma0_clk {
 828                                                 #clock-cells = <0>;
 829                                                 reg = <6>;
 830                                         };
 831
 832                                         dma1_clk: dma1_clk {
 833                                                 #clock-cells = <0>;
 834                                                 reg = <7>;
 835                                         };
 836
 837                                         aes_clk: aes_clk {
 838                                                 #clock-cells = <0>;
 839                                                 reg = <9>;
 840                                         };
 841
 842                                         aesb_clk: aesb_clk {
 843                                                 #clock-cells = <0>;
 844                                                 reg = <10>;
 845                                         };
 846
 847                                         sha_clk: sha_clk {
 848                                                 #clock-cells = <0>;
 849                                                 reg = <12>;
 850                                         };
 851
 852                                         mpddr_clk: mpddr_clk {
 853                                                 #clock-cells = <0>;
 854                                                 reg = <13>;
 855                                         };
 856
 857                                         matrix0_clk: matrix0_clk {
 858                                                 #clock-cells = <0>;
 859                                                 reg = <15>;
 860                                         };
 861
 862                                         sdmmc0_hclk: sdmmc0_hclk {
 863                                                 #clock-cells = <0>;
 864                                                 reg = <31>;
 865                                         };
 866
 867                                         sdmmc1_hclk: sdmmc1_hclk {
 868                                                 #clock-cells = <0>;
 869                                                 reg = <32>;
 870                                         };
 871
 872                                         lcdc_clk: lcdc_clk {
 873                                                 #clock-cells = <0>;
 874                                                 reg = <45>;
 875                                         };
 876
 877                                         isc_clk: isc_clk {
 878                                                 #clock-cells = <0>;
 879                                                 reg = <46>;
 880                                         };
 881
 882                                         qspi0_clk: qspi0_clk {
 883                                                 #clock-cells = <0>;
 884                                                 reg = <52>;
 885                                         };
 886
 887                                         qspi1_clk: qspi1_clk {
 888                                                 #clock-cells = <0>;
 889                                                 reg = <53>;
 890                                         };
 891                                 };
 892
 893                                 gck {
 894                                         compatible = "atmel,sama5d2-clk-generated";
 895                                         #address-cells = <1>;
 896                                         #size-cells = <0>;
 897                                         interrupt-parent = <&pmc>;
 898                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 899
 900                                         sdmmc0_gclk: sdmmc0_gclk {
 901                                                 #clock-cells = <0>;
 902                                                 reg = <31>;
 903                                         };
 904
 905                                         sdmmc1_gclk: sdmmc1_gclk {
 906                                                 #clock-cells = <0>;
 907                                                 reg = <32>;
 908                                         };
 909
 910                                         tcb0_gclk: tcb0_gclk {
 911                                                 #clock-cells = <0>;
 912                                                 reg = <35>;
 913                                                 atmel,clk-output-range = <0 83000000>;
 914                                         };
 915
 916                                         tcb1_gclk: tcb1_gclk {
 917                                                 #clock-cells = <0>;
 918                                                 reg = <36>;
 919                                                 atmel,clk-output-range = <0 83000000>;
 920                                         };
 921
 922                                         pwm_gclk: pwm_gclk {
 923                                                 #clock-cells = <0>;
 924                                                 reg = <38>;
 925                                                 atmel,clk-output-range = <0 83000000>;
 926                                         };
 927
 928                                         pdmic_gclk: pdmic_gclk {
 929                                                 #clock-cells = <0>;
 930                                                 reg = <48>;
 931                                         };
 932
 933                                         i2s0_gclk: i2s0_gclk {
 934                                                 #clock-cells = <0>;
 935                                                 reg = <54>;
 936                                         };
 937
 938                                         i2s1_gclk: i2s1_gclk {
 939                                                 #clock-cells = <0>;
 940                                                 reg = <55>;
 941                                         };
 942
 943                                         can0_gclk: can0_gclk {
 944                                                 #clock-cells = <0>;
 945                                                 reg = <56>;
 946                                                 atmel,clk-output-range = <0 80000000>;
 947                                         };
 948
 949                                         can1_gclk: can1_gclk {
 950                                                 #clock-cells = <0>;
 951                                                 reg = <57>;
 952                                                 atmel,clk-output-range = <0 80000000>;
 953                                         };
 954                                 };
 955                         };
 956
 957                         sha@f0028000 {
 958                                 compatible = "atmel,at91sam9g46-sha";
 959                                 reg = <0xf0028000 0x100>;
 960                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 961                                 dmas = <&dma0
 962                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 963                                          AT91_XDMAC_DT_PERID(30))>;
 964                                 dma-names = "tx";
 965                                 clocks = <&sha_clk>;
 966                                 clock-names = "sha_clk";
 967                                 status = "okay";
 968                         };
 969
 970                         aes@f002c000 {
 971                                 compatible = "atmel,at91sam9g46-aes";
 972                                 reg = <0xf002c000 0x100>;
 973                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
 974                                 dmas = <&dma0
 975                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 976                                          AT91_XDMAC_DT_PERID(26))>,
 977                                        <&dma0
 978                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 979                                          AT91_XDMAC_DT_PERID(27))>;
 980                                 dma-names = "tx", "rx";
 981                                 clocks = <&aes_clk>;
 982                                 clock-names = "aes_clk";
 983                                 status = "okay";
 984                         };
 985
 986                         spi0: spi@f8000000 {
 987                                 compatible = "atmel,at91rm9200-spi";
 988                                 reg = <0xf8000000 0x100>;
 989                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
 990                                 dmas = <&dma0
 991                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 992                                          AT91_XDMAC_DT_PERID(6))>,
 993                                        <&dma0
 994                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 995                                          AT91_XDMAC_DT_PERID(7))>;
 996                                 dma-names = "tx", "rx";
 997                                 clocks = <&spi0_clk>;
 998                                 clock-names = "spi_clk";
 999                                 atmel,fifo-size = <16>;
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002                                 status = "disabled";
1003                         };
1004
1005                         ssc0: ssc@f8004000 {
1006                                 compatible = "atmel,at91sam9g45-ssc";
1007                                 reg = <0xf8004000 0x4000>;
1008                                 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
1009                                 dmas = <&dma0
1010                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1011                                         AT91_XDMAC_DT_PERID(21))>,
1012                                        <&dma0
1013                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1014                                         AT91_XDMAC_DT_PERID(22))>;
1015                                 dma-names = "tx", "rx";
1016                                 clocks = <&ssc0_clk>;
1017                                 clock-names = "pclk";
1018                                 status = "disabled";
1019                         };
1020
1021                         macb0: ethernet@f8008000 {
1022                                 compatible = "atmel,sama5d2-gem";
1023                                 reg = <0xf8008000 0x1000>;
1024                                 interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3          /* Queue 0 */
1025                                               66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
1026                                               67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029                                 clocks = <&macb0_clk>, <&macb0_clk>;
1030                                 clock-names = "hclk", "pclk";
1031                                 status = "disabled";
1032                         };
1033
1034                         tcb0: timer@f800c000 {
1035                                 compatible = "atmel,at91sam9x5-tcb";
1036                                 reg = <0xf800c000 0x100>;
1037                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
1038                                 clocks = <&tcb0_clk>, <&clk32k>;
1039                                 clock-names = "t0_clk", "slow_clk";
1040                         };
1041
1042                         tcb1: timer@f8010000 {
1043                                 compatible = "atmel,at91sam9x5-tcb";
1044                                 reg = <0xf8010000 0x100>;
1045                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1046                                 clocks = <&tcb1_clk>, <&clk32k>;
1047                                 clock-names = "t0_clk", "slow_clk";
1048                         };
1049
1050                         hsmc: hsmc@f8014000 {
1051                                 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
1052                                 reg = <0xf8014000 0x1000>;
1053                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1054                                 clocks = <&hsmc_clk>;
1055                                 #address-cells = <1>;
1056                                 #size-cells = <1>;
1057                                 ranges;
1058
1059                                 pmecc: ecc-engine@ffffc070 {
1060                                         compatible = "atmel,sama5d2-pmecc";
1061                                         reg = <0xffffc070 0x490>,
1062                                               <0xffffc500 0x100>;
1063                                 };
1064                         };
1065
1066                         pdmic: pdmic@f8018000 {
1067                                 compatible = "atmel,sama5d2-pdmic";
1068                                 reg = <0xf8018000 0x124>;
1069                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
1070                                 dmas = <&dma0
1071                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1072                                         | AT91_XDMAC_DT_PERID(50))>;
1073                                 dma-names = "rx";
1074                                 clocks = <&pdmic_clk>, <&pdmic_gclk>;
1075                                 clock-names = "pclk", "gclk";
1076                                 status = "disabled";
1077                         };
1078
1079                         uart0: serial@f801c000 {
1080                                 compatible = "atmel,at91sam9260-usart";
1081                                 reg = <0xf801c000 0x100>;
1082                                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
1083                                 dmas = <&dma0
1084                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1085                                          AT91_XDMAC_DT_PERID(35))>,
1086                                        <&dma0
1087                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1088                                          AT91_XDMAC_DT_PERID(36))>;
1089                                 dma-names = "tx", "rx";
1090                                 clocks = <&uart0_clk>;
1091                                 clock-names = "usart";
1092                                 status = "disabled";
1093                         };
1094
1095                         uart1: serial@f8020000 {
1096                                 compatible = "atmel,at91sam9260-usart";
1097                                 reg = <0xf8020000 0x100>;
1098                                 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
1099                                 dmas = <&dma0
1100                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1101                                          AT91_XDMAC_DT_PERID(37))>,
1102                                        <&dma0
1103                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1104                                          AT91_XDMAC_DT_PERID(38))>;
1105                                 dma-names = "tx", "rx";
1106                                 clocks = <&uart1_clk>;
1107                                 clock-names = "usart";
1108                                 status = "disabled";
1109                         };
1110
1111                         uart2: serial@f8024000 {
1112                                 compatible = "atmel,at91sam9260-usart";
1113                                 reg = <0xf8024000 0x100>;
1114                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1115                                 dmas = <&dma0
1116                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1117                                          AT91_XDMAC_DT_PERID(39))>,
1118                                        <&dma0
1119                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1120                                          AT91_XDMAC_DT_PERID(40))>;
1121                                 dma-names = "tx", "rx";
1122                                 clocks = <&uart2_clk>;
1123                                 clock-names = "usart";
1124                                 status = "disabled";
1125                         };
1126
1127                         i2c0: i2c@f8028000 {
1128                                 compatible = "atmel,sama5d2-i2c";
1129                                 reg = <0xf8028000 0x100>;
1130                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1131                                 dmas = <&dma0
1132                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1133                                          AT91_XDMAC_DT_PERID(0))>,
1134                                        <&dma0
1135                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1136                                          AT91_XDMAC_DT_PERID(1))>;
1137                                 dma-names = "tx", "rx";
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 clocks = <&twi0_clk>;
1141                                 atmel,fifo-size = <16>;
1142                                 status = "disabled";
1143                         };
1144
1145                         pwm0: pwm@f802c000 {
1146                                 compatible = "atmel,sama5d2-pwm";
1147                                 reg = <0xf802c000 0x4000>;
1148                                 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
1149                                 #pwm-cells = <3>;
1150                                 clocks = <&pwm_clk>;
1151                         };
1152
1153                         sfr: sfr@f8030000 {
1154                                 compatible = "atmel,sama5d2-sfr", "syscon";
1155                                 reg = <0xf8030000 0x98>;
1156                         };
1157
1158                         flx0: flexcom@f8034000 {
1159                                 compatible = "atmel,sama5d2-flexcom";
1160                                 reg = <0xf8034000 0x200>;
1161                                 clocks = <&flx0_clk>;
1162                                 #address-cells = <1>;
1163                                 #size-cells = <1>;
1164                                 ranges = <0x0 0xf8034000 0x800>;
1165                                 status = "disabled";
1166                         };
1167
1168                         flx1: flexcom@f8038000 {
1169                                 compatible = "atmel,sama5d2-flexcom";
1170                                 reg = <0xf8038000 0x200>;
1171                                 clocks = <&flx1_clk>;
1172                                 #address-cells = <1>;
1173                                 #size-cells = <1>;
1174                                 ranges = <0x0 0xf8038000 0x800>;
1175                                 status = "disabled";
1176                         };
1177
1178                         securam: sram@f8044000 {
1179                                 compatible = "atmel,sama5d2-securam", "mmio-sram";
1180                                 reg = <0xf8044000 0x1420>;
1181                                 clocks = <&securam_clk>;
1182                                 #address-cells = <1>;
1183                                 #size-cells = <1>;
1184                                 ranges = <0 0xf8044000 0x1420>;
1185                         };
1186
1187                         rstc@f8048000 {
1188                                 compatible = "atmel,sama5d3-rstc";
1189                                 reg = <0xf8048000 0x10>;
1190                                 clocks = <&clk32k>;
1191                         };
1192
1193                         shdwc@f8048010 {
1194                                 compatible = "atmel,sama5d2-shdwc";
1195                                 reg = <0xf8048010 0x10>;
1196                                 clocks = <&clk32k>;
1197                                 #address-cells = <1>;
1198                                 #size-cells = <0>;
1199                                 atmel,wakeup-rtc-timer;
1200                         };
1201
1202                         pit: timer@f8048030 {
1203                                 compatible = "atmel,at91sam9260-pit";
1204                                 reg = <0xf8048030 0x10>;
1205                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1206                                 clocks = <&h32ck>;
1207                         };
1208
1209                         watchdog@f8048040 {
1210                                 compatible = "atmel,sama5d4-wdt";
1211                                 reg = <0xf8048040 0x10>;
1212                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1213                                 clocks = <&clk32k>;
1214                                 status = "disabled";
1215                         };
1216
1217                         clk32k: sckc@f8048050 {
1218                                 compatible = "atmel,sama5d4-sckc";
1219                                 reg = <0xf8048050 0x4>;
1220
1221                                 clocks = <&slow_xtal>;
1222                                 #clock-cells = <0>;
1223                         };
1224
1225                         rtc@f80480b0 {
1226                                 compatible = "atmel,at91rm9200-rtc";
1227                                 reg = <0xf80480b0 0x30>;
1228                                 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1229                                 clocks = <&clk32k>;
1230                         };
1231
1232                         can0: can@f8054000 {
1233                                 compatible = "bosch,m_can";
1234                                 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
1235                                 reg-names = "m_can", "message_ram";
1236                                 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
1237                                              <64 IRQ_TYPE_LEVEL_HIGH 7>;
1238                                 interrupt-names = "int0", "int1";
1239                                 clocks = <&can0_clk>, <&can0_gclk>;
1240                                 clock-names = "hclk", "cclk";
1241                                 assigned-clocks = <&can0_gclk>;
1242                                 assigned-clock-parents = <&utmi>;
1243                                 assigned-clock-rates = <40000000>;
1244                                 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
1245                                 status = "disabled";
1246                         };
1247
1248                         spi1: spi@fc000000 {
1249                                 compatible = "atmel,at91rm9200-spi";
1250                                 reg = <0xfc000000 0x100>;
1251                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1252                                 dmas = <&dma0
1253                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1254                                          AT91_XDMAC_DT_PERID(8))>,
1255                                        <&dma0
1256                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1257                                          AT91_XDMAC_DT_PERID(9))>;
1258                                 dma-names = "tx", "rx";
1259                                 clocks = <&spi1_clk>;
1260                                 clock-names = "spi_clk";
1261                                 atmel,fifo-size = <16>;
1262                                 #address-cells = <1>;
1263                                 #size-cells = <0>;
1264                                 status = "disabled";
1265                         };
1266
1267                         uart3: serial@fc008000 {
1268                                 compatible = "atmel,at91sam9260-usart";
1269                                 reg = <0xfc008000 0x100>;
1270                                 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1271                                 dmas = <&dma1
1272                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1273                                          AT91_XDMAC_DT_PERID(41))>,
1274                                        <&dma1
1275                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1276                                          AT91_XDMAC_DT_PERID(42))>;
1277                                 dma-names = "tx", "rx";
1278                                 clocks = <&uart3_clk>;
1279                                 clock-names = "usart";
1280                                 status = "disabled";
1281                         };
1282
1283                         uart4: serial@fc00c000 {
1284                                 compatible = "atmel,at91sam9260-usart";
1285                                 reg = <0xfc00c000 0x100>;
1286                                 dmas = <&dma0
1287                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1288                                          AT91_XDMAC_DT_PERID(43))>,
1289                                        <&dma0
1290                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1291                                          AT91_XDMAC_DT_PERID(44))>;
1292                                 dma-names = "tx", "rx";
1293                                 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1294                                 clocks = <&uart4_clk>;
1295                                 clock-names = "usart";
1296                                 status = "disabled";
1297                         };
1298
1299                         flx2: flexcom@fc010000 {
1300                                 compatible = "atmel,sama5d2-flexcom";
1301                                 reg = <0xfc010000 0x200>;
1302                                 clocks = <&flx2_clk>;
1303                                 #address-cells = <1>;
1304                                 #size-cells = <1>;
1305                                 ranges = <0x0 0xfc010000 0x800>;
1306                                 status = "disabled";
1307                         };
1308
1309                         flx3: flexcom@fc014000 {
1310                                 compatible = "atmel,sama5d2-flexcom";
1311                                 reg = <0xfc014000 0x200>;
1312                                 clocks = <&flx3_clk>;
1313                                 #address-cells = <1>;
1314                                 #size-cells = <1>;
1315                                 ranges = <0x0 0xfc014000 0x800>;
1316                                 status = "disabled";
1317                         };
1318
1319                         flx4: flexcom@fc018000 {
1320                                 compatible = "atmel,sama5d2-flexcom";
1321                                 reg = <0xfc018000 0x200>;
1322                                 clocks = <&flx4_clk>;
1323                                 #address-cells = <1>;
1324                                 #size-cells = <1>;
1325                                 ranges = <0x0 0xfc018000 0x800>;
1326                                 status = "disabled";
1327                         };
1328
1329                         trng@fc01c000 {
1330                                 compatible = "atmel,at91sam9g45-trng";
1331                                 reg = <0xfc01c000 0x100>;
1332                                 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1333                                 clocks = <&trng_clk>;
1334                         };
1335
1336                         aic: interrupt-controller@fc020000 {
1337                                 #interrupt-cells = <3>;
1338                                 compatible = "atmel,sama5d2-aic";
1339                                 interrupt-controller;
1340                                 reg = <0xfc020000 0x200>;
1341                                 atmel,external-irqs = <49>;
1342                         };
1343
1344                         i2c1: i2c@fc028000 {
1345                                 compatible = "atmel,sama5d2-i2c";
1346                                 reg = <0xfc028000 0x100>;
1347                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1348                                 dmas = <&dma0
1349                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1350                                          AT91_XDMAC_DT_PERID(2))>,
1351                                        <&dma0
1352                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1353                                          AT91_XDMAC_DT_PERID(3))>;
1354                                 dma-names = "tx", "rx";
1355                                 #address-cells = <1>;
1356                                 #size-cells = <0>;
1357                                 clocks = <&twi1_clk>;
1358                                 atmel,fifo-size = <16>;
1359                                 status = "disabled";
1360                         };
1361
1362                         adc: adc@fc030000 {
1363                                 compatible = "atmel,sama5d2-adc";
1364                                 reg = <0xfc030000 0x100>;
1365                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1366                                 clocks = <&adc_clk>;
1367                                 clock-names = "adc_clk";
1368                                 atmel,min-sample-rate-hz = <200000>;
1369                                 atmel,max-sample-rate-hz = <20000000>;
1370                                 atmel,startup-time-ms = <4>;
1371                                 status = "disabled";
1372                         };
1373
1374                         pioA: pinctrl@fc038000 {
1375                                 compatible = "atmel,sama5d2-pinctrl";
1376                                 reg = <0xfc038000 0x600>;
1377                                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1378                                              <68 IRQ_TYPE_LEVEL_HIGH 7>,
1379                                              <69 IRQ_TYPE_LEVEL_HIGH 7>,
1380                                              <70 IRQ_TYPE_LEVEL_HIGH 7>;
1381                                 interrupt-controller;
1382                                 #interrupt-cells = <2>;
1383                                 gpio-controller;
1384                                 #gpio-cells = <2>;
1385                                 clocks = <&pioA_clk>;
1386                         };
1387
1388                         secumod@fc040000 {
1389                                 compatible = "atmel,sama5d2-secumod", "syscon";
1390                                 reg = <0xfc040000 0x100>;
1391                         };
1392
1393                         tdes@fc044000 {
1394                                 compatible = "atmel,at91sam9g46-tdes";
1395                                 reg = <0xfc044000 0x100>;
1396                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1397                                 dmas = <&dma0
1398                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1399                                          AT91_XDMAC_DT_PERID(28))>,
1400                                        <&dma0
1401                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1402                                          AT91_XDMAC_DT_PERID(29))>;
1403                                 dma-names = "tx", "rx";
1404                                 clocks = <&tdes_clk>;
1405                                 clock-names = "tdes_clk";
1406                                 status = "okay";
1407                         };
1408
1409                         can1: can@fc050000 {
1410                                 compatible = "bosch,m_can";
1411                                 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1412                                 reg-names = "m_can", "message_ram";
1413                                 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1414                                              <65 IRQ_TYPE_LEVEL_HIGH 7>;
1415                                 interrupt-names = "int0", "int1";
1416                                 clocks = <&can1_clk>, <&can1_gclk>;
1417                                 clock-names = "hclk", "cclk";
1418                                 assigned-clocks = <&can1_gclk>;
1419                                 assigned-clock-parents = <&utmi>;
1420                                 assigned-clock-rates = <40000000>;
1421                                 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1422                                 status = "disabled";
1423                         };
1424
1425                         sfrbu: sfr@fc05c000 {
1426                                 compatible = "atmel,sama5d2-sfrbu", "syscon";
1427                                 reg = <0xfc05c000 0x20>;
1428                         };
1429
1430                         chipid@fc069000 {
1431                                 compatible = "atmel,sama5d2-chipid";
1432                                 reg = <0xfc069000 0x8>;
1433                         };
1434                 };
1435         };
1436 };