arch/arm/boot/dts/sama5d2.dtsi

   1 /*
   2  * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
   3  *
   4  *  Copyright (C) 2015 Atmel,
   5  *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/dma/at91.h>
  48 #include <dt-bindings/interrupt-controller/irq.h>
  49 #include <dt-bindings/clock/at91.h>
  50
  51 / {
  52         model = "Atmel SAMA5D2 family SoC";
  53         compatible = "atmel,sama5d2";
  54         interrupt-parent = <&aic>;
  55
  56         aliases {
  57                 serial0 = &uart1;
  58                 serial1 = &uart3;
  59                 tcb0 = &tcb0;
  60                 tcb1 = &tcb1;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a5";
  70                         reg = <0>;
  71                         next-level-cache = <&L2>;
  72                 };
  73         };
  74
  75         pmu {
  76                 compatible = "arm,cortex-a5-pmu";
  77                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
  78         };
  79
  80         etb {
  81                 compatible = "arm,coresight-etb10", "arm,primecell";
  82                 reg = <0x740000 0x1000>;
  83
  84                 clocks = <&mck>;
  85                 clock-names = "apb_pclk";
  86
  87                 port {
  88                         etb_in: endpoint {
  89                                 slave-mode;
  90                                 remote-endpoint = <&etm_out>;
  91                         };
  92                 };
  93         };
  94
  95         etm {
  96                 compatible = "arm,coresight-etm3x", "arm,primecell";
  97                 reg = <0x73C000 0x1000>;
  98
  99                 clocks = <&mck>;
 100                 clock-names = "apb_pclk";
 101
 102                 port {
 103                         etm_out: endpoint {
 104                                 remote-endpoint = <&etb_in>;
 105                         };
 106                 };
 107         };
 108
 109         memory {
 110                 reg = <0x20000000 0x20000000>;
 111         };
 112
 113         clocks {
 114                 slow_xtal: slow_xtal {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                 };
 119
 120                 main_xtal: main_xtal {
 121                         compatible = "fixed-clock";
 122                         #clock-cells = <0>;
 123                         clock-frequency = <0>;
 124                 };
 125         };
 126
 127         ns_sram: sram@00200000 {
 128                 compatible = "mmio-sram";
 129                 reg = <0x00200000 0x20000>;
 130         };
 131
 132         ahb {
 133                 compatible = "simple-bus";
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 ranges;
 137
 138                 usb0: gadget@00300000 {
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         compatible = "atmel,sama5d3-udc";
 142                         reg = <0x00300000 0x100000
 143                                0xfc02c000 0x400>;
 144                         interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
 145                         clocks = <&udphs_clk>, <&utmi>;
 146                         clock-names = "pclk", "hclk";
 147                         status = "disabled";
 148
 149                         ep@0 {
 150                                 reg = <0>;
 151                                 atmel,fifo-size = <64>;
 152                                 atmel,nb-banks = <1>;
 153                         };
 154
 155                         ep@1 {
 156                                 reg = <1>;
 157                                 atmel,fifo-size = <1024>;
 158                                 atmel,nb-banks = <3>;
 159                                 atmel,can-dma;
 160                                 atmel,can-isoc;
 161                         };
 162
 163                         ep@2 {
 164                                 reg = <2>;
 165                                 atmel,fifo-size = <1024>;
 166                                 atmel,nb-banks = <3>;
 167                                 atmel,can-dma;
 168                                 atmel,can-isoc;
 169                         };
 170
 171                         ep@3 {
 172                                 reg = <3>;
 173                                 atmel,fifo-size = <1024>;
 174                                 atmel,nb-banks = <2>;
 175                                 atmel,can-dma;
 176                                 atmel,can-isoc;
 177                         };
 178
 179                         ep@4 {
 180                                 reg = <4>;
 181                                 atmel,fifo-size = <1024>;
 182                                 atmel,nb-banks = <2>;
 183                                 atmel,can-dma;
 184                                 atmel,can-isoc;
 185                         };
 186
 187                         ep@5 {
 188                                 reg = <5>;
 189                                 atmel,fifo-size = <1024>;
 190                                 atmel,nb-banks = <2>;
 191                                 atmel,can-dma;
 192                                 atmel,can-isoc;
 193                         };
 194
 195                         ep@6 {
 196                                 reg = <6>;
 197                                 atmel,fifo-size = <1024>;
 198                                 atmel,nb-banks = <2>;
 199                                 atmel,can-dma;
 200                                 atmel,can-isoc;
 201                         };
 202
 203                         ep@7 {
 204                                 reg = <7>;
 205                                 atmel,fifo-size = <1024>;
 206                                 atmel,nb-banks = <2>;
 207                                 atmel,can-dma;
 208                                 atmel,can-isoc;
 209                         };
 210
 211                         ep@8 {
 212                                 reg = <8>;
 213                                 atmel,fifo-size = <1024>;
 214                                 atmel,nb-banks = <2>;
 215                                 atmel,can-isoc;
 216                         };
 217
 218                         ep@9 {
 219                                 reg = <9>;
 220                                 atmel,fifo-size = <1024>;
 221                                 atmel,nb-banks = <2>;
 222                                 atmel,can-isoc;
 223                         };
 224
 225                         ep@10 {
 226                                 reg = <10>;
 227                                 atmel,fifo-size = <1024>;
 228                                 atmel,nb-banks = <2>;
 229                                 atmel,can-isoc;
 230                         };
 231
 232                         ep@11 {
 233                                 reg = <11>;
 234                                 atmel,fifo-size = <1024>;
 235                                 atmel,nb-banks = <2>;
 236                                 atmel,can-isoc;
 237                         };
 238
 239                         ep@12 {
 240                                 reg = <12>;
 241                                 atmel,fifo-size = <1024>;
 242                                 atmel,nb-banks = <2>;
 243                                 atmel,can-isoc;
 244                         };
 245
 246                         ep@13 {
 247                                 reg = <13>;
 248                                 atmel,fifo-size = <1024>;
 249                                 atmel,nb-banks = <2>;
 250                                 atmel,can-isoc;
 251                         };
 252
 253                         ep@14 {
 254                                 reg = <14>;
 255                                 atmel,fifo-size = <1024>;
 256                                 atmel,nb-banks = <2>;
 257                                 atmel,can-isoc;
 258                         };
 259
 260                         ep@15 {
 261                                 reg = <15>;
 262                                 atmel,fifo-size = <1024>;
 263                                 atmel,nb-banks = <2>;
 264                                 atmel,can-isoc;
 265                         };
 266                 };
 267
 268                 usb1: ohci@00400000 {
 269                         compatible = "atmel,sama5d2-ohci", "usb-ohci";
 270                         reg = <0x00400000 0x100000>;
 271                         interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
 272                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
 273                         clock-names = "ohci_clk", "hclk", "uhpck";
 274                         status = "disabled";
 275                 };
 276
 277                 usb2: ehci@00500000 {
 278                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 279                         reg = <0x00500000 0x100000>;
 280                         interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
 281                         clocks = <&utmi>, <&uhphs_clk>;
 282                         clock-names = "usb_clk", "ehci_clk";
 283                         status = "disabled";
 284                 };
 285
 286                 L2: cache-controller@00a00000 {
 287                         compatible = "arm,pl310-cache";
 288                         reg = <0x00a00000 0x1000>;
 289                         interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
 290                         cache-unified;
 291                         cache-level = <2>;
 292                 };
 293
 294                 nand0: nand@80000000 {
 295                         compatible = "atmel,sama5d2-nand";
 296                         #address-cells = <1>;
 297                         #size-cells = <1>;
 298                         ranges;
 299                         reg = < /* EBI CS3 */
 300                                 0x80000000 0x08000000
 301                                 /* SMC PMECC regs */
 302                                 0xf8014070 0x00000490
 303                                 /* SMC PMECC Error Location regs */
 304                                 0xf8014500 0x00000200
 305                                 /* ROM Galois tables */
 306                                 0x00040000 0x00018000
 307                                 >;
 308                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
 309                         atmel,nand-addr-offset = <21>;
 310                         atmel,nand-cmd-offset = <22>;
 311                         atmel,nand-has-dma;
 312                         atmel,has-pmecc;
 313                         atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
 314                         status = "disabled";
 315
 316                         nfc@c0000000 {
 317                                 compatible = "atmel,sama5d3-nfc";
 318                                 #address-cells = <1>;
 319                                 #size-cells = <1>;
 320                                 reg = < /* NFC Command Registers */
 321                                         0xc0000000 0x08000000
 322                                         /* NFC HSMC regs */
 323                                         0xf8014000 0x00000070
 324                                         /* NFC SRAM banks */
 325                                         0x00100000 0x00100000
 326                                         >;
 327                                 clocks = <&hsmc_clk>;
 328                                 atmel,write-by-sram;
 329                         };
 330                 };
 331
 332                 sdmmc0: sdio-host@a0000000 {
 333                         compatible = "atmel,sama5d2-sdhci";
 334                         reg = <0xa0000000 0x300>;
 335                         interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
 336                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
 337                         clock-names = "hclock", "multclk", "baseclk";
 338                         status = "disabled";
 339                 };
 340
 341                 sdmmc1: sdio-host@b0000000 {
 342                         compatible = "atmel,sama5d2-sdhci";
 343                         reg = <0xb0000000 0x300>;
 344                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
 345                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
 346                         clock-names = "hclock", "multclk", "baseclk";
 347                         status = "disabled";
 348                 };
 349
 350                 apb {
 351                         compatible = "simple-bus";
 352                         #address-cells = <1>;
 353                         #size-cells = <1>;
 354                         ranges;
 355
 356                         hlcdc: hlcdc@f0000000 {
 357                                 compatible = "atmel,sama5d2-hlcdc";
 358                                 reg = <0xf0000000 0x2000>;
 359                                 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
 360                                 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
 361                                 clock-names = "periph_clk","sys_clk", "slow_clk";
 362                                 status = "disabled";
 363
 364                                 hlcdc-display-controller {
 365                                         compatible = "atmel,hlcdc-display-controller";
 366                                         #address-cells = <1>;
 367                                         #size-cells = <0>;
 368
 369                                         port@0 {
 370                                                 #address-cells = <1>;
 371                                                 #size-cells = <0>;
 372                                                 reg = <0>;
 373                                         };
 374                                 };
 375
 376                                 hlcdc_pwm: hlcdc-pwm {
 377                                         compatible = "atmel,hlcdc-pwm";
 378                                         #pwm-cells = <3>;
 379                                 };
 380                         };
 381
 382                         ramc0: ramc@f000c000 {
 383                                 compatible = "atmel,sama5d3-ddramc";
 384                                 reg = <0xf000c000 0x200>;
 385                                 clocks = <&ddrck>, <&mpddr_clk>;
 386                                 clock-names = "ddrck", "mpddr";
 387                         };
 388
 389                         dma0: dma-controller@f0010000 {
 390                                 compatible = "atmel,sama5d4-dma";
 391                                 reg = <0xf0010000 0x1000>;
 392                                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
 393                                 #dma-cells = <1>;
 394                                 clocks = <&dma0_clk>;
 395                                 clock-names = "dma_clk";
 396                         };
 397
 398                         pmc: pmc@f0014000 {
 399                                 compatible = "atmel,sama5d2-pmc", "syscon";
 400                                 reg = <0xf0014000 0x160>;
 401                                 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
 402                                 interrupt-controller;
 403                                 #address-cells = <1>;
 404                                 #size-cells = <0>;
 405                                 #interrupt-cells = <1>;
 406
 407                                 main_rc_osc: main_rc_osc {
 408                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 409                                         #clock-cells = <0>;
 410                                         interrupt-parent = <&pmc>;
 411                                         interrupts = <AT91_PMC_MOSCRCS>;
 412                                         clock-frequency = <12000000>;
 413                                         clock-accuracy = <100000000>;
 414                                 };
 415
 416                                 main_osc: main_osc {
 417                                         compatible = "atmel,at91rm9200-clk-main-osc";
 418                                         #clock-cells = <0>;
 419                                         interrupt-parent = <&pmc>;
 420                                         interrupts = <AT91_PMC_MOSCS>;
 421                                         clocks = <&main_xtal>;
 422                                 };
 423
 424                                 main: mainck {
 425                                         compatible = "atmel,at91sam9x5-clk-main";
 426                                         #clock-cells = <0>;
 427                                         interrupt-parent = <&pmc>;
 428                                         interrupts = <AT91_PMC_MOSCSELS>;
 429                                         clocks = <&main_rc_osc &main_osc>;
 430                                 };
 431
 432                                 plla: pllack {
 433                                         compatible = "atmel,sama5d3-clk-pll";
 434                                         #clock-cells = <0>;
 435                                         interrupt-parent = <&pmc>;
 436                                         interrupts = <AT91_PMC_LOCKA>;
 437                                         clocks = <&main>;
 438                                         reg = <0>;
 439                                         atmel,clk-input-range = <12000000 12000000>;
 440                                         #atmel,pll-clk-output-range-cells = <4>;
 441                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 442                                 };
 443
 444                                 plladiv: plladivck {
 445                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 446                                         #clock-cells = <0>;
 447                                         clocks = <&plla>;
 448                                 };
 449
 450                                 utmi: utmick {
 451                                         compatible = "atmel,at91sam9x5-clk-utmi";
 452                                         #clock-cells = <0>;
 453                                         interrupt-parent = <&pmc>;
 454                                         interrupts = <AT91_PMC_LOCKU>;
 455                                         clocks = <&main>;
 456                                 };
 457
 458                                 mck: masterck {
 459                                         compatible = "atmel,at91sam9x5-clk-master";
 460                                         #clock-cells = <0>;
 461                                         interrupt-parent = <&pmc>;
 462                                         interrupts = <AT91_PMC_MCKRDY>;
 463                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 464                                         atmel,clk-output-range = <124000000 166000000>;
 465                                         atmel,clk-divisors = <1 2 4 3>;
 466                                 };
 467
 468                                 h32ck: h32mxck {
 469                                         #clock-cells = <0>;
 470                                         compatible = "atmel,sama5d4-clk-h32mx";
 471                                         clocks = <&mck>;
 472                                 };
 473
 474                                 usb: usbck {
 475                                         compatible = "atmel,at91sam9x5-clk-usb";
 476                                         #clock-cells = <0>;
 477                                         clocks = <&plladiv>, <&utmi>;
 478                                 };
 479
 480                                 prog: progck {
 481                                         compatible = "atmel,at91sam9x5-clk-programmable";
 482                                         #address-cells = <1>;
 483                                         #size-cells = <0>;
 484                                         interrupt-parent = <&pmc>;
 485                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 486
 487                                         prog0: prog0 {
 488                                                 #clock-cells = <0>;
 489                                                 reg = <0>;
 490                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 491                                         };
 492
 493                                         prog1: prog1 {
 494                                                 #clock-cells = <0>;
 495                                                 reg = <1>;
 496                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 497                                         };
 498
 499                                         prog2: prog2 {
 500                                                 #clock-cells = <0>;
 501                                                 reg = <2>;
 502                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 503                                         };
 504                                 };
 505
 506                                 systemck {
 507                                         compatible = "atmel,at91rm9200-clk-system";
 508                                         #address-cells = <1>;
 509                                         #size-cells = <0>;
 510
 511                                         ddrck: ddrck {
 512                                                 #clock-cells = <0>;
 513                                                 reg = <2>;
 514                                                 clocks = <&mck>;
 515                                         };
 516
 517                                         lcdck: lcdck {
 518                                                 #clock-cells = <0>;
 519                                                 reg = <3>;
 520                                                 clocks = <&mck>;
 521                                         };
 522
 523                                         uhpck: uhpck {
 524                                                 #clock-cells = <0>;
 525                                                 reg = <6>;
 526                                                 clocks = <&usb>;
 527                                         };
 528
 529                                         udpck: udpck {
 530                                                 #clock-cells = <0>;
 531                                                 reg = <7>;
 532                                                 clocks = <&usb>;
 533                                         };
 534
 535                                         pck0: pck0 {
 536                                                 #clock-cells = <0>;
 537                                                 reg = <8>;
 538                                                 clocks = <&prog0>;
 539                                         };
 540
 541                                         pck1: pck1 {
 542                                                 #clock-cells = <0>;
 543                                                 reg = <9>;
 544                                                 clocks = <&prog1>;
 545                                         };
 546
 547                                         pck2: pck2 {
 548                                                 #clock-cells = <0>;
 549                                                 reg = <10>;
 550                                                 clocks = <&prog2>;
 551                                         };
 552
 553                                         iscck: iscck {
 554                                                 #clock-cells = <0>;
 555                                                 reg = <18>;
 556                                                 clocks = <&mck>;
 557                                         };
 558                                 };
 559
 560                                 periph32ck {
 561                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 562                                         #address-cells = <1>;
 563                                         #size-cells = <0>;
 564                                         clocks = <&h32ck>;
 565
 566                                         macb0_clk: macb0_clk {
 567                                                 #clock-cells = <0>;
 568                                                 reg = <5>;
 569                                                 atmel,clk-output-range = <0 83000000>;
 570                                         };
 571
 572                                         tdes_clk: tdes_clk {
 573                                                 #clock-cells = <0>;
 574                                                 reg = <11>;
 575                                                 atmel,clk-output-range = <0 83000000>;
 576                                         };
 577
 578                                         matrix1_clk: matrix1_clk {
 579                                                 #clock-cells = <0>;
 580                                                 reg = <14>;
 581                                         };
 582
 583                                         hsmc_clk: hsmc_clk {
 584                                                 #clock-cells = <0>;
 585                                                 reg = <17>;
 586                                         };
 587
 588                                         pioA_clk: pioA_clk {
 589                                                 #clock-cells = <0>;
 590                                                 reg = <18>;
 591                                                 atmel,clk-output-range = <0 83000000>;
 592                                         };
 593
 594                                         flx0_clk: flx0_clk {
 595                                                 #clock-cells = <0>;
 596                                                 reg = <19>;
 597                                                 atmel,clk-output-range = <0 83000000>;
 598                                         };
 599
 600                                         flx1_clk: flx1_clk {
 601                                                 #clock-cells = <0>;
 602                                                 reg = <20>;
 603                                                 atmel,clk-output-range = <0 83000000>;
 604                                         };
 605
 606                                         flx2_clk: flx2_clk {
 607                                                 #clock-cells = <0>;
 608                                                 reg = <21>;
 609                                                 atmel,clk-output-range = <0 83000000>;
 610                                         };
 611
 612                                         flx3_clk: flx3_clk {
 613                                                 #clock-cells = <0>;
 614                                                 reg = <22>;
 615                                                 atmel,clk-output-range = <0 83000000>;
 616                                         };
 617
 618                                         flx4_clk: flx4_clk {
 619                                                 #clock-cells = <0>;
 620                                                 reg = <23>;
 621                                                 atmel,clk-output-range = <0 83000000>;
 622                                         };
 623
 624                                         uart0_clk: uart0_clk {
 625                                                 #clock-cells = <0>;
 626                                                 reg = <24>;
 627                                                 atmel,clk-output-range = <0 83000000>;
 628                                         };
 629
 630                                         uart1_clk: uart1_clk {
 631                                                 #clock-cells = <0>;
 632                                                 reg = <25>;
 633                                                 atmel,clk-output-range = <0 83000000>;
 634                                         };
 635
 636                                         uart2_clk: uart2_clk {
 637                                                 #clock-cells = <0>;
 638                                                 reg = <26>;
 639                                                 atmel,clk-output-range = <0 83000000>;
 640                                         };
 641
 642                                         uart3_clk: uart3_clk {
 643                                                 #clock-cells = <0>;
 644                                                 reg = <27>;
 645                                                 atmel,clk-output-range = <0 83000000>;
 646                                         };
 647
 648                                         uart4_clk: uart4_clk {
 649                                                 #clock-cells = <0>;
 650                                                 reg = <28>;
 651                                                 atmel,clk-output-range = <0 83000000>;
 652                                         };
 653
 654                                         twi0_clk: twi0_clk {
 655                                                 reg = <29>;
 656                                                 #clock-cells = <0>;
 657                                                 atmel,clk-output-range = <0 83000000>;
 658                                         };
 659
 660                                         twi1_clk: twi1_clk {
 661                                                 #clock-cells = <0>;
 662                                                 reg = <30>;
 663                                                 atmel,clk-output-range = <0 83000000>;
 664                                         };
 665
 666                                         spi0_clk: spi0_clk {
 667                                                 #clock-cells = <0>;
 668                                                 reg = <33>;
 669                                                 atmel,clk-output-range = <0 83000000>;
 670                                         };
 671
 672                                         spi1_clk: spi1_clk {
 673                                                 #clock-cells = <0>;
 674                                                 reg = <34>;
 675                                                 atmel,clk-output-range = <0 83000000>;
 676                                         };
 677
 678                                         tcb0_clk: tcb0_clk {
 679                                                 #clock-cells = <0>;
 680                                                 reg = <35>;
 681                                                 atmel,clk-output-range = <0 83000000>;
 682                                         };
 683
 684                                         tcb1_clk: tcb1_clk {
 685                                                 #clock-cells = <0>;
 686                                                 reg = <36>;
 687                                                 atmel,clk-output-range = <0 83000000>;
 688                                         };
 689
 690                                         pwm_clk: pwm_clk {
 691                                                 #clock-cells = <0>;
 692                                                 reg = <38>;
 693                                                 atmel,clk-output-range = <0 83000000>;
 694                                         };
 695
 696                                         adc_clk: adc_clk {
 697                                                 #clock-cells = <0>;
 698                                                 reg = <40>;
 699                                                 atmel,clk-output-range = <0 83000000>;
 700                                         };
 701
 702                                         uhphs_clk: uhphs_clk {
 703                                                 #clock-cells = <0>;
 704                                                 reg = <41>;
 705                                                 atmel,clk-output-range = <0 83000000>;
 706                                         };
 707
 708                                         udphs_clk: udphs_clk {
 709                                                 #clock-cells = <0>;
 710                                                 reg = <42>;
 711                                                 atmel,clk-output-range = <0 83000000>;
 712                                         };
 713
 714                                         ssc0_clk: ssc0_clk {
 715                                                 #clock-cells = <0>;
 716                                                 reg = <43>;
 717                                                 atmel,clk-output-range = <0 83000000>;
 718                                         };
 719
 720                                         ssc1_clk: ssc1_clk {
 721                                                 #clock-cells = <0>;
 722                                                 reg = <44>;
 723                                                 atmel,clk-output-range = <0 83000000>;
 724                                         };
 725
 726                                         trng_clk: trng_clk {
 727                                                 #clock-cells = <0>;
 728                                                 reg = <47>;
 729                                                 atmel,clk-output-range = <0 83000000>;
 730                                         };
 731
 732                                         pdmic_clk: pdmic_clk {
 733                                                 #clock-cells = <0>;
 734                                                 reg = <48>;
 735                                                 atmel,clk-output-range = <0 83000000>;
 736                                         };
 737
 738                                         i2s0_clk: i2s0_clk {
 739                                                 #clock-cells = <0>;
 740                                                 reg = <54>;
 741                                                 atmel,clk-output-range = <0 83000000>;
 742                                         };
 743
 744                                         i2s1_clk: i2s1_clk {
 745                                                 #clock-cells = <0>;
 746                                                 reg = <55>;
 747                                                 atmel,clk-output-range = <0 83000000>;
 748                                         };
 749
 750                                         classd_clk: classd_clk {
 751                                                 #clock-cells = <0>;
 752                                                 reg = <59>;
 753                                                 atmel,clk-output-range = <0 83000000>;
 754                                         };
 755                                 };
 756
 757                                 periph64ck {
 758                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 759                                         #address-cells = <1>;
 760                                         #size-cells = <0>;
 761                                         clocks = <&mck>;
 762
 763                                         dma0_clk: dma0_clk {
 764                                                 #clock-cells = <0>;
 765                                                 reg = <6>;
 766                                         };
 767
 768                                         dma1_clk: dma1_clk {
 769                                                 #clock-cells = <0>;
 770                                                 reg = <7>;
 771                                         };
 772
 773                                         aes_clk: aes_clk {
 774                                                 #clock-cells = <0>;
 775                                                 reg = <9>;
 776                                         };
 777
 778                                         aesb_clk: aesb_clk {
 779                                                 #clock-cells = <0>;
 780                                                 reg = <10>;
 781                                         };
 782
 783                                         sha_clk: sha_clk {
 784                                                 #clock-cells = <0>;
 785                                                 reg = <12>;
 786                                         };
 787
 788                                         mpddr_clk: mpddr_clk {
 789                                                 #clock-cells = <0>;
 790                                                 reg = <13>;
 791                                         };
 792
 793                                         matrix0_clk: matrix0_clk {
 794                                                 #clock-cells = <0>;
 795                                                 reg = <15>;
 796                                         };
 797
 798                                         sdmmc0_hclk: sdmmc0_hclk {
 799                                                 #clock-cells = <0>;
 800                                                 reg = <31>;
 801                                         };
 802
 803                                         sdmmc1_hclk: sdmmc1_hclk {
 804                                                 #clock-cells = <0>;
 805                                                 reg = <32>;
 806                                         };
 807
 808                                         lcdc_clk: lcdc_clk {
 809                                                 #clock-cells = <0>;
 810                                                 reg = <45>;
 811                                         };
 812
 813                                         isc_clk: isc_clk {
 814                                                 #clock-cells = <0>;
 815                                                 reg = <46>;
 816                                         };
 817
 818                                         qspi0_clk: qspi0_clk {
 819                                                 #clock-cells = <0>;
 820                                                 reg = <52>;
 821                                         };
 822
 823                                         qspi1_clk: qspi1_clk {
 824                                                 #clock-cells = <0>;
 825                                                 reg = <53>;
 826                                         };
 827                                 };
 828
 829                                 gck {
 830                                         compatible = "atmel,sama5d2-clk-generated";
 831                                         #address-cells = <1>;
 832                                         #size-cells = <0>;
 833                                         interrupt-parent = <&pmc>;
 834                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 835
 836                                         sdmmc0_gclk: sdmmc0_gclk {
 837                                                 #clock-cells = <0>;
 838                                                 reg = <31>;
 839                                         };
 840
 841                                         sdmmc1_gclk: sdmmc1_gclk {
 842                                                 #clock-cells = <0>;
 843                                                 reg = <32>;
 844                                         };
 845
 846                                         tcb0_gclk: tcb0_gclk {
 847                                                 #clock-cells = <0>;
 848                                                 reg = <35>;
 849                                                 atmel,clk-output-range = <0 83000000>;
 850                                         };
 851
 852                                         tcb1_gclk: tcb1_gclk {
 853                                                 #clock-cells = <0>;
 854                                                 reg = <36>;
 855                                                 atmel,clk-output-range = <0 83000000>;
 856                                         };
 857
 858                                         pwm_gclk: pwm_gclk {
 859                                                 #clock-cells = <0>;
 860                                                 reg = <38>;
 861                                                 atmel,clk-output-range = <0 83000000>;
 862                                         };
 863
 864                                         pdmic_gclk: pdmic_gclk {
 865                                                 #clock-cells = <0>;
 866                                                 reg = <48>;
 867                                         };
 868
 869                                         i2s0_gclk: i2s0_gclk {
 870                                                 #clock-cells = <0>;
 871                                                 reg = <54>;
 872                                         };
 873
 874                                         i2s1_gclk: i2s1_gclk {
 875                                                 #clock-cells = <0>;
 876                                                 reg = <55>;
 877                                         };
 878                                 };
 879                         };
 880
 881                         sha@f0028000 {
 882                                 compatible = "atmel,at91sam9g46-sha";
 883                                 reg = <0xf0028000 0x100>;
 884                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
 885                                 dmas = <&dma0
 886                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 887                                          AT91_XDMAC_DT_PERID(30))>;
 888                                 dma-names = "tx";
 889                                 clocks = <&sha_clk>;
 890                                 clock-names = "sha_clk";
 891                                 status = "okay";
 892                         };
 893
 894                         aes@f002c000 {
 895                                 compatible = "atmel,at91sam9g46-aes";
 896                                 reg = <0xf002c000 0x100>;
 897                                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
 898                                 dmas = <&dma0
 899                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 900                                          AT91_XDMAC_DT_PERID(26))>,
 901                                        <&dma0
 902                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 903                                          AT91_XDMAC_DT_PERID(27))>;
 904                                 dma-names = "tx", "rx";
 905                                 clocks = <&aes_clk>;
 906                                 clock-names = "aes_clk";
 907                                 status = "okay";
 908                         };
 909
 910                         spi0: spi@f8000000 {
 911                                 compatible = "atmel,at91rm9200-spi";
 912                                 reg = <0xf8000000 0x100>;
 913                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
 914                                 dmas = <&dma0
 915                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 916                                          AT91_XDMAC_DT_PERID(6))>,
 917                                        <&dma0
 918                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 919                                          AT91_XDMAC_DT_PERID(7))>;
 920                                 dma-names = "tx", "rx";
 921                                 clocks = <&spi0_clk>;
 922                                 clock-names = "spi_clk";
 923                                 atmel,fifo-size = <16>;
 924                                 #address-cells = <1>;
 925                                 #size-cells = <0>;
 926                                 status = "disabled";
 927                         };
 928
 929                         macb0: ethernet@f8008000 {
 930                                 compatible = "atmel,sama5d2-gem";
 931                                 reg = <0xf8008000 0x1000>;
 932                                 interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3          /* Queue 0 */
 933                                               66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
 934                                               67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
 935                                 #address-cells = <1>;
 936                                 #size-cells = <0>;
 937                                 clocks = <&macb0_clk>, <&macb0_clk>;
 938                                 clock-names = "hclk", "pclk";
 939                                 status = "disabled";
 940                         };
 941
 942                         tcb0: timer@f800c000 {
 943                                 compatible = "atmel,at91sam9x5-tcb";
 944                                 reg = <0xf800c000 0x100>;
 945                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
 946                                 clocks = <&tcb0_clk>, <&clk32k>;
 947                                 clock-names = "t0_clk", "slow_clk";
 948                         };
 949
 950                         tcb1: timer@f8010000 {
 951                                 compatible = "atmel,at91sam9x5-tcb";
 952                                 reg = <0xf8010000 0x100>;
 953                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
 954                                 clocks = <&tcb1_clk>, <&clk32k>;
 955                                 clock-names = "t0_clk", "slow_clk";
 956                         };
 957
 958                         pdmic: pdmic@f8018000 {
 959                                 compatible = "atmel,sama5d2-pdmic";
 960                                 reg = <0xf8018000 0x124>;
 961                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
 962                                 dmas = <&dma0
 963                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 964                                         | AT91_XDMAC_DT_PERID(50))>;
 965                                 dma-names = "rx";
 966                                 clocks = <&pdmic_clk>, <&pdmic_gclk>;
 967                                 clock-names = "pclk", "gclk";
 968                                 status = "disabled";
 969                         };
 970
 971                         uart0: serial@f801c000 {
 972                                 compatible = "atmel,at91sam9260-usart";
 973                                 reg = <0xf801c000 0x100>;
 974                                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
 975                                 dmas = <&dma0
 976                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 977                                          AT91_XDMAC_DT_PERID(35))>,
 978                                        <&dma0
 979                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 980                                          AT91_XDMAC_DT_PERID(36))>;
 981                                 dma-names = "tx", "rx";
 982                                 clocks = <&uart0_clk>;
 983                                 clock-names = "usart";
 984                                 status = "disabled";
 985                         };
 986
 987                         uart1: serial@f8020000 {
 988                                 compatible = "atmel,at91sam9260-usart";
 989                                 reg = <0xf8020000 0x100>;
 990                                 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
 991                                 dmas = <&dma0
 992                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 993                                          AT91_XDMAC_DT_PERID(37))>,
 994                                        <&dma0
 995                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
 996                                          AT91_XDMAC_DT_PERID(38))>;
 997                                 dma-names = "tx", "rx";
 998                                 clocks = <&uart1_clk>;
 999                                 clock-names = "usart";
1000                                 status = "disabled";
1001                         };
1002
1003                         uart2: serial@f8024000 {
1004                                 compatible = "atmel,at91sam9260-usart";
1005                                 reg = <0xf8024000 0x100>;
1006                                 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1007                                 dmas = <&dma0
1008                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1009                                          AT91_XDMAC_DT_PERID(39))>,
1010                                        <&dma0
1011                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1012                                          AT91_XDMAC_DT_PERID(40))>;
1013                                 dma-names = "tx", "rx";
1014                                 clocks = <&uart2_clk>;
1015                                 clock-names = "usart";
1016                                 status = "disabled";
1017                         };
1018
1019                         i2c0: i2c@f8028000 {
1020                                 compatible = "atmel,sama5d2-i2c";
1021                                 reg = <0xf8028000 0x100>;
1022                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1023                                 dmas = <&dma0
1024                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1025                                          AT91_XDMAC_DT_PERID(0))>,
1026                                        <&dma0
1027                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1028                                          AT91_XDMAC_DT_PERID(1))>;
1029                                 dma-names = "tx", "rx";
1030                                 #address-cells = <1>;
1031                                 #size-cells = <0>;
1032                                 clocks = <&twi0_clk>;
1033                                 status = "disabled";
1034                         };
1035
1036                         sfr: sfr@f8030000 {
1037                                 compatible = "atmel,sama5d2-sfr", "syscon";
1038                                 reg = <0xf8030000 0x98>;
1039                         };
1040
1041                         flx0: flexcom@f8034000 {
1042                                 compatible = "atmel,sama5d2-flexcom";
1043                                 reg = <0xf8034000 0x200>;
1044                                 clocks = <&flx0_clk>;
1045                                 #address-cells = <1>;
1046                                 #size-cells = <1>;
1047                                 ranges = <0x0 0xf8034000 0x800>;
1048                                 status = "disabled";
1049                         };
1050
1051                         flx1: flexcom@f8038000 {
1052                                 compatible = "atmel,sama5d2-flexcom";
1053                                 reg = <0xf8038000 0x200>;
1054                                 clocks = <&flx1_clk>;
1055                                 #address-cells = <1>;
1056                                 #size-cells = <1>;
1057                                 ranges = <0x0 0xf8038000 0x800>;
1058                                 status = "disabled";
1059                         };
1060
1061                         rstc@f8048000 {
1062                                 compatible = "atmel,sama5d3-rstc";
1063                                 reg = <0xf8048000 0x10>;
1064                                 clocks = <&clk32k>;
1065                         };
1066
1067                         shdwc@f8048010 {
1068                                 compatible = "atmel,sama5d2-shdwc";
1069                                 reg = <0xf8048010 0x10>;
1070                                 clocks = <&clk32k>;
1071                                 #address-cells = <1>;
1072                                 #size-cells = <0>;
1073                                 atmel,wakeup-rtc-timer;
1074                         };
1075
1076                         pit: timer@f8048030 {
1077                                 compatible = "atmel,at91sam9260-pit";
1078                                 reg = <0xf8048030 0x10>;
1079                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1080                                 clocks = <&h32ck>;
1081                         };
1082
1083                         watchdog@f8048040 {
1084                                 compatible = "atmel,sama5d4-wdt";
1085                                 reg = <0xf8048040 0x10>;
1086                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1087                                 clocks = <&clk32k>;
1088                                 status = "disabled";
1089                         };
1090
1091                         sckc@f8048050 {
1092                                 compatible = "atmel,at91sam9x5-sckc";
1093                                 reg = <0xf8048050 0x4>;
1094
1095                                 slow_rc_osc: slow_rc_osc {
1096                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1097                                         #clock-cells = <0>;
1098                                         clock-frequency = <32768>;
1099                                         clock-accuracy = <250000000>;
1100                                         atmel,startup-time-usec = <75>;
1101                                 };
1102
1103                                 slow_osc: slow_osc {
1104                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
1105                                         #clock-cells = <0>;
1106                                         clocks = <&slow_xtal>;
1107                                         atmel,startup-time-usec = <1200000>;
1108                                 };
1109
1110                                 clk32k: slowck {
1111                                         compatible = "atmel,at91sam9x5-clk-slow";
1112                                         #clock-cells = <0>;
1113                                         clocks = <&slow_rc_osc &slow_osc>;
1114                                 };
1115                         };
1116
1117                         rtc@f80480b0 {
1118                                 compatible = "atmel,at91rm9200-rtc";
1119                                 reg = <0xf80480b0 0x30>;
1120                                 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1121                                 clocks = <&clk32k>;
1122                         };
1123
1124                         spi1: spi@fc000000 {
1125                                 compatible = "atmel,at91rm9200-spi";
1126                                 reg = <0xfc000000 0x100>;
1127                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1128                                 dmas = <&dma0
1129                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1130                                          AT91_XDMAC_DT_PERID(8))>,
1131                                        <&dma0
1132                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1133                                          AT91_XDMAC_DT_PERID(9))>;
1134                                 dma-names = "tx", "rx";
1135                                 clocks = <&spi1_clk>;
1136                                 clock-names = "spi_clk";
1137                                 atmel,fifo-size = <16>;
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 status = "disabled";
1141                         };
1142
1143                         uart3: serial@fc008000 {
1144                                 compatible = "atmel,at91sam9260-usart";
1145                                 reg = <0xfc008000 0x100>;
1146                                 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1147                                 dmas = <&dma0
1148                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1149                                          AT91_XDMAC_DT_PERID(41))>,
1150                                        <&dma0
1151                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1152                                          AT91_XDMAC_DT_PERID(42))>;
1153                                 dma-names = "tx", "rx";
1154                                 clocks = <&uart3_clk>;
1155                                 clock-names = "usart";
1156                                 status = "disabled";
1157                         };
1158
1159                         uart4: serial@fc00c000 {
1160                                 compatible = "atmel,at91sam9260-usart";
1161                                 reg = <0xfc00c000 0x100>;
1162                                 dmas = <&dma0
1163                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1164                                          AT91_XDMAC_DT_PERID(43))>,
1165                                        <&dma0
1166                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1167                                          AT91_XDMAC_DT_PERID(44))>;
1168                                 dma-names = "tx", "rx";
1169                                 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1170                                 clocks = <&uart4_clk>;
1171                                 clock-names = "usart";
1172                                 status = "disabled";
1173                         };
1174
1175                         flx2: flexcom@fc010000 {
1176                                 compatible = "atmel,sama5d2-flexcom";
1177                                 reg = <0xfc010000 0x200>;
1178                                 clocks = <&flx2_clk>;
1179                                 #address-cells = <1>;
1180                                 #size-cells = <1>;
1181                                 ranges = <0x0 0xfc010000 0x800>;
1182                                 status = "disabled";
1183                         };
1184
1185                         flx3: flexcom@fc014000 {
1186                                 compatible = "atmel,sama5d2-flexcom";
1187                                 reg = <0xfc014000 0x200>;
1188                                 clocks = <&flx3_clk>;
1189                                 #address-cells = <1>;
1190                                 #size-cells = <1>;
1191                                 ranges = <0x0 0xfc014000 0x800>;
1192                                 status = "disabled";
1193                         };
1194
1195                         flx4: flexcom@fc018000 {
1196                                 compatible = "atmel,sama5d2-flexcom";
1197                                 reg = <0xfc018000 0x200>;
1198                                 clocks = <&flx4_clk>;
1199                                 #address-cells = <1>;
1200                                 #size-cells = <1>;
1201                                 ranges = <0x0 0xfc018000 0x800>;
1202                                 status = "disabled";
1203                         };
1204
1205                         trng@fc01c000 {
1206                                 compatible = "atmel,at91sam9g45-trng";
1207                                 reg = <0xfc01c000 0x100>;
1208                                 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1209                                 clocks = <&trng_clk>;
1210                         };
1211
1212                         aic: interrupt-controller@fc020000 {
1213                                 #interrupt-cells = <3>;
1214                                 compatible = "atmel,sama5d2-aic";
1215                                 interrupt-controller;
1216                                 reg = <0xfc020000 0x200>;
1217                                 atmel,external-irqs = <49>;
1218                         };
1219
1220                         i2c1: i2c@fc028000 {
1221                                 compatible = "atmel,sama5d2-i2c";
1222                                 reg = <0xfc028000 0x100>;
1223                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1224                                 dmas = <&dma0
1225                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1226                                          AT91_XDMAC_DT_PERID(2))>,
1227                                        <&dma0
1228                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1229                                          AT91_XDMAC_DT_PERID(3))>;
1230                                 dma-names = "tx", "rx";
1231                                 #address-cells = <1>;
1232                                 #size-cells = <0>;
1233                                 clocks = <&twi1_clk>;
1234                                 status = "disabled";
1235                         };
1236
1237                         adc: adc@fc030000 {
1238                                 compatible = "atmel,sama5d2-adc";
1239                                 reg = <0xfc030000 0x100>;
1240                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1241                                 clocks = <&adc_clk>;
1242                                 clock-names = "adc_clk";
1243                                 atmel,min-sample-rate-hz = <200000>;
1244                                 atmel,max-sample-rate-hz = <20000000>;
1245                                 atmel,startup-time-ms = <4>;
1246                                 status = "disabled";
1247                         };
1248
1249                         pioA: pinctrl@fc038000 {
1250                                 compatible = "atmel,sama5d2-pinctrl";
1251                                 reg = <0xfc038000 0x600>;
1252                                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1253                                              <68 IRQ_TYPE_LEVEL_HIGH 7>,
1254                                              <69 IRQ_TYPE_LEVEL_HIGH 7>,
1255                                              <70 IRQ_TYPE_LEVEL_HIGH 7>;
1256                                 interrupt-controller;
1257                                 #interrupt-cells = <2>;
1258                                 gpio-controller;
1259                                 #gpio-cells = <2>;
1260                                 clocks = <&pioA_clk>;
1261                         };
1262
1263                         tdes@fc044000 {
1264                                 compatible = "atmel,at91sam9g46-tdes";
1265                                 reg = <0xfc044000 0x100>;
1266                                 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1267                                 dmas = <&dma0
1268                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1269                                          AT91_XDMAC_DT_PERID(28))>,
1270                                        <&dma0
1271                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1272                                          AT91_XDMAC_DT_PERID(29))>;
1273                                 dma-names = "tx", "rx";
1274                                 clocks = <&tdes_clk>;
1275                                 clock-names = "tdes_clk";
1276                                 status = "okay";
1277                         };
1278
1279                         chipid@fc069000 {
1280                                 compatible = "atmel,sama5d2-chipid";
1281                                 reg = <0xfc069000 0x8>;
1282                         };
1283                 };
1284         };
1285 };