arch/arm/boot/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/power/rk3288-power.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         compatible = "rockchip,rk3288";
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 mshc0 = &emmc;
  30                 mshc1 = &sdmmc;
  31                 mshc2 = &sdio0;
  32                 mshc3 = &sdio1;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &uart2;
  36                 serial3 = &uart3;
  37                 serial4 = &uart4;
  38                 spi0 = &spi0;
  39                 spi1 = &spi1;
  40                 spi2 = &spi2;
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a12-pmu";
  45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         resets = <&cru SRST_CORE0>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clock-latency = <40000>;
  66                         clocks = <&cru ARMCLK>;
  67                 };
  68                 cpu1: cpu@501 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a12";
  71                         reg = <0x501>;
  72                         resets = <&cru SRST_CORE1>;
  73                         operating-points-v2 = <&cpu_opp_table>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                         clock-latency = <40000>;
  76                         clocks = <&cru ARMCLK>;
  77                 };
  78                 cpu2: cpu@502 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a12";
  81                         reg = <0x502>;
  82                         resets = <&cru SRST_CORE2>;
  83                         operating-points-v2 = <&cpu_opp_table>;
  84                         #cooling-cells = <2>; /* min followed by max */
  85                         clock-latency = <40000>;
  86                         clocks = <&cru ARMCLK>;
  87                 };
  88                 cpu3: cpu@503 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a12";
  91                         reg = <0x503>;
  92                         resets = <&cru SRST_CORE3>;
  93                         operating-points-v2 = <&cpu_opp_table>;
  94                         #cooling-cells = <2>; /* min followed by max */
  95                         clock-latency = <40000>;
  96                         clocks = <&cru ARMCLK>;
  97                 };
  98         };
  99
 100         cpu_opp_table: cpu-opp-table {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp-126000000 {
 105                         opp-hz = /bits/ 64 <126000000>;
 106                         opp-microvolt = <900000>;
 107                 };
 108                 opp-216000000 {
 109                         opp-hz = /bits/ 64 <216000000>;
 110                         opp-microvolt = <900000>;
 111                 };
 112                 opp-312000000 {
 113                         opp-hz = /bits/ 64 <312000000>;
 114                         opp-microvolt = <900000>;
 115                 };
 116                 opp-408000000 {
 117                         opp-hz = /bits/ 64 <408000000>;
 118                         opp-microvolt = <900000>;
 119                 };
 120                 opp-600000000 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <900000>;
 123                 };
 124                 opp-696000000 {
 125                         opp-hz = /bits/ 64 <696000000>;
 126                         opp-microvolt = <950000>;
 127                 };
 128                 opp-816000000 {
 129                         opp-hz = /bits/ 64 <816000000>;
 130                         opp-microvolt = <1000000>;
 131                 };
 132                 opp-1008000000 {
 133                         opp-hz = /bits/ 64 <1008000000>;
 134                         opp-microvolt = <1050000>;
 135                 };
 136                 opp-1200000000 {
 137                         opp-hz = /bits/ 64 <1200000000>;
 138                         opp-microvolt = <1100000>;
 139                 };
 140                 opp-1416000000 {
 141                         opp-hz = /bits/ 64 <1416000000>;
 142                         opp-microvolt = <1200000>;
 143                 };
 144                 opp-1512000000 {
 145                         opp-hz = /bits/ 64 <1512000000>;
 146                         opp-microvolt = <1300000>;
 147                 };
 148                 opp-1608000000 {
 149                         opp-hz = /bits/ 64 <1608000000>;
 150                         opp-microvolt = <1350000>;
 151                 };
 152         };
 153
 154         amba {
 155                 compatible = "simple-bus";
 156                 #address-cells = <2>;
 157                 #size-cells = <2>;
 158                 ranges;
 159
 160                 dmac_peri: dma-controller@ff250000 {
 161                         compatible = "arm,pl330", "arm,primecell";
 162                         reg = <0x0 0xff250000 0x0 0x4000>;
 163                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 165                         #dma-cells = <1>;
 166                         arm,pl330-broken-no-flushp;
 167                         clocks = <&cru ACLK_DMAC2>;
 168                         clock-names = "apb_pclk";
 169                 };
 170
 171                 dmac_bus_ns: dma-controller@ff600000 {
 172                         compatible = "arm,pl330", "arm,primecell";
 173                         reg = <0x0 0xff600000 0x0 0x4000>;
 174                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 175                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 176                         #dma-cells = <1>;
 177                         arm,pl330-broken-no-flushp;
 178                         clocks = <&cru ACLK_DMAC1>;
 179                         clock-names = "apb_pclk";
 180                         status = "disabled";
 181                 };
 182
 183                 dmac_bus_s: dma-controller@ffb20000 {
 184                         compatible = "arm,pl330", "arm,primecell";
 185                         reg = <0x0 0xffb20000 0x0 0x4000>;
 186                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 188                         #dma-cells = <1>;
 189                         arm,pl330-broken-no-flushp;
 190                         clocks = <&cru ACLK_DMAC1>;
 191                         clock-names = "apb_pclk";
 192                 };
 193         };
 194
 195         reserved-memory {
 196                 #address-cells = <2>;
 197                 #size-cells = <2>;
 198                 ranges;
 199
 200                 /*
 201                  * The rk3288 cannot use the memory area above 0xfe000000
 202                  * for dma operations for some reason. While there is
 203                  * probably a better solution available somewhere, we
 204                  * haven't found it yet and while devices with 2GB of ram
 205                  * are not affected, this issue prevents 4GB from booting.
 206                  * So to make these devices at least bootable, block
 207                  * this area for the time being until the real solution
 208                  * is found.
 209                  */
 210                 dma-unusable@fe000000 {
 211                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 212                 };
 213         };
 214
 215         xin24m: oscillator {
 216                 compatible = "fixed-clock";
 217                 clock-frequency = <24000000>;
 218                 clock-output-names = "xin24m";
 219                 #clock-cells = <0>;
 220         };
 221
 222         timer {
 223                 compatible = "arm,armv7-timer";
 224                 arm,cpu-registers-not-fw-configured;
 225                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 226                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 227                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 228                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 229                 clock-frequency = <24000000>;
 230         };
 231
 232         timer: timer@ff810000 {
 233                 compatible = "rockchip,rk3288-timer";
 234                 reg = <0x0 0xff810000 0x0 0x20>;
 235                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 237                 clock-names = "timer", "pclk";
 238         };
 239
 240         display-subsystem {
 241                 compatible = "rockchip,display-subsystem";
 242                 ports = <&vopl_out>, <&vopb_out>;
 243         };
 244
 245         sdmmc: dwmmc@ff0c0000 {
 246                 compatible = "rockchip,rk3288-dw-mshc";
 247                 max-frequency = <150000000>;
 248                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 249                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 250                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 251                 fifo-depth = <0x100>;
 252                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 253                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 254                 resets = <&cru SRST_MMC0>;
 255                 reset-names = "reset";
 256                 status = "disabled";
 257         };
 258
 259         sdio0: dwmmc@ff0d0000 {
 260                 compatible = "rockchip,rk3288-dw-mshc";
 261                 max-frequency = <150000000>;
 262                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 263                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 264                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 265                 fifo-depth = <0x100>;
 266                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 267                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 268                 resets = <&cru SRST_SDIO0>;
 269                 reset-names = "reset";
 270                 status = "disabled";
 271         };
 272
 273         sdio1: dwmmc@ff0e0000 {
 274                 compatible = "rockchip,rk3288-dw-mshc";
 275                 max-frequency = <150000000>;
 276                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 277                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 278                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 279                 fifo-depth = <0x100>;
 280                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 281                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 282                 resets = <&cru SRST_SDIO1>;
 283                 reset-names = "reset";
 284                 status = "disabled";
 285         };
 286
 287         emmc: dwmmc@ff0f0000 {
 288                 compatible = "rockchip,rk3288-dw-mshc";
 289                 max-frequency = <150000000>;
 290                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 291                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 292                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 293                 fifo-depth = <0x100>;
 294                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 295                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 296                 resets = <&cru SRST_EMMC>;
 297                 reset-names = "reset";
 298                 status = "disabled";
 299         };
 300
 301         saradc: saradc@ff100000 {
 302                 compatible = "rockchip,saradc";
 303                 reg = <0x0 0xff100000 0x0 0x100>;
 304                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 305                 #io-channel-cells = <1>;
 306                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 307                 clock-names = "saradc", "apb_pclk";
 308                 resets = <&cru SRST_SARADC>;
 309                 reset-names = "saradc-apb";
 310                 status = "disabled";
 311         };
 312
 313         spi0: spi@ff110000 {
 314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 315                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 316                 clock-names = "spiclk", "apb_pclk";
 317                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 318                 dma-names = "tx", "rx";
 319                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 322                 reg = <0x0 0xff110000 0x0 0x1000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi1: spi@ff120000 {
 329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 330                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 331                 clock-names = "spiclk", "apb_pclk";
 332                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 333                 dma-names = "tx", "rx";
 334                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 337                 reg = <0x0 0xff120000 0x0 0x1000>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         spi2: spi@ff130000 {
 344                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 345                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 346                 clock-names = "spiclk", "apb_pclk";
 347                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 348                 dma-names = "tx", "rx";
 349                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 352                 reg = <0x0 0xff130000 0x0 0x1000>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 status = "disabled";
 356         };
 357
 358         i2c1: i2c@ff140000 {
 359                 compatible = "rockchip,rk3288-i2c";
 360                 reg = <0x0 0xff140000 0x0 0x1000>;
 361                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clock-names = "i2c";
 365                 clocks = <&cru PCLK_I2C1>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c1_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c3: i2c@ff150000 {
 372                 compatible = "rockchip,rk3288-i2c";
 373                 reg = <0x0 0xff150000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C3>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c3_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         i2c4: i2c@ff160000 {
 385                 compatible = "rockchip,rk3288-i2c";
 386                 reg = <0x0 0xff160000 0x0 0x1000>;
 387                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 clock-names = "i2c";
 391                 clocks = <&cru PCLK_I2C4>;
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&i2c4_xfer>;
 394                 status = "disabled";
 395         };
 396
 397         i2c5: i2c@ff170000 {
 398                 compatible = "rockchip,rk3288-i2c";
 399                 reg = <0x0 0xff170000 0x0 0x1000>;
 400                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 clock-names = "i2c";
 404                 clocks = <&cru PCLK_I2C5>;
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&i2c5_xfer>;
 407                 status = "disabled";
 408         };
 409
 410         uart0: serial@ff180000 {
 411                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 412                 reg = <0x0 0xff180000 0x0 0x100>;
 413                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&uart0_xfer>;
 420                 status = "disabled";
 421         };
 422
 423         uart1: serial@ff190000 {
 424                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 425                 reg = <0x0 0xff190000 0x0 0x100>;
 426                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 427                 reg-shift = <2>;
 428                 reg-io-width = <4>;
 429                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 430                 clock-names = "baudclk", "apb_pclk";
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&uart1_xfer>;
 433                 status = "disabled";
 434         };
 435
 436         uart2: serial@ff690000 {
 437                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 438                 reg = <0x0 0xff690000 0x0 0x100>;
 439                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 440                 reg-shift = <2>;
 441                 reg-io-width = <4>;
 442                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 443                 clock-names = "baudclk", "apb_pclk";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&uart2_xfer>;
 446                 status = "disabled";
 447         };
 448
 449         uart3: serial@ff1b0000 {
 450                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 451                 reg = <0x0 0xff1b0000 0x0 0x100>;
 452                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 456                 clock-names = "baudclk", "apb_pclk";
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&uart3_xfer>;
 459                 status = "disabled";
 460         };
 461
 462         uart4: serial@ff1c0000 {
 463                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 464                 reg = <0x0 0xff1c0000 0x0 0x100>;
 465                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 466                 reg-shift = <2>;
 467                 reg-io-width = <4>;
 468                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&uart4_xfer>;
 472                 status = "disabled";
 473         };
 474
 475         thermal-zones {
 476                 reserve_thermal: reserve_thermal {
 477                         polling-delay-passive = <1000>; /* milliseconds */
 478                         polling-delay = <5000>; /* milliseconds */
 479
 480                         thermal-sensors = <&tsadc 0>;
 481                 };
 482
 483                 cpu_thermal: cpu_thermal {
 484                         polling-delay-passive = <100>; /* milliseconds */
 485                         polling-delay = <5000>; /* milliseconds */
 486
 487                         thermal-sensors = <&tsadc 1>;
 488
 489                         trips {
 490                                 cpu_alert0: cpu_alert0 {
 491                                         temperature = <70000>; /* millicelsius */
 492                                         hysteresis = <2000>; /* millicelsius */
 493                                         type = "passive";
 494                                 };
 495                                 cpu_alert1: cpu_alert1 {
 496                                         temperature = <75000>; /* millicelsius */
 497                                         hysteresis = <2000>; /* millicelsius */
 498                                         type = "passive";
 499                                 };
 500                                 cpu_crit: cpu_crit {
 501                                         temperature = <90000>; /* millicelsius */
 502                                         hysteresis = <2000>; /* millicelsius */
 503                                         type = "critical";
 504                                 };
 505                         };
 506
 507                         cooling-maps {
 508                                 map0 {
 509                                         trip = <&cpu_alert0>;
 510                                         cooling-device =
 511                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 512                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 513                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 514                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 515                                 };
 516                                 map1 {
 517                                         trip = <&cpu_alert1>;
 518                                         cooling-device =
 519                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 520                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 521                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 522                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 523                                 };
 524                         };
 525                 };
 526
 527                 gpu_thermal: gpu_thermal {
 528                         polling-delay-passive = <100>; /* milliseconds */
 529                         polling-delay = <5000>; /* milliseconds */
 530
 531                         thermal-sensors = <&tsadc 2>;
 532
 533                         trips {
 534                                 gpu_alert0: gpu_alert0 {
 535                                         temperature = <70000>; /* millicelsius */
 536                                         hysteresis = <2000>; /* millicelsius */
 537                                         type = "passive";
 538                                 };
 539                                 gpu_crit: gpu_crit {
 540                                         temperature = <90000>; /* millicelsius */
 541                                         hysteresis = <2000>; /* millicelsius */
 542                                         type = "critical";
 543                                 };
 544                         };
 545
 546                         cooling-maps {
 547                                 map0 {
 548                                         trip = <&gpu_alert0>;
 549                                         cooling-device =
 550                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 551                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 552                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 553                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 554                                 };
 555                         };
 556                 };
 557         };
 558
 559         tsadc: tsadc@ff280000 {
 560                 compatible = "rockchip,rk3288-tsadc";
 561                 reg = <0x0 0xff280000 0x0 0x100>;
 562                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 564                 clock-names = "tsadc", "apb_pclk";
 565                 resets = <&cru SRST_TSADC>;
 566                 reset-names = "tsadc-apb";
 567                 pinctrl-names = "init", "default", "sleep";
 568                 pinctrl-0 = <&otp_gpio>;
 569                 pinctrl-1 = <&otp_out>;
 570                 pinctrl-2 = <&otp_gpio>;
 571                 #thermal-sensor-cells = <1>;
 572                 rockchip,hw-tshut-temp = <95000>;
 573                 status = "disabled";
 574         };
 575
 576         gmac: ethernet@ff290000 {
 577                 compatible = "rockchip,rk3288-gmac";
 578                 reg = <0x0 0xff290000 0x0 0x10000>;
 579                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 580                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 581                 interrupt-names = "macirq", "eth_wake_irq";
 582                 rockchip,grf = <&grf>;
 583                 clocks = <&cru SCLK_MAC>,
 584                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 585                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 586                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 587                 clock-names = "stmmaceth",
 588                         "mac_clk_rx", "mac_clk_tx",
 589                         "clk_mac_ref", "clk_mac_refout",
 590                         "aclk_mac", "pclk_mac";
 591                 resets = <&cru SRST_MAC>;
 592                 reset-names = "stmmaceth";
 593                 status = "disabled";
 594         };
 595
 596         usb_host0_ehci: usb@ff500000 {
 597                 compatible = "generic-ehci";
 598                 reg = <0x0 0xff500000 0x0 0x100>;
 599                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&cru HCLK_USBHOST0>;
 601                 clock-names = "usbhost";
 602                 phys = <&usbphy1>;
 603                 phy-names = "usb";
 604                 status = "disabled";
 605         };
 606
 607         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 608
 609         usb_host1: usb@ff540000 {
 610                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 611                                 "snps,dwc2";
 612                 reg = <0x0 0xff540000 0x0 0x40000>;
 613                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&cru HCLK_USBHOST1>;
 615                 clock-names = "otg";
 616                 dr_mode = "host";
 617                 phys = <&usbphy2>;
 618                 phy-names = "usb2-phy";
 619                 snps,reset-phy-on-wake;
 620                 status = "disabled";
 621         };
 622
 623         usb_otg: usb@ff580000 {
 624                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 625                                 "snps,dwc2";
 626                 reg = <0x0 0xff580000 0x0 0x40000>;
 627                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&cru HCLK_OTG0>;
 629                 clock-names = "otg";
 630                 dr_mode = "otg";
 631                 g-np-tx-fifo-size = <16>;
 632                 g-rx-fifo-size = <275>;
 633                 g-tx-fifo-size = <256 128 128 64 64 32>;
 634                 phys = <&usbphy0>;
 635                 phy-names = "usb2-phy";
 636                 status = "disabled";
 637         };
 638
 639         usb_hsic: usb@ff5c0000 {
 640                 compatible = "generic-ehci";
 641                 reg = <0x0 0xff5c0000 0x0 0x100>;
 642                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 643                 clocks = <&cru HCLK_HSIC>;
 644                 clock-names = "usbhost";
 645                 status = "disabled";
 646         };
 647
 648         i2c0: i2c@ff650000 {
 649                 compatible = "rockchip,rk3288-i2c";
 650                 reg = <0x0 0xff650000 0x0 0x1000>;
 651                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654                 clock-names = "i2c";
 655                 clocks = <&cru PCLK_I2C0>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&i2c0_xfer>;
 658                 status = "disabled";
 659         };
 660
 661         i2c2: i2c@ff660000 {
 662                 compatible = "rockchip,rk3288-i2c";
 663                 reg = <0x0 0xff660000 0x0 0x1000>;
 664                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 clock-names = "i2c";
 668                 clocks = <&cru PCLK_I2C2>;
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&i2c2_xfer>;
 671                 status = "disabled";
 672         };
 673
 674         pwm0: pwm@ff680000 {
 675                 compatible = "rockchip,rk3288-pwm";
 676                 reg = <0x0 0xff680000 0x0 0x10>;
 677                 #pwm-cells = <3>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&pwm0_pin>;
 680                 clocks = <&cru PCLK_PWM>;
 681                 clock-names = "pwm";
 682                 status = "disabled";
 683         };
 684
 685         pwm1: pwm@ff680010 {
 686                 compatible = "rockchip,rk3288-pwm";
 687                 reg = <0x0 0xff680010 0x0 0x10>;
 688                 #pwm-cells = <3>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&pwm1_pin>;
 691                 clocks = <&cru PCLK_PWM>;
 692                 clock-names = "pwm";
 693                 status = "disabled";
 694         };
 695
 696         pwm2: pwm@ff680020 {
 697                 compatible = "rockchip,rk3288-pwm";
 698                 reg = <0x0 0xff680020 0x0 0x10>;
 699                 #pwm-cells = <3>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&pwm2_pin>;
 702                 clocks = <&cru PCLK_PWM>;
 703                 clock-names = "pwm";
 704                 status = "disabled";
 705         };
 706
 707         pwm3: pwm@ff680030 {
 708                 compatible = "rockchip,rk3288-pwm";
 709                 reg = <0x0 0xff680030 0x0 0x10>;
 710                 #pwm-cells = <2>;
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&pwm3_pin>;
 713                 clocks = <&cru PCLK_PWM>;
 714                 clock-names = "pwm";
 715                 status = "disabled";
 716         };
 717
 718         bus_intmem@ff700000 {
 719                 compatible = "mmio-sram";
 720                 reg = <0x0 0xff700000 0x0 0x18000>;
 721                 #address-cells = <1>;
 722                 #size-cells = <1>;
 723                 ranges = <0 0x0 0xff700000 0x18000>;
 724                 smp-sram@0 {
 725                         compatible = "rockchip,rk3066-smp-sram";
 726                         reg = <0x00 0x10>;
 727                 };
 728         };
 729
 730         sram@ff720000 {
 731                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 732                 reg = <0x0 0xff720000 0x0 0x1000>;
 733         };
 734
 735         pmu: power-management@ff730000 {
 736                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 737                 reg = <0x0 0xff730000 0x0 0x100>;
 738
 739                 power: power-controller {
 740                         compatible = "rockchip,rk3288-power-controller";
 741                         #power-domain-cells = <1>;
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744
 745                         assigned-clocks = <&cru SCLK_EDP_24M>;
 746                         assigned-clock-parents = <&xin24m>;
 747
 748                         /*
 749                          * Note: Although SCLK_* are the working clocks
 750                          * of device without including on the NOC, needed for
 751                          * synchronous reset.
 752                          *
 753                          * The clocks on the which NOC:
 754                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 755                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 756                          * ACLK_RGA is on ACLK_RGA_NIU.
 757                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 758                          *
 759                          * Which clock are device clocks:
 760                          *      clocks          devices
 761                          *      *_IEP           IEP:Image Enhancement Processor
 762                          *      *_ISP           ISP:Image Signal Processing
 763                          *      *_VIP           VIP:Video Input Processor
 764                          *      *_VOP*          VOP:Visual Output Processor
 765                          *      *_RGA           RGA
 766                          *      *_EDP*          EDP
 767                          *      *_LVDS_*        LVDS
 768                          *      *_HDMI          HDMI
 769                          *      *_MIPI_*        MIPI
 770                          */
 771                         pd_vio@RK3288_PD_VIO {
 772                                 reg = <RK3288_PD_VIO>;
 773                                 clocks = <&cru ACLK_IEP>,
 774                                          <&cru ACLK_ISP>,
 775                                          <&cru ACLK_RGA>,
 776                                          <&cru ACLK_VIP>,
 777                                          <&cru ACLK_VOP0>,
 778                                          <&cru ACLK_VOP1>,
 779                                          <&cru DCLK_VOP0>,
 780                                          <&cru DCLK_VOP1>,
 781                                          <&cru HCLK_IEP>,
 782                                          <&cru HCLK_ISP>,
 783                                          <&cru HCLK_RGA>,
 784                                          <&cru HCLK_VIP>,
 785                                          <&cru HCLK_VOP0>,
 786                                          <&cru HCLK_VOP1>,
 787                                          <&cru PCLK_EDP_CTRL>,
 788                                          <&cru PCLK_HDMI_CTRL>,
 789                                          <&cru PCLK_LVDS_PHY>,
 790                                          <&cru PCLK_MIPI_CSI>,
 791                                          <&cru PCLK_MIPI_DSI0>,
 792                                          <&cru PCLK_MIPI_DSI1>,
 793                                          <&cru SCLK_EDP_24M>,
 794                                          <&cru SCLK_EDP>,
 795                                          <&cru SCLK_ISP_JPE>,
 796                                          <&cru SCLK_ISP>,
 797                                          <&cru SCLK_RGA>;
 798                                 pm_qos = <&qos_vio0_iep>,
 799                                          <&qos_vio1_vop>,
 800                                          <&qos_vio1_isp_w0>,
 801                                          <&qos_vio1_isp_w1>,
 802                                          <&qos_vio0_vop>,
 803                                          <&qos_vio0_vip>,
 804                                          <&qos_vio2_rga_r>,
 805                                          <&qos_vio2_rga_w>,
 806                                          <&qos_vio1_isp_r>;
 807                         };
 808
 809                         /*
 810                          * Note: The following 3 are HEVC(H.265) clocks,
 811                          * and on the ACLK_HEVC_NIU (NOC).
 812                          */
 813                         pd_hevc@RK3288_PD_HEVC {
 814                                 reg = <RK3288_PD_HEVC>;
 815                                 clocks = <&cru ACLK_HEVC>,
 816                                          <&cru SCLK_HEVC_CABAC>,
 817                                          <&cru SCLK_HEVC_CORE>;
 818                                 pm_qos = <&qos_hevc_r>,
 819                                          <&qos_hevc_w>;
 820                         };
 821
 822                         /*
 823                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 824                          * (video endecoder & decoder) clocks that on the
 825                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 826                          */
 827                         pd_video@RK3288_PD_VIDEO {
 828                                 reg = <RK3288_PD_VIDEO>;
 829                                 clocks = <&cru ACLK_VCODEC>,
 830                                          <&cru HCLK_VCODEC>;
 831                                 pm_qos = <&qos_video>;
 832                         };
 833
 834                         /*
 835                          * Note: ACLK_GPU is the GPU clock,
 836                          * and on the ACLK_GPU_NIU (NOC).
 837                          */
 838                         pd_gpu@RK3288_PD_GPU {
 839                                 reg = <RK3288_PD_GPU>;
 840                                 clocks = <&cru ACLK_GPU>;
 841                                 pm_qos = <&qos_gpu_r>,
 842                                          <&qos_gpu_w>;
 843                         };
 844                 };
 845
 846                 reboot-mode {
 847                         compatible = "syscon-reboot-mode";
 848                         offset = <0x94>;
 849                         mode-normal = <BOOT_NORMAL>;
 850                         mode-recovery = <BOOT_RECOVERY>;
 851                         mode-bootloader = <BOOT_FASTBOOT>;
 852                         mode-loader = <BOOT_BL_DOWNLOAD>;
 853                 };
 854         };
 855
 856         sgrf: syscon@ff740000 {
 857                 compatible = "rockchip,rk3288-sgrf", "syscon";
 858                 reg = <0x0 0xff740000 0x0 0x1000>;
 859         };
 860
 861         cru: clock-controller@ff760000 {
 862                 compatible = "rockchip,rk3288-cru";
 863                 reg = <0x0 0xff760000 0x0 0x1000>;
 864                 rockchip,grf = <&grf>;
 865                 #clock-cells = <1>;
 866                 #reset-cells = <1>;
 867                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 868                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 869                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 870                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 871                                   <&cru PCLK_PERI>;
 872                 assigned-clock-rates = <594000000>, <400000000>,
 873                                        <500000000>, <300000000>,
 874                                        <150000000>, <75000000>,
 875                                        <300000000>, <150000000>,
 876                                        <75000000>;
 877         };
 878
 879         grf: syscon@ff770000 {
 880                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 881                 reg = <0x0 0xff770000 0x0 0x1000>;
 882
 883                 edp_phy: edp-phy {
 884                         compatible = "rockchip,rk3288-dp-phy";
 885                         clocks = <&cru SCLK_EDP_24M>;
 886                         clock-names = "24m";
 887                         #phy-cells = <0>;
 888                         status = "disabled";
 889                 };
 890
 891                 io_domains: io-domains {
 892                         compatible = "rockchip,rk3288-io-voltage-domain";
 893                         status = "disabled";
 894                 };
 895
 896                 usbphy: usbphy {
 897                         compatible = "rockchip,rk3288-usb-phy";
 898                         #address-cells = <1>;
 899                         #size-cells = <0>;
 900                         status = "disabled";
 901
 902                         usbphy0: usb-phy@320 {
 903                                 #phy-cells = <0>;
 904                                 reg = <0x320>;
 905                                 clocks = <&cru SCLK_OTGPHY0>;
 906                                 clock-names = "phyclk";
 907                                 #clock-cells = <0>;
 908                                 resets = <&cru SRST_USBOTG_PHY>;
 909                                 reset-names = "phy-reset";
 910                         };
 911
 912                         usbphy1: usb-phy@334 {
 913                                 #phy-cells = <0>;
 914                                 reg = <0x334>;
 915                                 clocks = <&cru SCLK_OTGPHY1>;
 916                                 clock-names = "phyclk";
 917                                 #clock-cells = <0>;
 918                                 resets = <&cru SRST_USBHOST0_PHY>;
 919                                 reset-names = "phy-reset";
 920                         };
 921
 922                         usbphy2: usb-phy@348 {
 923                                 #phy-cells = <0>;
 924                                 reg = <0x348>;
 925                                 clocks = <&cru SCLK_OTGPHY2>;
 926                                 clock-names = "phyclk";
 927                                 #clock-cells = <0>;
 928                                 resets = <&cru SRST_USBHOST1_PHY>;
 929                                 reset-names = "phy-reset";
 930                         };
 931                 };
 932         };
 933
 934         wdt: watchdog@ff800000 {
 935                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 936                 reg = <0x0 0xff800000 0x0 0x100>;
 937                 clocks = <&cru PCLK_WDT>;
 938                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 939                 status = "disabled";
 940         };
 941
 942         spdif: sound@ff88b0000 {
 943                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 944                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 945                 #sound-dai-cells = <0>;
 946                 clock-names = "hclk", "mclk";
 947                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 948                 dmas = <&dmac_bus_s 3>;
 949                 dma-names = "tx";
 950                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 951                 pinctrl-names = "default";
 952                 pinctrl-0 = <&spdif_tx>;
 953                 rockchip,grf = <&grf>;
 954                 status = "disabled";
 955         };
 956
 957         i2s: i2s@ff890000 {
 958                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 959                 reg = <0x0 0xff890000 0x0 0x10000>;
 960                 #sound-dai-cells = <0>;
 961                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 962                 #address-cells = <1>;
 963                 #size-cells = <0>;
 964                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 965                 dma-names = "tx", "rx";
 966                 clock-names = "i2s_hclk", "i2s_clk";
 967                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 968                 pinctrl-names = "default";
 969                 pinctrl-0 = <&i2s0_bus>;
 970                 rockchip,playback-channels = <8>;
 971                 rockchip,capture-channels = <2>;
 972                 status = "disabled";
 973         };
 974
 975         crypto: cypto-controller@ff8a0000 {
 976                 compatible = "rockchip,rk3288-crypto";
 977                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 978                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 979                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 980                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 981                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 982                 resets = <&cru SRST_CRYPTO>;
 983                 reset-names = "crypto-rst";
 984                 status = "okay";
 985         };
 986
 987         iep_mmu: iommu@ff900800 {
 988                 compatible = "rockchip,iommu";
 989                 reg = <0x0 0xff900800 0x0 0x40>;
 990                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 991                 interrupt-names = "iep_mmu";
 992                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 993                 clock-names = "aclk", "iface";
 994                 #iommu-cells = <0>;
 995                 status = "disabled";
 996         };
 997
 998         isp_mmu: iommu@ff914000 {
 999                 compatible = "rockchip,iommu";
1000                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1001                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1002                 interrupt-names = "isp_mmu";
1003                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1004                 clock-names = "aclk", "iface";
1005                 #iommu-cells = <0>;
1006                 rockchip,disable-mmu-reset;
1007                 status = "disabled";
1008         };
1009
1010         rga: rga@ff920000 {
1011                 compatible = "rockchip,rk3288-rga";
1012                 reg = <0x0 0xff920000 0x0 0x180>;
1013                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1014                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1015                 clock-names = "aclk", "hclk", "sclk";
1016                 power-domains = <&power RK3288_PD_VIO>;
1017                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1018                 reset-names = "core", "axi", "ahb";
1019         };
1020
1021         vopb: vop@ff930000 {
1022                 compatible = "rockchip,rk3288-vop";
1023                 reg = <0x0 0xff930000 0x0 0x19c>;
1024                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1025                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1026                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1027                 power-domains = <&power RK3288_PD_VIO>;
1028                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1029                 reset-names = "axi", "ahb", "dclk";
1030                 iommus = <&vopb_mmu>;
1031                 status = "disabled";
1032
1033                 vopb_out: port {
1034                         #address-cells = <1>;
1035                         #size-cells = <0>;
1036
1037                         vopb_out_hdmi: endpoint@0 {
1038                                 reg = <0>;
1039                                 remote-endpoint = <&hdmi_in_vopb>;
1040                         };
1041
1042                         vopb_out_edp: endpoint@1 {
1043                                 reg = <1>;
1044                                 remote-endpoint = <&edp_in_vopb>;
1045                         };
1046
1047                         vopb_out_mipi: endpoint@2 {
1048                                 reg = <2>;
1049                                 remote-endpoint = <&mipi_in_vopb>;
1050                         };
1051
1052                         vopb_out_lvds: endpoint@3 {
1053                                 reg = <3>;
1054                                 remote-endpoint = <&lvds_in_vopb>;
1055                         };
1056                 };
1057         };
1058
1059         vopb_mmu: iommu@ff930300 {
1060                 compatible = "rockchip,iommu";
1061                 reg = <0x0 0xff930300 0x0 0x100>;
1062                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1063                 interrupt-names = "vopb_mmu";
1064                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1065                 clock-names = "aclk", "iface";
1066                 power-domains = <&power RK3288_PD_VIO>;
1067                 #iommu-cells = <0>;
1068                 status = "disabled";
1069         };
1070
1071         vopl: vop@ff940000 {
1072                 compatible = "rockchip,rk3288-vop";
1073                 reg = <0x0 0xff940000 0x0 0x19c>;
1074                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1075                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1076                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1077                 power-domains = <&power RK3288_PD_VIO>;
1078                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1079                 reset-names = "axi", "ahb", "dclk";
1080                 iommus = <&vopl_mmu>;
1081                 status = "disabled";
1082
1083                 vopl_out: port {
1084                         #address-cells = <1>;
1085                         #size-cells = <0>;
1086
1087                         vopl_out_hdmi: endpoint@0 {
1088                                 reg = <0>;
1089                                 remote-endpoint = <&hdmi_in_vopl>;
1090                         };
1091
1092                         vopl_out_edp: endpoint@1 {
1093                                 reg = <1>;
1094                                 remote-endpoint = <&edp_in_vopl>;
1095                         };
1096
1097                         vopl_out_mipi: endpoint@2 {
1098                                 reg = <2>;
1099                                 remote-endpoint = <&mipi_in_vopl>;
1100                         };
1101
1102                         vopl_out_lvds: endpoint@3 {
1103                                 reg = <3>;
1104                                 remote-endpoint = <&lvds_in_vopl>;
1105                         };
1106                 };
1107         };
1108
1109         vopl_mmu: iommu@ff940300 {
1110                 compatible = "rockchip,iommu";
1111                 reg = <0x0 0xff940300 0x0 0x100>;
1112                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1113                 interrupt-names = "vopl_mmu";
1114                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1115                 clock-names = "aclk", "iface";
1116                 power-domains = <&power RK3288_PD_VIO>;
1117                 #iommu-cells = <0>;
1118                 status = "disabled";
1119         };
1120
1121         mipi_dsi: mipi@ff960000 {
1122                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1123                 reg = <0x0 0xff960000 0x0 0x4000>;
1124                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1125                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1126                 clock-names = "ref", "pclk";
1127                 power-domains = <&power RK3288_PD_VIO>;
1128                 rockchip,grf = <&grf>;
1129                 status = "disabled";
1130
1131                 ports {
1132                         mipi_in: port {
1133                                 #address-cells = <1>;
1134                                 #size-cells = <0>;
1135                                 mipi_in_vopb: endpoint@0 {
1136                                         reg = <0>;
1137                                         remote-endpoint = <&vopb_out_mipi>;
1138                                 };
1139                                 mipi_in_vopl: endpoint@1 {
1140                                         reg = <1>;
1141                                         remote-endpoint = <&vopl_out_mipi>;
1142                                 };
1143                         };
1144                 };
1145         };
1146
1147         lvds: lvds@ff96c000 {
1148                 compatible = "rockchip,rk3288-lvds";
1149                 reg = <0x0 0xff96c000 0x0 0x4000>;
1150                 clocks = <&cru PCLK_LVDS_PHY>;
1151                 clock-names = "pclk_lvds";
1152                 pinctrl-names = "lcdc";
1153                 pinctrl-0 = <&lcdc_ctl>;
1154                 power-domains = <&power RK3288_PD_VIO>;
1155                 rockchip,grf = <&grf>;
1156                 status = "disabled";
1157
1158                 ports {
1159                         #address-cells = <1>;
1160                         #size-cells = <0>;
1161
1162                         lvds_in: port@0 {
1163                                 reg = <0>;
1164
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167
1168                                 lvds_in_vopb: endpoint@0 {
1169                                         reg = <0>;
1170                                         remote-endpoint = <&vopb_out_lvds>;
1171                                 };
1172                                 lvds_in_vopl: endpoint@1 {
1173                                         reg = <1>;
1174                                         remote-endpoint = <&vopl_out_lvds>;
1175                                 };
1176                         };
1177                 };
1178         };
1179
1180         edp: dp@ff970000 {
1181                 compatible = "rockchip,rk3288-dp";
1182                 reg = <0x0 0xff970000 0x0 0x4000>;
1183                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1184                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1185                 clock-names = "dp", "pclk";
1186                 phys = <&edp_phy>;
1187                 phy-names = "dp";
1188                 resets = <&cru SRST_EDP>;
1189                 reset-names = "dp";
1190                 rockchip,grf = <&grf>;
1191                 status = "disabled";
1192
1193                 ports {
1194                         #address-cells = <1>;
1195                         #size-cells = <0>;
1196                         edp_in: port@0 {
1197                                 reg = <0>;
1198                                 #address-cells = <1>;
1199                                 #size-cells = <0>;
1200                                 edp_in_vopb: endpoint@0 {
1201                                         reg = <0>;
1202                                         remote-endpoint = <&vopb_out_edp>;
1203                                 };
1204                                 edp_in_vopl: endpoint@1 {
1205                                         reg = <1>;
1206                                         remote-endpoint = <&vopl_out_edp>;
1207                                 };
1208                         };
1209                 };
1210         };
1211
1212         hdmi: hdmi@ff980000 {
1213                 compatible = "rockchip,rk3288-dw-hdmi";
1214                 reg = <0x0 0xff980000 0x0 0x20000>;
1215                 reg-io-width = <4>;
1216                 #sound-dai-cells = <0>;
1217                 rockchip,grf = <&grf>;
1218                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1219                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1220                 clock-names = "iahb", "isfr", "cec";
1221                 power-domains = <&power RK3288_PD_VIO>;
1222                 status = "disabled";
1223
1224                 ports {
1225                         hdmi_in: port {
1226                                 #address-cells = <1>;
1227                                 #size-cells = <0>;
1228                                 hdmi_in_vopb: endpoint@0 {
1229                                         reg = <0>;
1230                                         remote-endpoint = <&vopb_out_hdmi>;
1231                                 };
1232                                 hdmi_in_vopl: endpoint@1 {
1233                                         reg = <1>;
1234                                         remote-endpoint = <&vopl_out_hdmi>;
1235                                 };
1236                         };
1237                 };
1238         };
1239
1240         vpu: video-codec@ff9a0000 {
1241                 compatible = "rockchip,rk3288-vpu";
1242                 reg = <0x0 0xff9a0000 0x0 0x800>;
1243                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1244                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1245                 interrupt-names = "vepu", "vdpu";
1246                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1247                 clock-names = "aclk", "hclk";
1248                 iommus = <&vpu_mmu>;
1249                 power-domains = <&power RK3288_PD_VIDEO>;
1250         };
1251
1252         vpu_mmu: iommu@ff9a0800 {
1253                 compatible = "rockchip,iommu";
1254                 reg = <0x0 0xff9a0800 0x0 0x100>;
1255                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1256                 interrupt-names = "vpu_mmu";
1257                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1258                 clock-names = "aclk", "iface";
1259                 #iommu-cells = <0>;
1260                 power-domains = <&power RK3288_PD_VIDEO>;
1261         };
1262
1263         hevc_mmu: iommu@ff9c0440 {
1264                 compatible = "rockchip,iommu";
1265                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1266                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1267                 interrupt-names = "hevc_mmu";
1268                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1269                 clock-names = "aclk", "iface";
1270                 #iommu-cells = <0>;
1271                 status = "disabled";
1272         };
1273
1274         gpu: gpu@ffa30000 {
1275                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1276                 reg = <0x0 0xffa30000 0x0 0x10000>;
1277                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1278                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1279                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1280                 interrupt-names = "job", "mmu", "gpu";
1281                 clocks = <&cru ACLK_GPU>;
1282                 operating-points-v2 = <&gpu_opp_table>;
1283                 power-domains = <&power RK3288_PD_GPU>;
1284                 status = "disabled";
1285         };
1286
1287         gpu_opp_table: gpu-opp-table {
1288                 compatible = "operating-points-v2";
1289
1290                 opp-100000000 {
1291                         opp-hz = /bits/ 64 <100000000>;
1292                         opp-microvolt = <950000>;
1293                 };
1294                 opp-200000000 {
1295                         opp-hz = /bits/ 64 <200000000>;
1296                         opp-microvolt = <950000>;
1297                 };
1298                 opp-300000000 {
1299                         opp-hz = /bits/ 64 <300000000>;
1300                         opp-microvolt = <1000000>;
1301                 };
1302                 opp-400000000 {
1303                         opp-hz = /bits/ 64 <400000000>;
1304                         opp-microvolt = <1100000>;
1305                 };
1306                 opp-500000000 {
1307                         opp-hz = /bits/ 64 <500000000>;
1308                         opp-microvolt = <1200000>;
1309                 };
1310                 opp-600000000 {
1311                         opp-hz = /bits/ 64 <600000000>;
1312                         opp-microvolt = <1250000>;
1313                 };
1314         };
1315
1316         qos_gpu_r: qos@ffaa0000 {
1317                 compatible = "syscon";
1318                 reg = <0x0 0xffaa0000 0x0 0x20>;
1319         };
1320
1321         qos_gpu_w: qos@ffaa0080 {
1322                 compatible = "syscon";
1323                 reg = <0x0 0xffaa0080 0x0 0x20>;
1324         };
1325
1326         qos_vio1_vop: qos@ffad0000 {
1327                 compatible = "syscon";
1328                 reg = <0x0 0xffad0000 0x0 0x20>;
1329         };
1330
1331         qos_vio1_isp_w0: qos@ffad0100 {
1332                 compatible = "syscon";
1333                 reg = <0x0 0xffad0100 0x0 0x20>;
1334         };
1335
1336         qos_vio1_isp_w1: qos@ffad0180 {
1337                 compatible = "syscon";
1338                 reg = <0x0 0xffad0180 0x0 0x20>;
1339         };
1340
1341         qos_vio0_vop: qos@ffad0400 {
1342                 compatible = "syscon";
1343                 reg = <0x0 0xffad0400 0x0 0x20>;
1344         };
1345
1346         qos_vio0_vip: qos@ffad0480 {
1347                 compatible = "syscon";
1348                 reg = <0x0 0xffad0480 0x0 0x20>;
1349         };
1350
1351         qos_vio0_iep: qos@ffad0500 {
1352                 compatible = "syscon";
1353                 reg = <0x0 0xffad0500 0x0 0x20>;
1354         };
1355
1356         qos_vio2_rga_r: qos@ffad0800 {
1357                 compatible = "syscon";
1358                 reg = <0x0 0xffad0800 0x0 0x20>;
1359         };
1360
1361         qos_vio2_rga_w: qos@ffad0880 {
1362                 compatible = "syscon";
1363                 reg = <0x0 0xffad0880 0x0 0x20>;
1364         };
1365
1366         qos_vio1_isp_r: qos@ffad0900 {
1367                 compatible = "syscon";
1368                 reg = <0x0 0xffad0900 0x0 0x20>;
1369         };
1370
1371         qos_video: qos@ffae0000 {
1372                 compatible = "syscon";
1373                 reg = <0x0 0xffae0000 0x0 0x20>;
1374         };
1375
1376         qos_hevc_r: qos@ffaf0000 {
1377                 compatible = "syscon";
1378                 reg = <0x0 0xffaf0000 0x0 0x20>;
1379         };
1380
1381         qos_hevc_w: qos@ffaf0080 {
1382                 compatible = "syscon";
1383                 reg = <0x0 0xffaf0080 0x0 0x20>;
1384         };
1385
1386         gic: interrupt-controller@ffc01000 {
1387                 compatible = "arm,gic-400";
1388                 interrupt-controller;
1389                 #interrupt-cells = <3>;
1390                 #address-cells = <0>;
1391
1392                 reg = <0x0 0xffc01000 0x0 0x1000>,
1393                       <0x0 0xffc02000 0x0 0x2000>,
1394                       <0x0 0xffc04000 0x0 0x2000>,
1395                       <0x0 0xffc06000 0x0 0x2000>;
1396                 interrupts = <GIC_PPI 9 0xf04>;
1397         };
1398
1399         efuse: efuse@ffb40000 {
1400                 compatible = "rockchip,rk3288-efuse";
1401                 reg = <0x0 0xffb40000 0x0 0x20>;
1402                 #address-cells = <1>;
1403                 #size-cells = <1>;
1404                 clocks = <&cru PCLK_EFUSE256>;
1405                 clock-names = "pclk_efuse";
1406
1407                 cpu_leakage: cpu_leakage@17 {
1408                         reg = <0x17 0x1>;
1409                 };
1410         };
1411
1412         pinctrl: pinctrl {
1413                 compatible = "rockchip,rk3288-pinctrl";
1414                 rockchip,grf = <&grf>;
1415                 rockchip,pmu = <&pmu>;
1416                 #address-cells = <2>;
1417                 #size-cells = <2>;
1418                 ranges;
1419
1420                 gpio0: gpio0@ff750000 {
1421                         compatible = "rockchip,gpio-bank";
1422                         reg = <0x0 0xff750000 0x0 0x100>;
1423                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1424                         clocks = <&cru PCLK_GPIO0>;
1425
1426                         gpio-controller;
1427                         #gpio-cells = <2>;
1428
1429                         interrupt-controller;
1430                         #interrupt-cells = <2>;
1431                 };
1432
1433                 gpio1: gpio1@ff780000 {
1434                         compatible = "rockchip,gpio-bank";
1435                         reg = <0x0 0xff780000 0x0 0x100>;
1436                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1437                         clocks = <&cru PCLK_GPIO1>;
1438
1439                         gpio-controller;
1440                         #gpio-cells = <2>;
1441
1442                         interrupt-controller;
1443                         #interrupt-cells = <2>;
1444                 };
1445
1446                 gpio2: gpio2@ff790000 {
1447                         compatible = "rockchip,gpio-bank";
1448                         reg = <0x0 0xff790000 0x0 0x100>;
1449                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1450                         clocks = <&cru PCLK_GPIO2>;
1451
1452                         gpio-controller;
1453                         #gpio-cells = <2>;
1454
1455                         interrupt-controller;
1456                         #interrupt-cells = <2>;
1457                 };
1458
1459                 gpio3: gpio3@ff7a0000 {
1460                         compatible = "rockchip,gpio-bank";
1461                         reg = <0x0 0xff7a0000 0x0 0x100>;
1462                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1463                         clocks = <&cru PCLK_GPIO3>;
1464
1465                         gpio-controller;
1466                         #gpio-cells = <2>;
1467
1468                         interrupt-controller;
1469                         #interrupt-cells = <2>;
1470                 };
1471
1472                 gpio4: gpio4@ff7b0000 {
1473                         compatible = "rockchip,gpio-bank";
1474                         reg = <0x0 0xff7b0000 0x0 0x100>;
1475                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1476                         clocks = <&cru PCLK_GPIO4>;
1477
1478                         gpio-controller;
1479                         #gpio-cells = <2>;
1480
1481                         interrupt-controller;
1482                         #interrupt-cells = <2>;
1483                 };
1484
1485                 gpio5: gpio5@ff7c0000 {
1486                         compatible = "rockchip,gpio-bank";
1487                         reg = <0x0 0xff7c0000 0x0 0x100>;
1488                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1489                         clocks = <&cru PCLK_GPIO5>;
1490
1491                         gpio-controller;
1492                         #gpio-cells = <2>;
1493
1494                         interrupt-controller;
1495                         #interrupt-cells = <2>;
1496                 };
1497
1498                 gpio6: gpio6@ff7d0000 {
1499                         compatible = "rockchip,gpio-bank";
1500                         reg = <0x0 0xff7d0000 0x0 0x100>;
1501                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1502                         clocks = <&cru PCLK_GPIO6>;
1503
1504                         gpio-controller;
1505                         #gpio-cells = <2>;
1506
1507                         interrupt-controller;
1508                         #interrupt-cells = <2>;
1509                 };
1510
1511                 gpio7: gpio7@ff7e0000 {
1512                         compatible = "rockchip,gpio-bank";
1513                         reg = <0x0 0xff7e0000 0x0 0x100>;
1514                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1515                         clocks = <&cru PCLK_GPIO7>;
1516
1517                         gpio-controller;
1518                         #gpio-cells = <2>;
1519
1520                         interrupt-controller;
1521                         #interrupt-cells = <2>;
1522                 };
1523
1524                 gpio8: gpio8@ff7f0000 {
1525                         compatible = "rockchip,gpio-bank";
1526                         reg = <0x0 0xff7f0000 0x0 0x100>;
1527                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1528                         clocks = <&cru PCLK_GPIO8>;
1529
1530                         gpio-controller;
1531                         #gpio-cells = <2>;
1532
1533                         interrupt-controller;
1534                         #interrupt-cells = <2>;
1535                 };
1536
1537                 hdmi {
1538                         hdmi_cec_c0: hdmi-cec-c0 {
1539                                 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1540                         };
1541
1542                         hdmi_cec_c7: hdmi-cec-c7 {
1543                                 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
1544                         };
1545
1546                         hdmi_ddc: hdmi-ddc {
1547                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1548                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1549                         };
1550                 };
1551
1552                 pcfg_pull_up: pcfg-pull-up {
1553                         bias-pull-up;
1554                 };
1555
1556                 pcfg_pull_down: pcfg-pull-down {
1557                         bias-pull-down;
1558                 };
1559
1560                 pcfg_pull_none: pcfg-pull-none {
1561                         bias-disable;
1562                 };
1563
1564                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1565                         bias-disable;
1566                         drive-strength = <12>;
1567                 };
1568
1569                 sleep {
1570                         global_pwroff: global-pwroff {
1571                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1572                         };
1573
1574                         ddrio_pwroff: ddrio-pwroff {
1575                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1576                         };
1577
1578                         ddr0_retention: ddr0-retention {
1579                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1580                         };
1581
1582                         ddr1_retention: ddr1-retention {
1583                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1584                         };
1585                 };
1586
1587                 edp {
1588                         edp_hpd: edp-hpd {
1589                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1590                         };
1591                 };
1592
1593                 i2c0 {
1594                         i2c0_xfer: i2c0-xfer {
1595                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1596                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1597                         };
1598                 };
1599
1600                 i2c1 {
1601                         i2c1_xfer: i2c1-xfer {
1602                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1603                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605                 };
1606
1607                 i2c2 {
1608                         i2c2_xfer: i2c2-xfer {
1609                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1610                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 i2c3 {
1615                         i2c3_xfer: i2c3-xfer {
1616                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1617                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 i2c4 {
1622                         i2c4_xfer: i2c4-xfer {
1623                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1624                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1625                         };
1626                 };
1627
1628                 i2c5 {
1629                         i2c5_xfer: i2c5-xfer {
1630                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1631                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1632                         };
1633                 };
1634
1635                 i2s0 {
1636                         i2s0_bus: i2s0-bus {
1637                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1638                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1639                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1640                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1641                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1642                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1643                         };
1644                 };
1645
1646                 lcdc {
1647                         lcdc_ctl: lcdc-ctl {
1648                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1649                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1650                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1651                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1652                         };
1653                 };
1654
1655                 sdmmc {
1656                         sdmmc_clk: sdmmc-clk {
1657                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1658                         };
1659
1660                         sdmmc_cmd: sdmmc-cmd {
1661                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1662                         };
1663
1664                         sdmmc_cd: sdmmc-cd {
1665                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1666                         };
1667
1668                         sdmmc_bus1: sdmmc-bus1 {
1669                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1670                         };
1671
1672                         sdmmc_bus4: sdmmc-bus4 {
1673                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1674                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1675                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1676                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1677                         };
1678                 };
1679
1680                 sdio0 {
1681                         sdio0_bus1: sdio0-bus1 {
1682                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1683                         };
1684
1685                         sdio0_bus4: sdio0-bus4 {
1686                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1687                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1688                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1689                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1690                         };
1691
1692                         sdio0_cmd: sdio0-cmd {
1693                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1694                         };
1695
1696                         sdio0_clk: sdio0-clk {
1697                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1698                         };
1699
1700                         sdio0_cd: sdio0-cd {
1701                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1702                         };
1703
1704                         sdio0_wp: sdio0-wp {
1705                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1706                         };
1707
1708                         sdio0_pwr: sdio0-pwr {
1709                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1710                         };
1711
1712                         sdio0_bkpwr: sdio0-bkpwr {
1713                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1714                         };
1715
1716                         sdio0_int: sdio0-int {
1717                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1718                         };
1719                 };
1720
1721                 sdio1 {
1722                         sdio1_bus1: sdio1-bus1 {
1723                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1724                         };
1725
1726                         sdio1_bus4: sdio1-bus4 {
1727                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1728                                                 <3 25 4 &pcfg_pull_up>,
1729                                                 <3 26 4 &pcfg_pull_up>,
1730                                                 <3 27 4 &pcfg_pull_up>;
1731                         };
1732
1733                         sdio1_cd: sdio1-cd {
1734                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1735                         };
1736
1737                         sdio1_wp: sdio1-wp {
1738                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1739                         };
1740
1741                         sdio1_bkpwr: sdio1-bkpwr {
1742                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1743                         };
1744
1745                         sdio1_int: sdio1-int {
1746                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1747                         };
1748
1749                         sdio1_cmd: sdio1-cmd {
1750                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1751                         };
1752
1753                         sdio1_clk: sdio1-clk {
1754                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1755                         };
1756
1757                         sdio1_pwr: sdio1-pwr {
1758                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1759                         };
1760                 };
1761
1762                 emmc {
1763                         emmc_clk: emmc-clk {
1764                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1765                         };
1766
1767                         emmc_cmd: emmc-cmd {
1768                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1769                         };
1770
1771                         emmc_pwr: emmc-pwr {
1772                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1773                         };
1774
1775                         emmc_bus1: emmc-bus1 {
1776                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1777                         };
1778
1779                         emmc_bus4: emmc-bus4 {
1780                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1781                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1782                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1783                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1784                         };
1785
1786                         emmc_bus8: emmc-bus8 {
1787                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1788                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1789                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1790                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1791                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1792                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1793                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1794                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1795                         };
1796                 };
1797
1798                 spi0 {
1799                         spi0_clk: spi0-clk {
1800                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1801                         };
1802                         spi0_cs0: spi0-cs0 {
1803                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1804                         };
1805                         spi0_tx: spi0-tx {
1806                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1807                         };
1808                         spi0_rx: spi0-rx {
1809                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1810                         };
1811                         spi0_cs1: spi0-cs1 {
1812                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814                 };
1815                 spi1 {
1816                         spi1_clk: spi1-clk {
1817                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1818                         };
1819                         spi1_cs0: spi1-cs0 {
1820                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1821                         };
1822                         spi1_rx: spi1-rx {
1823                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1824                         };
1825                         spi1_tx: spi1-tx {
1826                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1827                         };
1828                 };
1829
1830                 spi2 {
1831                         spi2_cs1: spi2-cs1 {
1832                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1833                         };
1834                         spi2_clk: spi2-clk {
1835                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1836                         };
1837                         spi2_cs0: spi2-cs0 {
1838                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1839                         };
1840                         spi2_rx: spi2-rx {
1841                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1842                         };
1843                         spi2_tx: spi2-tx {
1844                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1845                         };
1846                 };
1847
1848                 uart0 {
1849                         uart0_xfer: uart0-xfer {
1850                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1851                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1852                         };
1853
1854                         uart0_cts: uart0-cts {
1855                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1856                         };
1857
1858                         uart0_rts: uart0-rts {
1859                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1860                         };
1861                 };
1862
1863                 uart1 {
1864                         uart1_xfer: uart1-xfer {
1865                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1866                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1867                         };
1868
1869                         uart1_cts: uart1-cts {
1870                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1871                         };
1872
1873                         uart1_rts: uart1-rts {
1874                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1875                         };
1876                 };
1877
1878                 uart2 {
1879                         uart2_xfer: uart2-xfer {
1880                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1881                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1882                         };
1883                         /* no rts / cts for uart2 */
1884                 };
1885
1886                 uart3 {
1887                         uart3_xfer: uart3-xfer {
1888                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1889                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1890                         };
1891
1892                         uart3_cts: uart3-cts {
1893                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1894                         };
1895
1896                         uart3_rts: uart3-rts {
1897                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1898                         };
1899                 };
1900
1901                 uart4 {
1902                         uart4_xfer: uart4-xfer {
1903                                 rockchip,pins = <5 15 3 &pcfg_pull_up>,
1904                                                 <5 14 3 &pcfg_pull_none>;
1905                         };
1906
1907                         uart4_cts: uart4-cts {
1908                                 rockchip,pins = <5 12 3 &pcfg_pull_up>;
1909                         };
1910
1911                         uart4_rts: uart4-rts {
1912                                 rockchip,pins = <5 13 3 &pcfg_pull_none>;
1913                         };
1914                 };
1915
1916                 tsadc {
1917                         otp_gpio: otp-gpio {
1918                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1919                         };
1920
1921                         otp_out: otp-out {
1922                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1923                         };
1924                 };
1925
1926                 pwm0 {
1927                         pwm0_pin: pwm0-pin {
1928                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 pwm1 {
1933                         pwm1_pin: pwm1-pin {
1934                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 pwm2 {
1939                         pwm2_pin: pwm2-pin {
1940                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1941                         };
1942                 };
1943
1944                 pwm3 {
1945                         pwm3_pin: pwm3-pin {
1946                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1947                         };
1948                 };
1949
1950                 gmac {
1951                         rgmii_pins: rgmii-pins {
1952                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1953                                                 <3 31 3 &pcfg_pull_none>,
1954                                                 <3 26 3 &pcfg_pull_none>,
1955                                                 <3 27 3 &pcfg_pull_none>,
1956                                                 <3 28 3 &pcfg_pull_none_12ma>,
1957                                                 <3 29 3 &pcfg_pull_none_12ma>,
1958                                                 <3 24 3 &pcfg_pull_none_12ma>,
1959                                                 <3 25 3 &pcfg_pull_none_12ma>,
1960                                                 <4 0 3 &pcfg_pull_none>,
1961                                                 <4 5 3 &pcfg_pull_none>,
1962                                                 <4 6 3 &pcfg_pull_none>,
1963                                                 <4 9 3 &pcfg_pull_none_12ma>,
1964                                                 <4 4 3 &pcfg_pull_none_12ma>,
1965                                                 <4 1 3 &pcfg_pull_none>,
1966                                                 <4 3 3 &pcfg_pull_none>;
1967                         };
1968
1969                         rmii_pins: rmii-pins {
1970                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1971                                                 <3 31 3 &pcfg_pull_none>,
1972                                                 <3 28 3 &pcfg_pull_none>,
1973                                                 <3 29 3 &pcfg_pull_none>,
1974                                                 <4 0 3 &pcfg_pull_none>,
1975                                                 <4 5 3 &pcfg_pull_none>,
1976                                                 <4 4 3 &pcfg_pull_none>,
1977                                                 <4 1 3 &pcfg_pull_none>,
1978                                                 <4 2 3 &pcfg_pull_none>,
1979                                                 <4 3 3 &pcfg_pull_none>;
1980                         };
1981                 };
1982
1983                 spdif {
1984                         spdif_tx: spdif-tx {
1985                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1986                         };
1987                 };
1988         };
1989 };