arch/arm/boot/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/power/rk3288-power.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         compatible = "rockchip,rk3288";
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 mshc0 = &emmc;
  30                 mshc1 = &sdmmc;
  31                 mshc2 = &sdio0;
  32                 mshc3 = &sdio1;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &uart2;
  36                 serial3 = &uart3;
  37                 serial4 = &uart4;
  38                 spi0 = &spi0;
  39                 spi1 = &spi1;
  40                 spi2 = &spi2;
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a12-pmu";
  45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         resets = <&cru SRST_CORE0>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clock-latency = <40000>;
  66                         clocks = <&cru ARMCLK>;
  67                 };
  68                 cpu1: cpu@501 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a12";
  71                         reg = <0x501>;
  72                         resets = <&cru SRST_CORE1>;
  73                         operating-points-v2 = <&cpu_opp_table>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                         clock-latency = <40000>;
  76                         clocks = <&cru ARMCLK>;
  77                 };
  78                 cpu2: cpu@502 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a12";
  81                         reg = <0x502>;
  82                         resets = <&cru SRST_CORE2>;
  83                         operating-points-v2 = <&cpu_opp_table>;
  84                         #cooling-cells = <2>; /* min followed by max */
  85                         clock-latency = <40000>;
  86                         clocks = <&cru ARMCLK>;
  87                 };
  88                 cpu3: cpu@503 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a12";
  91                         reg = <0x503>;
  92                         resets = <&cru SRST_CORE3>;
  93                         operating-points-v2 = <&cpu_opp_table>;
  94                         #cooling-cells = <2>; /* min followed by max */
  95                         clock-latency = <40000>;
  96                         clocks = <&cru ARMCLK>;
  97                 };
  98         };
  99
 100         cpu_opp_table: cpu-opp-table {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp-126000000 {
 105                         opp-hz = /bits/ 64 <126000000>;
 106                         opp-microvolt = <900000>;
 107                 };
 108                 opp-216000000 {
 109                         opp-hz = /bits/ 64 <216000000>;
 110                         opp-microvolt = <900000>;
 111                 };
 112                 opp-312000000 {
 113                         opp-hz = /bits/ 64 <312000000>;
 114                         opp-microvolt = <900000>;
 115                 };
 116                 opp-408000000 {
 117                         opp-hz = /bits/ 64 <408000000>;
 118                         opp-microvolt = <900000>;
 119                 };
 120                 opp-600000000 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <900000>;
 123                 };
 124                 opp-696000000 {
 125                         opp-hz = /bits/ 64 <696000000>;
 126                         opp-microvolt = <950000>;
 127                 };
 128                 opp-816000000 {
 129                         opp-hz = /bits/ 64 <816000000>;
 130                         opp-microvolt = <1000000>;
 131                 };
 132                 opp-1008000000 {
 133                         opp-hz = /bits/ 64 <1008000000>;
 134                         opp-microvolt = <1050000>;
 135                 };
 136                 opp-1200000000 {
 137                         opp-hz = /bits/ 64 <1200000000>;
 138                         opp-microvolt = <1100000>;
 139                 };
 140                 opp-1416000000 {
 141                         opp-hz = /bits/ 64 <1416000000>;
 142                         opp-microvolt = <1200000>;
 143                 };
 144                 opp-1512000000 {
 145                         opp-hz = /bits/ 64 <1512000000>;
 146                         opp-microvolt = <1300000>;
 147                 };
 148                 opp-1608000000 {
 149                         opp-hz = /bits/ 64 <1608000000>;
 150                         opp-microvolt = <1350000>;
 151                 };
 152         };
 153
 154         amba {
 155                 compatible = "simple-bus";
 156                 #address-cells = <2>;
 157                 #size-cells = <2>;
 158                 ranges;
 159
 160                 dmac_peri: dma-controller@ff250000 {
 161                         compatible = "arm,pl330", "arm,primecell";
 162                         reg = <0x0 0xff250000 0x0 0x4000>;
 163                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 165                         #dma-cells = <1>;
 166                         arm,pl330-broken-no-flushp;
 167                         clocks = <&cru ACLK_DMAC2>;
 168                         clock-names = "apb_pclk";
 169                 };
 170
 171                 dmac_bus_ns: dma-controller@ff600000 {
 172                         compatible = "arm,pl330", "arm,primecell";
 173                         reg = <0x0 0xff600000 0x0 0x4000>;
 174                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 175                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 176                         #dma-cells = <1>;
 177                         arm,pl330-broken-no-flushp;
 178                         clocks = <&cru ACLK_DMAC1>;
 179                         clock-names = "apb_pclk";
 180                         status = "disabled";
 181                 };
 182
 183                 dmac_bus_s: dma-controller@ffb20000 {
 184                         compatible = "arm,pl330", "arm,primecell";
 185                         reg = <0x0 0xffb20000 0x0 0x4000>;
 186                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 188                         #dma-cells = <1>;
 189                         arm,pl330-broken-no-flushp;
 190                         clocks = <&cru ACLK_DMAC1>;
 191                         clock-names = "apb_pclk";
 192                 };
 193         };
 194
 195         reserved-memory {
 196                 #address-cells = <2>;
 197                 #size-cells = <2>;
 198                 ranges;
 199
 200                 /*
 201                  * The rk3288 cannot use the memory area above 0xfe000000
 202                  * for dma operations for some reason. While there is
 203                  * probably a better solution available somewhere, we
 204                  * haven't found it yet and while devices with 2GB of ram
 205                  * are not affected, this issue prevents 4GB from booting.
 206                  * So to make these devices at least bootable, block
 207                  * this area for the time being until the real solution
 208                  * is found.
 209                  */
 210                 dma-unusable@fe000000 {
 211                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 212                 };
 213         };
 214
 215         xin24m: oscillator {
 216                 compatible = "fixed-clock";
 217                 clock-frequency = <24000000>;
 218                 clock-output-names = "xin24m";
 219                 #clock-cells = <0>;
 220         };
 221
 222         timer {
 223                 compatible = "arm,armv7-timer";
 224                 arm,cpu-registers-not-fw-configured;
 225                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 226                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 227                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 228                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 229                 clock-frequency = <24000000>;
 230         };
 231
 232         timer: timer@ff810000 {
 233                 compatible = "rockchip,rk3288-timer";
 234                 reg = <0x0 0xff810000 0x0 0x20>;
 235                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 237                 clock-names = "timer", "pclk";
 238         };
 239
 240         display-subsystem {
 241                 compatible = "rockchip,display-subsystem";
 242                 ports = <&vopl_out>, <&vopb_out>;
 243         };
 244
 245         sdmmc: dwmmc@ff0c0000 {
 246                 compatible = "rockchip,rk3288-dw-mshc";
 247                 max-frequency = <150000000>;
 248                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 249                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 250                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 251                 fifo-depth = <0x100>;
 252                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 253                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 254                 resets = <&cru SRST_MMC0>;
 255                 reset-names = "reset";
 256                 status = "disabled";
 257         };
 258
 259         sdio0: dwmmc@ff0d0000 {
 260                 compatible = "rockchip,rk3288-dw-mshc";
 261                 max-frequency = <150000000>;
 262                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 263                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 264                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 265                 fifo-depth = <0x100>;
 266                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 267                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 268                 resets = <&cru SRST_SDIO0>;
 269                 reset-names = "reset";
 270                 status = "disabled";
 271         };
 272
 273         sdio1: dwmmc@ff0e0000 {
 274                 compatible = "rockchip,rk3288-dw-mshc";
 275                 max-frequency = <150000000>;
 276                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 277                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 278                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 279                 fifo-depth = <0x100>;
 280                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 281                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 282                 resets = <&cru SRST_SDIO1>;
 283                 reset-names = "reset";
 284                 status = "disabled";
 285         };
 286
 287         emmc: dwmmc@ff0f0000 {
 288                 compatible = "rockchip,rk3288-dw-mshc";
 289                 max-frequency = <150000000>;
 290                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 291                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 292                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 293                 fifo-depth = <0x100>;
 294                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 295                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 296                 resets = <&cru SRST_EMMC>;
 297                 reset-names = "reset";
 298                 status = "disabled";
 299         };
 300
 301         saradc: saradc@ff100000 {
 302                 compatible = "rockchip,saradc";
 303                 reg = <0x0 0xff100000 0x0 0x100>;
 304                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 305                 #io-channel-cells = <1>;
 306                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 307                 clock-names = "saradc", "apb_pclk";
 308                 resets = <&cru SRST_SARADC>;
 309                 reset-names = "saradc-apb";
 310                 status = "disabled";
 311         };
 312
 313         spi0: spi@ff110000 {
 314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 315                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 316                 clock-names = "spiclk", "apb_pclk";
 317                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 318                 dma-names = "tx", "rx";
 319                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 322                 reg = <0x0 0xff110000 0x0 0x1000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi1: spi@ff120000 {
 329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 330                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 331                 clock-names = "spiclk", "apb_pclk";
 332                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 333                 dma-names = "tx", "rx";
 334                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 337                 reg = <0x0 0xff120000 0x0 0x1000>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         spi2: spi@ff130000 {
 344                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 345                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 346                 clock-names = "spiclk", "apb_pclk";
 347                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 348                 dma-names = "tx", "rx";
 349                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 352                 reg = <0x0 0xff130000 0x0 0x1000>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 status = "disabled";
 356         };
 357
 358         i2c1: i2c@ff140000 {
 359                 compatible = "rockchip,rk3288-i2c";
 360                 reg = <0x0 0xff140000 0x0 0x1000>;
 361                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clock-names = "i2c";
 365                 clocks = <&cru PCLK_I2C1>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c1_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c3: i2c@ff150000 {
 372                 compatible = "rockchip,rk3288-i2c";
 373                 reg = <0x0 0xff150000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C3>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c3_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         i2c4: i2c@ff160000 {
 385                 compatible = "rockchip,rk3288-i2c";
 386                 reg = <0x0 0xff160000 0x0 0x1000>;
 387                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 clock-names = "i2c";
 391                 clocks = <&cru PCLK_I2C4>;
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&i2c4_xfer>;
 394                 status = "disabled";
 395         };
 396
 397         i2c5: i2c@ff170000 {
 398                 compatible = "rockchip,rk3288-i2c";
 399                 reg = <0x0 0xff170000 0x0 0x1000>;
 400                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 clock-names = "i2c";
 404                 clocks = <&cru PCLK_I2C5>;
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&i2c5_xfer>;
 407                 status = "disabled";
 408         };
 409
 410         uart0: serial@ff180000 {
 411                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 412                 reg = <0x0 0xff180000 0x0 0x100>;
 413                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&uart0_xfer>;
 420                 status = "disabled";
 421         };
 422
 423         uart1: serial@ff190000 {
 424                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 425                 reg = <0x0 0xff190000 0x0 0x100>;
 426                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 427                 reg-shift = <2>;
 428                 reg-io-width = <4>;
 429                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 430                 clock-names = "baudclk", "apb_pclk";
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&uart1_xfer>;
 433                 status = "disabled";
 434         };
 435
 436         uart2: serial@ff690000 {
 437                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 438                 reg = <0x0 0xff690000 0x0 0x100>;
 439                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 440                 reg-shift = <2>;
 441                 reg-io-width = <4>;
 442                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 443                 clock-names = "baudclk", "apb_pclk";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&uart2_xfer>;
 446                 status = "disabled";
 447         };
 448
 449         uart3: serial@ff1b0000 {
 450                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 451                 reg = <0x0 0xff1b0000 0x0 0x100>;
 452                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 456                 clock-names = "baudclk", "apb_pclk";
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&uart3_xfer>;
 459                 status = "disabled";
 460         };
 461
 462         uart4: serial@ff1c0000 {
 463                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 464                 reg = <0x0 0xff1c0000 0x0 0x100>;
 465                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 466                 reg-shift = <2>;
 467                 reg-io-width = <4>;
 468                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&uart4_xfer>;
 472                 status = "disabled";
 473         };
 474
 475         thermal-zones {
 476                 reserve_thermal: reserve_thermal {
 477                         polling-delay-passive = <1000>; /* milliseconds */
 478                         polling-delay = <5000>; /* milliseconds */
 479
 480                         thermal-sensors = <&tsadc 0>;
 481                 };
 482
 483                 cpu_thermal: cpu_thermal {
 484                         polling-delay-passive = <100>; /* milliseconds */
 485                         polling-delay = <5000>; /* milliseconds */
 486
 487                         thermal-sensors = <&tsadc 1>;
 488
 489                         trips {
 490                                 cpu_alert0: cpu_alert0 {
 491                                         temperature = <70000>; /* millicelsius */
 492                                         hysteresis = <2000>; /* millicelsius */
 493                                         type = "passive";
 494                                 };
 495                                 cpu_alert1: cpu_alert1 {
 496                                         temperature = <75000>; /* millicelsius */
 497                                         hysteresis = <2000>; /* millicelsius */
 498                                         type = "passive";
 499                                 };
 500                                 cpu_crit: cpu_crit {
 501                                         temperature = <90000>; /* millicelsius */
 502                                         hysteresis = <2000>; /* millicelsius */
 503                                         type = "critical";
 504                                 };
 505                         };
 506
 507                         cooling-maps {
 508                                 map0 {
 509                                         trip = <&cpu_alert0>;
 510                                         cooling-device =
 511                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 512                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 513                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 514                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 515                                 };
 516                                 map1 {
 517                                         trip = <&cpu_alert1>;
 518                                         cooling-device =
 519                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 520                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 521                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 522                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 523                                 };
 524                         };
 525                 };
 526
 527                 gpu_thermal: gpu_thermal {
 528                         polling-delay-passive = <100>; /* milliseconds */
 529                         polling-delay = <5000>; /* milliseconds */
 530
 531                         thermal-sensors = <&tsadc 2>;
 532
 533                         trips {
 534                                 gpu_alert0: gpu_alert0 {
 535                                         temperature = <70000>; /* millicelsius */
 536                                         hysteresis = <2000>; /* millicelsius */
 537                                         type = "passive";
 538                                 };
 539                                 gpu_crit: gpu_crit {
 540                                         temperature = <90000>; /* millicelsius */
 541                                         hysteresis = <2000>; /* millicelsius */
 542                                         type = "critical";
 543                                 };
 544                         };
 545
 546                         cooling-maps {
 547                                 map0 {
 548                                         trip = <&gpu_alert0>;
 549                                         cooling-device =
 550                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 551                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 552                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 553                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 554                                 };
 555                         };
 556                 };
 557         };
 558
 559         tsadc: tsadc@ff280000 {
 560                 compatible = "rockchip,rk3288-tsadc";
 561                 reg = <0x0 0xff280000 0x0 0x100>;
 562                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 564                 clock-names = "tsadc", "apb_pclk";
 565                 resets = <&cru SRST_TSADC>;
 566                 reset-names = "tsadc-apb";
 567                 pinctrl-names = "init", "default", "sleep";
 568                 pinctrl-0 = <&otp_gpio>;
 569                 pinctrl-1 = <&otp_out>;
 570                 pinctrl-2 = <&otp_gpio>;
 571                 #thermal-sensor-cells = <1>;
 572                 rockchip,hw-tshut-temp = <95000>;
 573                 status = "disabled";
 574         };
 575
 576         gmac: ethernet@ff290000 {
 577                 compatible = "rockchip,rk3288-gmac";
 578                 reg = <0x0 0xff290000 0x0 0x10000>;
 579                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 580                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 581                 interrupt-names = "macirq", "eth_wake_irq";
 582                 rockchip,grf = <&grf>;
 583                 clocks = <&cru SCLK_MAC>,
 584                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 585                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 586                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 587                 clock-names = "stmmaceth",
 588                         "mac_clk_rx", "mac_clk_tx",
 589                         "clk_mac_ref", "clk_mac_refout",
 590                         "aclk_mac", "pclk_mac";
 591                 resets = <&cru SRST_MAC>;
 592                 reset-names = "stmmaceth";
 593                 status = "disabled";
 594         };
 595
 596         usb_host0_ehci: usb@ff500000 {
 597                 compatible = "generic-ehci";
 598                 reg = <0x0 0xff500000 0x0 0x100>;
 599                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&cru HCLK_USBHOST0>;
 601                 clock-names = "usbhost";
 602                 phys = <&usbphy1>;
 603                 phy-names = "usb";
 604                 status = "disabled";
 605         };
 606
 607         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 608
 609         usb_host1: usb@ff540000 {
 610                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 611                                 "snps,dwc2";
 612                 reg = <0x0 0xff540000 0x0 0x40000>;
 613                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&cru HCLK_USBHOST1>;
 615                 clock-names = "otg";
 616                 dr_mode = "host";
 617                 phys = <&usbphy2>;
 618                 phy-names = "usb2-phy";
 619                 status = "disabled";
 620         };
 621
 622         usb_otg: usb@ff580000 {
 623                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 624                                 "snps,dwc2";
 625                 reg = <0x0 0xff580000 0x0 0x40000>;
 626                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 627                 clocks = <&cru HCLK_OTG0>;
 628                 clock-names = "otg";
 629                 dr_mode = "otg";
 630                 g-np-tx-fifo-size = <16>;
 631                 g-rx-fifo-size = <275>;
 632                 g-tx-fifo-size = <256 128 128 64 64 32>;
 633                 phys = <&usbphy0>;
 634                 phy-names = "usb2-phy";
 635                 status = "disabled";
 636         };
 637
 638         usb_hsic: usb@ff5c0000 {
 639                 compatible = "generic-ehci";
 640                 reg = <0x0 0xff5c0000 0x0 0x100>;
 641                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&cru HCLK_HSIC>;
 643                 clock-names = "usbhost";
 644                 status = "disabled";
 645         };
 646
 647         i2c0: i2c@ff650000 {
 648                 compatible = "rockchip,rk3288-i2c";
 649                 reg = <0x0 0xff650000 0x0 0x1000>;
 650                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 clock-names = "i2c";
 654                 clocks = <&cru PCLK_I2C0>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&i2c0_xfer>;
 657                 status = "disabled";
 658         };
 659
 660         i2c2: i2c@ff660000 {
 661                 compatible = "rockchip,rk3288-i2c";
 662                 reg = <0x0 0xff660000 0x0 0x1000>;
 663                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 664                 #address-cells = <1>;
 665                 #size-cells = <0>;
 666                 clock-names = "i2c";
 667                 clocks = <&cru PCLK_I2C2>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&i2c2_xfer>;
 670                 status = "disabled";
 671         };
 672
 673         pwm0: pwm@ff680000 {
 674                 compatible = "rockchip,rk3288-pwm";
 675                 reg = <0x0 0xff680000 0x0 0x10>;
 676                 #pwm-cells = <3>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&pwm0_pin>;
 679                 clocks = <&cru PCLK_PWM>;
 680                 clock-names = "pwm";
 681                 status = "disabled";
 682         };
 683
 684         pwm1: pwm@ff680010 {
 685                 compatible = "rockchip,rk3288-pwm";
 686                 reg = <0x0 0xff680010 0x0 0x10>;
 687                 #pwm-cells = <3>;
 688                 pinctrl-names = "default";
 689                 pinctrl-0 = <&pwm1_pin>;
 690                 clocks = <&cru PCLK_PWM>;
 691                 clock-names = "pwm";
 692                 status = "disabled";
 693         };
 694
 695         pwm2: pwm@ff680020 {
 696                 compatible = "rockchip,rk3288-pwm";
 697                 reg = <0x0 0xff680020 0x0 0x10>;
 698                 #pwm-cells = <3>;
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&pwm2_pin>;
 701                 clocks = <&cru PCLK_PWM>;
 702                 clock-names = "pwm";
 703                 status = "disabled";
 704         };
 705
 706         pwm3: pwm@ff680030 {
 707                 compatible = "rockchip,rk3288-pwm";
 708                 reg = <0x0 0xff680030 0x0 0x10>;
 709                 #pwm-cells = <2>;
 710                 pinctrl-names = "default";
 711                 pinctrl-0 = <&pwm3_pin>;
 712                 clocks = <&cru PCLK_PWM>;
 713                 clock-names = "pwm";
 714                 status = "disabled";
 715         };
 716
 717         bus_intmem@ff700000 {
 718                 compatible = "mmio-sram";
 719                 reg = <0x0 0xff700000 0x0 0x18000>;
 720                 #address-cells = <1>;
 721                 #size-cells = <1>;
 722                 ranges = <0 0x0 0xff700000 0x18000>;
 723                 smp-sram@0 {
 724                         compatible = "rockchip,rk3066-smp-sram";
 725                         reg = <0x00 0x10>;
 726                 };
 727         };
 728
 729         sram@ff720000 {
 730                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 731                 reg = <0x0 0xff720000 0x0 0x1000>;
 732         };
 733
 734         pmu: power-management@ff730000 {
 735                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 736                 reg = <0x0 0xff730000 0x0 0x100>;
 737
 738                 power: power-controller {
 739                         compatible = "rockchip,rk3288-power-controller";
 740                         #power-domain-cells = <1>;
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743
 744                         assigned-clocks = <&cru SCLK_EDP_24M>;
 745                         assigned-clock-parents = <&xin24m>;
 746
 747                         /*
 748                          * Note: Although SCLK_* are the working clocks
 749                          * of device without including on the NOC, needed for
 750                          * synchronous reset.
 751                          *
 752                          * The clocks on the which NOC:
 753                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 754                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 755                          * ACLK_RGA is on ACLK_RGA_NIU.
 756                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 757                          *
 758                          * Which clock are device clocks:
 759                          *      clocks          devices
 760                          *      *_IEP           IEP:Image Enhancement Processor
 761                          *      *_ISP           ISP:Image Signal Processing
 762                          *      *_VIP           VIP:Video Input Processor
 763                          *      *_VOP*          VOP:Visual Output Processor
 764                          *      *_RGA           RGA
 765                          *      *_EDP*          EDP
 766                          *      *_LVDS_*        LVDS
 767                          *      *_HDMI          HDMI
 768                          *      *_MIPI_*        MIPI
 769                          */
 770                         pd_vio@RK3288_PD_VIO {
 771                                 reg = <RK3288_PD_VIO>;
 772                                 clocks = <&cru ACLK_IEP>,
 773                                          <&cru ACLK_ISP>,
 774                                          <&cru ACLK_RGA>,
 775                                          <&cru ACLK_VIP>,
 776                                          <&cru ACLK_VOP0>,
 777                                          <&cru ACLK_VOP1>,
 778                                          <&cru DCLK_VOP0>,
 779                                          <&cru DCLK_VOP1>,
 780                                          <&cru HCLK_IEP>,
 781                                          <&cru HCLK_ISP>,
 782                                          <&cru HCLK_RGA>,
 783                                          <&cru HCLK_VIP>,
 784                                          <&cru HCLK_VOP0>,
 785                                          <&cru HCLK_VOP1>,
 786                                          <&cru PCLK_EDP_CTRL>,
 787                                          <&cru PCLK_HDMI_CTRL>,
 788                                          <&cru PCLK_LVDS_PHY>,
 789                                          <&cru PCLK_MIPI_CSI>,
 790                                          <&cru PCLK_MIPI_DSI0>,
 791                                          <&cru PCLK_MIPI_DSI1>,
 792                                          <&cru SCLK_EDP_24M>,
 793                                          <&cru SCLK_EDP>,
 794                                          <&cru SCLK_ISP_JPE>,
 795                                          <&cru SCLK_ISP>,
 796                                          <&cru SCLK_RGA>;
 797                                 pm_qos = <&qos_vio0_iep>,
 798                                          <&qos_vio1_vop>,
 799                                          <&qos_vio1_isp_w0>,
 800                                          <&qos_vio1_isp_w1>,
 801                                          <&qos_vio0_vop>,
 802                                          <&qos_vio0_vip>,
 803                                          <&qos_vio2_rga_r>,
 804                                          <&qos_vio2_rga_w>,
 805                                          <&qos_vio1_isp_r>;
 806                         };
 807
 808                         /*
 809                          * Note: The following 3 are HEVC(H.265) clocks,
 810                          * and on the ACLK_HEVC_NIU (NOC).
 811                          */
 812                         pd_hevc@RK3288_PD_HEVC {
 813                                 reg = <RK3288_PD_HEVC>;
 814                                 clocks = <&cru ACLK_HEVC>,
 815                                          <&cru SCLK_HEVC_CABAC>,
 816                                          <&cru SCLK_HEVC_CORE>;
 817                                 pm_qos = <&qos_hevc_r>,
 818                                          <&qos_hevc_w>;
 819                         };
 820
 821                         /*
 822                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 823                          * (video endecoder & decoder) clocks that on the
 824                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 825                          */
 826                         pd_video@RK3288_PD_VIDEO {
 827                                 reg = <RK3288_PD_VIDEO>;
 828                                 clocks = <&cru ACLK_VCODEC>,
 829                                          <&cru HCLK_VCODEC>;
 830                                 pm_qos = <&qos_video>;
 831                         };
 832
 833                         /*
 834                          * Note: ACLK_GPU is the GPU clock,
 835                          * and on the ACLK_GPU_NIU (NOC).
 836                          */
 837                         pd_gpu@RK3288_PD_GPU {
 838                                 reg = <RK3288_PD_GPU>;
 839                                 clocks = <&cru ACLK_GPU>;
 840                                 pm_qos = <&qos_gpu_r>,
 841                                          <&qos_gpu_w>;
 842                         };
 843                 };
 844
 845                 reboot-mode {
 846                         compatible = "syscon-reboot-mode";
 847                         offset = <0x94>;
 848                         mode-normal = <BOOT_NORMAL>;
 849                         mode-recovery = <BOOT_RECOVERY>;
 850                         mode-bootloader = <BOOT_FASTBOOT>;
 851                         mode-loader = <BOOT_BL_DOWNLOAD>;
 852                 };
 853         };
 854
 855         sgrf: syscon@ff740000 {
 856                 compatible = "rockchip,rk3288-sgrf", "syscon";
 857                 reg = <0x0 0xff740000 0x0 0x1000>;
 858         };
 859
 860         cru: clock-controller@ff760000 {
 861                 compatible = "rockchip,rk3288-cru";
 862                 reg = <0x0 0xff760000 0x0 0x1000>;
 863                 rockchip,grf = <&grf>;
 864                 #clock-cells = <1>;
 865                 #reset-cells = <1>;
 866                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 867                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 868                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 869                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 870                                   <&cru PCLK_PERI>;
 871                 assigned-clock-rates = <594000000>, <400000000>,
 872                                        <500000000>, <300000000>,
 873                                        <150000000>, <75000000>,
 874                                        <300000000>, <150000000>,
 875                                        <75000000>;
 876         };
 877
 878         grf: syscon@ff770000 {
 879                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 880                 reg = <0x0 0xff770000 0x0 0x1000>;
 881
 882                 edp_phy: edp-phy {
 883                         compatible = "rockchip,rk3288-dp-phy";
 884                         clocks = <&cru SCLK_EDP_24M>;
 885                         clock-names = "24m";
 886                         #phy-cells = <0>;
 887                         status = "disabled";
 888                 };
 889
 890                 io_domains: io-domains {
 891                         compatible = "rockchip,rk3288-io-voltage-domain";
 892                         status = "disabled";
 893                 };
 894
 895                 usbphy: usbphy {
 896                         compatible = "rockchip,rk3288-usb-phy";
 897                         #address-cells = <1>;
 898                         #size-cells = <0>;
 899                         status = "disabled";
 900
 901                         usbphy0: usb-phy@320 {
 902                                 #phy-cells = <0>;
 903                                 reg = <0x320>;
 904                                 clocks = <&cru SCLK_OTGPHY0>;
 905                                 clock-names = "phyclk";
 906                                 #clock-cells = <0>;
 907                         };
 908
 909                         usbphy1: usb-phy@334 {
 910                                 #phy-cells = <0>;
 911                                 reg = <0x334>;
 912                                 clocks = <&cru SCLK_OTGPHY1>;
 913                                 clock-names = "phyclk";
 914                                 #clock-cells = <0>;
 915                         };
 916
 917                         usbphy2: usb-phy@348 {
 918                                 #phy-cells = <0>;
 919                                 reg = <0x348>;
 920                                 clocks = <&cru SCLK_OTGPHY2>;
 921                                 clock-names = "phyclk";
 922                                 #clock-cells = <0>;
 923                         };
 924                 };
 925         };
 926
 927         wdt: watchdog@ff800000 {
 928                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 929                 reg = <0x0 0xff800000 0x0 0x100>;
 930                 clocks = <&cru PCLK_WDT>;
 931                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 932                 status = "disabled";
 933         };
 934
 935         spdif: sound@ff88b0000 {
 936                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 937                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 938                 #sound-dai-cells = <0>;
 939                 clock-names = "hclk", "mclk";
 940                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 941                 dmas = <&dmac_bus_s 3>;
 942                 dma-names = "tx";
 943                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 944                 pinctrl-names = "default";
 945                 pinctrl-0 = <&spdif_tx>;
 946                 rockchip,grf = <&grf>;
 947                 status = "disabled";
 948         };
 949
 950         i2s: i2s@ff890000 {
 951                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 952                 reg = <0x0 0xff890000 0x0 0x10000>;
 953                 #sound-dai-cells = <0>;
 954                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 955                 #address-cells = <1>;
 956                 #size-cells = <0>;
 957                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 958                 dma-names = "tx", "rx";
 959                 clock-names = "i2s_hclk", "i2s_clk";
 960                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 961                 pinctrl-names = "default";
 962                 pinctrl-0 = <&i2s0_bus>;
 963                 rockchip,playback-channels = <8>;
 964                 rockchip,capture-channels = <2>;
 965                 status = "disabled";
 966         };
 967
 968         crypto: cypto-controller@ff8a0000 {
 969                 compatible = "rockchip,rk3288-crypto";
 970                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 971                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 972                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 973                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 974                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 975                 resets = <&cru SRST_CRYPTO>;
 976                 reset-names = "crypto-rst";
 977                 status = "okay";
 978         };
 979
 980         iep_mmu: iommu@ff900800 {
 981                 compatible = "rockchip,iommu";
 982                 reg = <0x0 0xff900800 0x0 0x40>;
 983                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 984                 interrupt-names = "iep_mmu";
 985                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 986                 clock-names = "aclk", "iface";
 987                 #iommu-cells = <0>;
 988                 status = "disabled";
 989         };
 990
 991         isp_mmu: iommu@ff914000 {
 992                 compatible = "rockchip,iommu";
 993                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
 994                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 995                 interrupt-names = "isp_mmu";
 996                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
 997                 clock-names = "aclk", "iface";
 998                 #iommu-cells = <0>;
 999                 rockchip,disable-mmu-reset;
1000                 status = "disabled";
1001         };
1002
1003         rga: rga@ff920000 {
1004                 compatible = "rockchip,rk3288-rga";
1005                 reg = <0x0 0xff920000 0x0 0x180>;
1006                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1007                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1008                 clock-names = "aclk", "hclk", "sclk";
1009                 power-domains = <&power RK3288_PD_VIO>;
1010                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1011                 reset-names = "core", "axi", "ahb";
1012         };
1013
1014         vopb: vop@ff930000 {
1015                 compatible = "rockchip,rk3288-vop";
1016                 reg = <0x0 0xff930000 0x0 0x19c>;
1017                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1019                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1020                 power-domains = <&power RK3288_PD_VIO>;
1021                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1022                 reset-names = "axi", "ahb", "dclk";
1023                 iommus = <&vopb_mmu>;
1024                 status = "disabled";
1025
1026                 vopb_out: port {
1027                         #address-cells = <1>;
1028                         #size-cells = <0>;
1029
1030                         vopb_out_hdmi: endpoint@0 {
1031                                 reg = <0>;
1032                                 remote-endpoint = <&hdmi_in_vopb>;
1033                         };
1034
1035                         vopb_out_edp: endpoint@1 {
1036                                 reg = <1>;
1037                                 remote-endpoint = <&edp_in_vopb>;
1038                         };
1039
1040                         vopb_out_mipi: endpoint@2 {
1041                                 reg = <2>;
1042                                 remote-endpoint = <&mipi_in_vopb>;
1043                         };
1044
1045                         vopb_out_lvds: endpoint@3 {
1046                                 reg = <3>;
1047                                 remote-endpoint = <&lvds_in_vopb>;
1048                         };
1049                 };
1050         };
1051
1052         vopb_mmu: iommu@ff930300 {
1053                 compatible = "rockchip,iommu";
1054                 reg = <0x0 0xff930300 0x0 0x100>;
1055                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "vopb_mmu";
1057                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1058                 clock-names = "aclk", "iface";
1059                 power-domains = <&power RK3288_PD_VIO>;
1060                 #iommu-cells = <0>;
1061                 status = "disabled";
1062         };
1063
1064         vopl: vop@ff940000 {
1065                 compatible = "rockchip,rk3288-vop";
1066                 reg = <0x0 0xff940000 0x0 0x19c>;
1067                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1068                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1069                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1070                 power-domains = <&power RK3288_PD_VIO>;
1071                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1072                 reset-names = "axi", "ahb", "dclk";
1073                 iommus = <&vopl_mmu>;
1074                 status = "disabled";
1075
1076                 vopl_out: port {
1077                         #address-cells = <1>;
1078                         #size-cells = <0>;
1079
1080                         vopl_out_hdmi: endpoint@0 {
1081                                 reg = <0>;
1082                                 remote-endpoint = <&hdmi_in_vopl>;
1083                         };
1084
1085                         vopl_out_edp: endpoint@1 {
1086                                 reg = <1>;
1087                                 remote-endpoint = <&edp_in_vopl>;
1088                         };
1089
1090                         vopl_out_mipi: endpoint@2 {
1091                                 reg = <2>;
1092                                 remote-endpoint = <&mipi_in_vopl>;
1093                         };
1094
1095                         vopl_out_lvds: endpoint@3 {
1096                                 reg = <3>;
1097                                 remote-endpoint = <&lvds_in_vopl>;
1098                         };
1099                 };
1100         };
1101
1102         vopl_mmu: iommu@ff940300 {
1103                 compatible = "rockchip,iommu";
1104                 reg = <0x0 0xff940300 0x0 0x100>;
1105                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1106                 interrupt-names = "vopl_mmu";
1107                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1108                 clock-names = "aclk", "iface";
1109                 power-domains = <&power RK3288_PD_VIO>;
1110                 #iommu-cells = <0>;
1111                 status = "disabled";
1112         };
1113
1114         mipi_dsi: mipi@ff960000 {
1115                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1116                 reg = <0x0 0xff960000 0x0 0x4000>;
1117                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1118                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1119                 clock-names = "ref", "pclk";
1120                 power-domains = <&power RK3288_PD_VIO>;
1121                 rockchip,grf = <&grf>;
1122                 status = "disabled";
1123
1124                 ports {
1125                         mipi_in: port {
1126                                 #address-cells = <1>;
1127                                 #size-cells = <0>;
1128                                 mipi_in_vopb: endpoint@0 {
1129                                         reg = <0>;
1130                                         remote-endpoint = <&vopb_out_mipi>;
1131                                 };
1132                                 mipi_in_vopl: endpoint@1 {
1133                                         reg = <1>;
1134                                         remote-endpoint = <&vopl_out_mipi>;
1135                                 };
1136                         };
1137                 };
1138         };
1139
1140         lvds: lvds@ff96c000 {
1141                 compatible = "rockchip,rk3288-lvds";
1142                 reg = <0x0 0xff96c000 0x0 0x4000>;
1143                 clocks = <&cru PCLK_LVDS_PHY>;
1144                 clock-names = "pclk_lvds";
1145                 pinctrl-names = "lcdc";
1146                 pinctrl-0 = <&lcdc_ctl>;
1147                 power-domains = <&power RK3288_PD_VIO>;
1148                 rockchip,grf = <&grf>;
1149                 status = "disabled";
1150
1151                 ports {
1152                         #address-cells = <1>;
1153                         #size-cells = <0>;
1154
1155                         lvds_in: port@0 {
1156                                 reg = <0>;
1157
1158                                 #address-cells = <1>;
1159                                 #size-cells = <0>;
1160
1161                                 lvds_in_vopb: endpoint@0 {
1162                                         reg = <0>;
1163                                         remote-endpoint = <&vopb_out_lvds>;
1164                                 };
1165                                 lvds_in_vopl: endpoint@1 {
1166                                         reg = <1>;
1167                                         remote-endpoint = <&vopl_out_lvds>;
1168                                 };
1169                         };
1170                 };
1171         };
1172
1173         edp: dp@ff970000 {
1174                 compatible = "rockchip,rk3288-dp";
1175                 reg = <0x0 0xff970000 0x0 0x4000>;
1176                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1177                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1178                 clock-names = "dp", "pclk";
1179                 phys = <&edp_phy>;
1180                 phy-names = "dp";
1181                 resets = <&cru SRST_EDP>;
1182                 reset-names = "dp";
1183                 rockchip,grf = <&grf>;
1184                 status = "disabled";
1185
1186                 ports {
1187                         #address-cells = <1>;
1188                         #size-cells = <0>;
1189                         edp_in: port@0 {
1190                                 reg = <0>;
1191                                 #address-cells = <1>;
1192                                 #size-cells = <0>;
1193                                 edp_in_vopb: endpoint@0 {
1194                                         reg = <0>;
1195                                         remote-endpoint = <&vopb_out_edp>;
1196                                 };
1197                                 edp_in_vopl: endpoint@1 {
1198                                         reg = <1>;
1199                                         remote-endpoint = <&vopl_out_edp>;
1200                                 };
1201                         };
1202                 };
1203         };
1204
1205         hdmi: hdmi@ff980000 {
1206                 compatible = "rockchip,rk3288-dw-hdmi";
1207                 reg = <0x0 0xff980000 0x0 0x20000>;
1208                 reg-io-width = <4>;
1209                 #sound-dai-cells = <0>;
1210                 rockchip,grf = <&grf>;
1211                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1212                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1213                 clock-names = "iahb", "isfr", "cec";
1214                 power-domains = <&power RK3288_PD_VIO>;
1215                 status = "disabled";
1216
1217                 ports {
1218                         hdmi_in: port {
1219                                 #address-cells = <1>;
1220                                 #size-cells = <0>;
1221                                 hdmi_in_vopb: endpoint@0 {
1222                                         reg = <0>;
1223                                         remote-endpoint = <&vopb_out_hdmi>;
1224                                 };
1225                                 hdmi_in_vopl: endpoint@1 {
1226                                         reg = <1>;
1227                                         remote-endpoint = <&vopl_out_hdmi>;
1228                                 };
1229                         };
1230                 };
1231         };
1232
1233         vpu: video-codec@ff9a0000 {
1234                 compatible = "rockchip,rk3288-vpu";
1235                 reg = <0x0 0xff9a0000 0x0 0x800>;
1236                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1237                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1238                 interrupt-names = "vepu", "vdpu";
1239                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1240                 clock-names = "aclk", "hclk";
1241                 iommus = <&vpu_mmu>;
1242                 power-domains = <&power RK3288_PD_VIDEO>;
1243         };
1244
1245         vpu_mmu: iommu@ff9a0800 {
1246                 compatible = "rockchip,iommu";
1247                 reg = <0x0 0xff9a0800 0x0 0x100>;
1248                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1249                 interrupt-names = "vpu_mmu";
1250                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1251                 clock-names = "aclk", "iface";
1252                 #iommu-cells = <0>;
1253                 power-domains = <&power RK3288_PD_VIDEO>;
1254         };
1255
1256         hevc_mmu: iommu@ff9c0440 {
1257                 compatible = "rockchip,iommu";
1258                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1259                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1260                 interrupt-names = "hevc_mmu";
1261                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1262                 clock-names = "aclk", "iface";
1263                 #iommu-cells = <0>;
1264                 status = "disabled";
1265         };
1266
1267         gpu: gpu@ffa30000 {
1268                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1269                 reg = <0x0 0xffa30000 0x0 0x10000>;
1270                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1271                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1272                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "job", "mmu", "gpu";
1274                 clocks = <&cru ACLK_GPU>;
1275                 operating-points-v2 = <&gpu_opp_table>;
1276                 power-domains = <&power RK3288_PD_GPU>;
1277                 status = "disabled";
1278         };
1279
1280         gpu_opp_table: gpu-opp-table {
1281                 compatible = "operating-points-v2";
1282
1283                 opp-100000000 {
1284                         opp-hz = /bits/ 64 <100000000>;
1285                         opp-microvolt = <950000>;
1286                 };
1287                 opp-200000000 {
1288                         opp-hz = /bits/ 64 <200000000>;
1289                         opp-microvolt = <950000>;
1290                 };
1291                 opp-300000000 {
1292                         opp-hz = /bits/ 64 <300000000>;
1293                         opp-microvolt = <1000000>;
1294                 };
1295                 opp-400000000 {
1296                         opp-hz = /bits/ 64 <400000000>;
1297                         opp-microvolt = <1100000>;
1298                 };
1299                 opp-500000000 {
1300                         opp-hz = /bits/ 64 <500000000>;
1301                         opp-microvolt = <1200000>;
1302                 };
1303                 opp-600000000 {
1304                         opp-hz = /bits/ 64 <600000000>;
1305                         opp-microvolt = <1250000>;
1306                 };
1307         };
1308
1309         qos_gpu_r: qos@ffaa0000 {
1310                 compatible = "syscon";
1311                 reg = <0x0 0xffaa0000 0x0 0x20>;
1312         };
1313
1314         qos_gpu_w: qos@ffaa0080 {
1315                 compatible = "syscon";
1316                 reg = <0x0 0xffaa0080 0x0 0x20>;
1317         };
1318
1319         qos_vio1_vop: qos@ffad0000 {
1320                 compatible = "syscon";
1321                 reg = <0x0 0xffad0000 0x0 0x20>;
1322         };
1323
1324         qos_vio1_isp_w0: qos@ffad0100 {
1325                 compatible = "syscon";
1326                 reg = <0x0 0xffad0100 0x0 0x20>;
1327         };
1328
1329         qos_vio1_isp_w1: qos@ffad0180 {
1330                 compatible = "syscon";
1331                 reg = <0x0 0xffad0180 0x0 0x20>;
1332         };
1333
1334         qos_vio0_vop: qos@ffad0400 {
1335                 compatible = "syscon";
1336                 reg = <0x0 0xffad0400 0x0 0x20>;
1337         };
1338
1339         qos_vio0_vip: qos@ffad0480 {
1340                 compatible = "syscon";
1341                 reg = <0x0 0xffad0480 0x0 0x20>;
1342         };
1343
1344         qos_vio0_iep: qos@ffad0500 {
1345                 compatible = "syscon";
1346                 reg = <0x0 0xffad0500 0x0 0x20>;
1347         };
1348
1349         qos_vio2_rga_r: qos@ffad0800 {
1350                 compatible = "syscon";
1351                 reg = <0x0 0xffad0800 0x0 0x20>;
1352         };
1353
1354         qos_vio2_rga_w: qos@ffad0880 {
1355                 compatible = "syscon";
1356                 reg = <0x0 0xffad0880 0x0 0x20>;
1357         };
1358
1359         qos_vio1_isp_r: qos@ffad0900 {
1360                 compatible = "syscon";
1361                 reg = <0x0 0xffad0900 0x0 0x20>;
1362         };
1363
1364         qos_video: qos@ffae0000 {
1365                 compatible = "syscon";
1366                 reg = <0x0 0xffae0000 0x0 0x20>;
1367         };
1368
1369         qos_hevc_r: qos@ffaf0000 {
1370                 compatible = "syscon";
1371                 reg = <0x0 0xffaf0000 0x0 0x20>;
1372         };
1373
1374         qos_hevc_w: qos@ffaf0080 {
1375                 compatible = "syscon";
1376                 reg = <0x0 0xffaf0080 0x0 0x20>;
1377         };
1378
1379         gic: interrupt-controller@ffc01000 {
1380                 compatible = "arm,gic-400";
1381                 interrupt-controller;
1382                 #interrupt-cells = <3>;
1383                 #address-cells = <0>;
1384
1385                 reg = <0x0 0xffc01000 0x0 0x1000>,
1386                       <0x0 0xffc02000 0x0 0x2000>,
1387                       <0x0 0xffc04000 0x0 0x2000>,
1388                       <0x0 0xffc06000 0x0 0x2000>;
1389                 interrupts = <GIC_PPI 9 0xf04>;
1390         };
1391
1392         efuse: efuse@ffb40000 {
1393                 compatible = "rockchip,rk3288-efuse";
1394                 reg = <0x0 0xffb40000 0x0 0x20>;
1395                 #address-cells = <1>;
1396                 #size-cells = <1>;
1397                 clocks = <&cru PCLK_EFUSE256>;
1398                 clock-names = "pclk_efuse";
1399
1400                 cpu_leakage: cpu_leakage@17 {
1401                         reg = <0x17 0x1>;
1402                 };
1403         };
1404
1405         pinctrl: pinctrl {
1406                 compatible = "rockchip,rk3288-pinctrl";
1407                 rockchip,grf = <&grf>;
1408                 rockchip,pmu = <&pmu>;
1409                 #address-cells = <2>;
1410                 #size-cells = <2>;
1411                 ranges;
1412
1413                 gpio0: gpio0@ff750000 {
1414                         compatible = "rockchip,gpio-bank";
1415                         reg = <0x0 0xff750000 0x0 0x100>;
1416                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1417                         clocks = <&cru PCLK_GPIO0>;
1418
1419                         gpio-controller;
1420                         #gpio-cells = <2>;
1421
1422                         interrupt-controller;
1423                         #interrupt-cells = <2>;
1424                 };
1425
1426                 gpio1: gpio1@ff780000 {
1427                         compatible = "rockchip,gpio-bank";
1428                         reg = <0x0 0xff780000 0x0 0x100>;
1429                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1430                         clocks = <&cru PCLK_GPIO1>;
1431
1432                         gpio-controller;
1433                         #gpio-cells = <2>;
1434
1435                         interrupt-controller;
1436                         #interrupt-cells = <2>;
1437                 };
1438
1439                 gpio2: gpio2@ff790000 {
1440                         compatible = "rockchip,gpio-bank";
1441                         reg = <0x0 0xff790000 0x0 0x100>;
1442                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1443                         clocks = <&cru PCLK_GPIO2>;
1444
1445                         gpio-controller;
1446                         #gpio-cells = <2>;
1447
1448                         interrupt-controller;
1449                         #interrupt-cells = <2>;
1450                 };
1451
1452                 gpio3: gpio3@ff7a0000 {
1453                         compatible = "rockchip,gpio-bank";
1454                         reg = <0x0 0xff7a0000 0x0 0x100>;
1455                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1456                         clocks = <&cru PCLK_GPIO3>;
1457
1458                         gpio-controller;
1459                         #gpio-cells = <2>;
1460
1461                         interrupt-controller;
1462                         #interrupt-cells = <2>;
1463                 };
1464
1465                 gpio4: gpio4@ff7b0000 {
1466                         compatible = "rockchip,gpio-bank";
1467                         reg = <0x0 0xff7b0000 0x0 0x100>;
1468                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1469                         clocks = <&cru PCLK_GPIO4>;
1470
1471                         gpio-controller;
1472                         #gpio-cells = <2>;
1473
1474                         interrupt-controller;
1475                         #interrupt-cells = <2>;
1476                 };
1477
1478                 gpio5: gpio5@ff7c0000 {
1479                         compatible = "rockchip,gpio-bank";
1480                         reg = <0x0 0xff7c0000 0x0 0x100>;
1481                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1482                         clocks = <&cru PCLK_GPIO5>;
1483
1484                         gpio-controller;
1485                         #gpio-cells = <2>;
1486
1487                         interrupt-controller;
1488                         #interrupt-cells = <2>;
1489                 };
1490
1491                 gpio6: gpio6@ff7d0000 {
1492                         compatible = "rockchip,gpio-bank";
1493                         reg = <0x0 0xff7d0000 0x0 0x100>;
1494                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1495                         clocks = <&cru PCLK_GPIO6>;
1496
1497                         gpio-controller;
1498                         #gpio-cells = <2>;
1499
1500                         interrupt-controller;
1501                         #interrupt-cells = <2>;
1502                 };
1503
1504                 gpio7: gpio7@ff7e0000 {
1505                         compatible = "rockchip,gpio-bank";
1506                         reg = <0x0 0xff7e0000 0x0 0x100>;
1507                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1508                         clocks = <&cru PCLK_GPIO7>;
1509
1510                         gpio-controller;
1511                         #gpio-cells = <2>;
1512
1513                         interrupt-controller;
1514                         #interrupt-cells = <2>;
1515                 };
1516
1517                 gpio8: gpio8@ff7f0000 {
1518                         compatible = "rockchip,gpio-bank";
1519                         reg = <0x0 0xff7f0000 0x0 0x100>;
1520                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1521                         clocks = <&cru PCLK_GPIO8>;
1522
1523                         gpio-controller;
1524                         #gpio-cells = <2>;
1525
1526                         interrupt-controller;
1527                         #interrupt-cells = <2>;
1528                 };
1529
1530                 hdmi {
1531                         hdmi_cec_c0: hdmi-cec-c0 {
1532                                 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1533                         };
1534
1535                         hdmi_cec_c7: hdmi-cec-c7 {
1536                                 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
1537                         };
1538
1539                         hdmi_ddc: hdmi-ddc {
1540                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1541                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1542                         };
1543                 };
1544
1545                 pcfg_pull_up: pcfg-pull-up {
1546                         bias-pull-up;
1547                 };
1548
1549                 pcfg_pull_down: pcfg-pull-down {
1550                         bias-pull-down;
1551                 };
1552
1553                 pcfg_pull_none: pcfg-pull-none {
1554                         bias-disable;
1555                 };
1556
1557                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1558                         bias-disable;
1559                         drive-strength = <12>;
1560                 };
1561
1562                 sleep {
1563                         global_pwroff: global-pwroff {
1564                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1565                         };
1566
1567                         ddrio_pwroff: ddrio-pwroff {
1568                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1569                         };
1570
1571                         ddr0_retention: ddr0-retention {
1572                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         ddr1_retention: ddr1-retention {
1576                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1577                         };
1578                 };
1579
1580                 edp {
1581                         edp_hpd: edp-hpd {
1582                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1583                         };
1584                 };
1585
1586                 i2c0 {
1587                         i2c0_xfer: i2c0-xfer {
1588                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1589                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 i2c1 {
1594                         i2c1_xfer: i2c1-xfer {
1595                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1596                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1597                         };
1598                 };
1599
1600                 i2c2 {
1601                         i2c2_xfer: i2c2-xfer {
1602                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1603                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605                 };
1606
1607                 i2c3 {
1608                         i2c3_xfer: i2c3-xfer {
1609                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1610                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 i2c4 {
1615                         i2c4_xfer: i2c4-xfer {
1616                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1617                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 i2c5 {
1622                         i2c5_xfer: i2c5-xfer {
1623                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1624                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1625                         };
1626                 };
1627
1628                 i2s0 {
1629                         i2s0_bus: i2s0-bus {
1630                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1631                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1632                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1633                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1634                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1635                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 lcdc {
1640                         lcdc_ctl: lcdc-ctl {
1641                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1642                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1643                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1644                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1645                         };
1646                 };
1647
1648                 sdmmc {
1649                         sdmmc_clk: sdmmc-clk {
1650                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1651                         };
1652
1653                         sdmmc_cmd: sdmmc-cmd {
1654                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1655                         };
1656
1657                         sdmmc_cd: sdmmc-cd {
1658                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1659                         };
1660
1661                         sdmmc_bus1: sdmmc-bus1 {
1662                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1663                         };
1664
1665                         sdmmc_bus4: sdmmc-bus4 {
1666                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1667                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1668                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1669                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1670                         };
1671                 };
1672
1673                 sdio0 {
1674                         sdio0_bus1: sdio0-bus1 {
1675                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1676                         };
1677
1678                         sdio0_bus4: sdio0-bus4 {
1679                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1680                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1681                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1682                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1683                         };
1684
1685                         sdio0_cmd: sdio0-cmd {
1686                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1687                         };
1688
1689                         sdio0_clk: sdio0-clk {
1690                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692
1693                         sdio0_cd: sdio0-cd {
1694                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1695                         };
1696
1697                         sdio0_wp: sdio0-wp {
1698                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1699                         };
1700
1701                         sdio0_pwr: sdio0-pwr {
1702                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1703                         };
1704
1705                         sdio0_bkpwr: sdio0-bkpwr {
1706                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1707                         };
1708
1709                         sdio0_int: sdio0-int {
1710                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1711                         };
1712                 };
1713
1714                 sdio1 {
1715                         sdio1_bus1: sdio1-bus1 {
1716                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio1_bus4: sdio1-bus4 {
1720                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1721                                                 <3 25 4 &pcfg_pull_up>,
1722                                                 <3 26 4 &pcfg_pull_up>,
1723                                                 <3 27 4 &pcfg_pull_up>;
1724                         };
1725
1726                         sdio1_cd: sdio1-cd {
1727                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1728                         };
1729
1730                         sdio1_wp: sdio1-wp {
1731                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1732                         };
1733
1734                         sdio1_bkpwr: sdio1-bkpwr {
1735                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1736                         };
1737
1738                         sdio1_int: sdio1-int {
1739                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1740                         };
1741
1742                         sdio1_cmd: sdio1-cmd {
1743                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1744                         };
1745
1746                         sdio1_clk: sdio1-clk {
1747                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1748                         };
1749
1750                         sdio1_pwr: sdio1-pwr {
1751                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1752                         };
1753                 };
1754
1755                 emmc {
1756                         emmc_clk: emmc-clk {
1757                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1758                         };
1759
1760                         emmc_cmd: emmc-cmd {
1761                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1762                         };
1763
1764                         emmc_pwr: emmc-pwr {
1765                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1766                         };
1767
1768                         emmc_bus1: emmc-bus1 {
1769                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1770                         };
1771
1772                         emmc_bus4: emmc-bus4 {
1773                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1774                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1775                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1776                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1777                         };
1778
1779                         emmc_bus8: emmc-bus8 {
1780                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1781                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1782                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1783                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1784                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1785                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1786                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1787                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                 };
1790
1791                 spi0 {
1792                         spi0_clk: spi0-clk {
1793                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1794                         };
1795                         spi0_cs0: spi0-cs0 {
1796                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1797                         };
1798                         spi0_tx: spi0-tx {
1799                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1800                         };
1801                         spi0_rx: spi0-rx {
1802                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1803                         };
1804                         spi0_cs1: spi0-cs1 {
1805                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1806                         };
1807                 };
1808                 spi1 {
1809                         spi1_clk: spi1-clk {
1810                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1811                         };
1812                         spi1_cs0: spi1-cs0 {
1813                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1814                         };
1815                         spi1_rx: spi1-rx {
1816                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1817                         };
1818                         spi1_tx: spi1-tx {
1819                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1820                         };
1821                 };
1822
1823                 spi2 {
1824                         spi2_cs1: spi2-cs1 {
1825                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1826                         };
1827                         spi2_clk: spi2-clk {
1828                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1829                         };
1830                         spi2_cs0: spi2-cs0 {
1831                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1832                         };
1833                         spi2_rx: spi2-rx {
1834                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1835                         };
1836                         spi2_tx: spi2-tx {
1837                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839                 };
1840
1841                 uart0 {
1842                         uart0_xfer: uart0-xfer {
1843                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1844                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1845                         };
1846
1847                         uart0_cts: uart0-cts {
1848                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1849                         };
1850
1851                         uart0_rts: uart0-rts {
1852                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1853                         };
1854                 };
1855
1856                 uart1 {
1857                         uart1_xfer: uart1-xfer {
1858                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1859                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1860                         };
1861
1862                         uart1_cts: uart1-cts {
1863                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1864                         };
1865
1866                         uart1_rts: uart1-rts {
1867                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1868                         };
1869                 };
1870
1871                 uart2 {
1872                         uart2_xfer: uart2-xfer {
1873                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1874                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1875                         };
1876                         /* no rts / cts for uart2 */
1877                 };
1878
1879                 uart3 {
1880                         uart3_xfer: uart3-xfer {
1881                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1882                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1883                         };
1884
1885                         uart3_cts: uart3-cts {
1886                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1887                         };
1888
1889                         uart3_rts: uart3-rts {
1890                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1891                         };
1892                 };
1893
1894                 uart4 {
1895                         uart4_xfer: uart4-xfer {
1896                                 rockchip,pins = <5 15 3 &pcfg_pull_up>,
1897                                                 <5 14 3 &pcfg_pull_none>;
1898                         };
1899
1900                         uart4_cts: uart4-cts {
1901                                 rockchip,pins = <5 12 3 &pcfg_pull_up>;
1902                         };
1903
1904                         uart4_rts: uart4-rts {
1905                                 rockchip,pins = <5 13 3 &pcfg_pull_none>;
1906                         };
1907                 };
1908
1909                 tsadc {
1910                         otp_gpio: otp-gpio {
1911                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1912                         };
1913
1914                         otp_out: otp-out {
1915                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1916                         };
1917                 };
1918
1919                 pwm0 {
1920                         pwm0_pin: pwm0-pin {
1921                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1922                         };
1923                 };
1924
1925                 pwm1 {
1926                         pwm1_pin: pwm1-pin {
1927                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1928                         };
1929                 };
1930
1931                 pwm2 {
1932                         pwm2_pin: pwm2-pin {
1933                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1934                         };
1935                 };
1936
1937                 pwm3 {
1938                         pwm3_pin: pwm3-pin {
1939                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1940                         };
1941                 };
1942
1943                 gmac {
1944                         rgmii_pins: rgmii-pins {
1945                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1946                                                 <3 31 3 &pcfg_pull_none>,
1947                                                 <3 26 3 &pcfg_pull_none>,
1948                                                 <3 27 3 &pcfg_pull_none>,
1949                                                 <3 28 3 &pcfg_pull_none_12ma>,
1950                                                 <3 29 3 &pcfg_pull_none_12ma>,
1951                                                 <3 24 3 &pcfg_pull_none_12ma>,
1952                                                 <3 25 3 &pcfg_pull_none_12ma>,
1953                                                 <4 0 3 &pcfg_pull_none>,
1954                                                 <4 5 3 &pcfg_pull_none>,
1955                                                 <4 6 3 &pcfg_pull_none>,
1956                                                 <4 9 3 &pcfg_pull_none_12ma>,
1957                                                 <4 4 3 &pcfg_pull_none_12ma>,
1958                                                 <4 1 3 &pcfg_pull_none>,
1959                                                 <4 3 3 &pcfg_pull_none>;
1960                         };
1961
1962                         rmii_pins: rmii-pins {
1963                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1964                                                 <3 31 3 &pcfg_pull_none>,
1965                                                 <3 28 3 &pcfg_pull_none>,
1966                                                 <3 29 3 &pcfg_pull_none>,
1967                                                 <4 0 3 &pcfg_pull_none>,
1968                                                 <4 5 3 &pcfg_pull_none>,
1969                                                 <4 4 3 &pcfg_pull_none>,
1970                                                 <4 1 3 &pcfg_pull_none>,
1971                                                 <4 2 3 &pcfg_pull_none>,
1972                                                 <4 3 3 &pcfg_pull_none>;
1973                         };
1974                 };
1975
1976                 spdif {
1977                         spdif_tx: spdif-tx {
1978                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1979                         };
1980                 };
1981         };
1982 };