arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 mshc0 = &emmc;
  65                 mshc1 = &sdmmc;
  66                 mshc2 = &sdio0;
  67                 mshc3 = &sdio1;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76         };
  77
  78         arm-pmu {
  79                 compatible = "arm,cortex-a12-pmu";
  80                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  84                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  85         };
  86
  87         cpus {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 enable-method = "rockchip,rk3066-smp";
  91                 rockchip,pmu = <&pmu>;
  92
  93                 cpu0: cpu@500 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a12";
  96                         reg = <0x500>;
  97                         resets = <&cru SRST_CORE0>;
  98                         operating-points = <
  99                                 /* KHz    uV */
 100                                 1608000 1350000
 101                                 1512000 1300000
 102                                 1416000 1200000
 103                                 1200000 1100000
 104                                 1008000 1050000
 105                                  816000 1000000
 106                                  696000  950000
 107                                  600000  900000
 108                                  408000  900000
 109                                  312000  900000
 110                                  216000  900000
 111                                  126000  900000
 112                         >;
 113                         #cooling-cells = <2>; /* min followed by max */
 114                         clock-latency = <40000>;
 115                         clocks = <&cru ARMCLK>;
 116                 };
 117                 cpu1: cpu@501 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a12";
 120                         reg = <0x501>;
 121                         resets = <&cru SRST_CORE1>;
 122                 };
 123                 cpu2: cpu@502 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a12";
 126                         reg = <0x502>;
 127                         resets = <&cru SRST_CORE2>;
 128                 };
 129                 cpu3: cpu@503 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a12";
 132                         reg = <0x503>;
 133                         resets = <&cru SRST_CORE3>;
 134                 };
 135         };
 136
 137         amba {
 138                 compatible = "simple-bus";
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges;
 142
 143                 dmac_peri: dma-controller@ff250000 {
 144                         compatible = "arm,pl330", "arm,primecell";
 145                         reg = <0xff250000 0x4000>;
 146                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 148                         #dma-cells = <1>;
 149                         arm,pl330-broken-no-flushp;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         clocks = <&cru ACLK_DMAC1>;
 162                         clock-names = "apb_pclk";
 163                         status = "disabled";
 164                 };
 165
 166                 dmac_bus_s: dma-controller@ffb20000 {
 167                         compatible = "arm,pl330", "arm,primecell";
 168                         reg = <0xffb20000 0x4000>;
 169                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 171                         #dma-cells = <1>;
 172                         arm,pl330-broken-no-flushp;
 173                         clocks = <&cru ACLK_DMAC1>;
 174                         clock-names = "apb_pclk";
 175                 };
 176         };
 177
 178         reserved-memory {
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 ranges;
 182
 183                 /*
 184                  * The rk3288 cannot use the memory area above 0xfe000000
 185                  * for dma operations for some reason. While there is
 186                  * probably a better solution available somewhere, we
 187                  * haven't found it yet and while devices with 2GB of ram
 188                  * are not affected, this issue prevents 4GB from booting.
 189                  * So to make these devices at least bootable, block
 190                  * this area for the time being until the real solution
 191                  * is found.
 192                  */
 193                 dma-unusable@fe000000 {
 194                         reg = <0xfe000000 0x1000000>;
 195                 };
 196         };
 197
 198         xin24m: oscillator {
 199                 compatible = "fixed-clock";
 200                 clock-frequency = <24000000>;
 201                 clock-output-names = "xin24m";
 202                 #clock-cells = <0>;
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 arm,cpu-registers-not-fw-configured;
 208                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 210                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 212                 clock-frequency = <24000000>;
 213         };
 214
 215         timer: timer@ff810000 {
 216                 compatible = "rockchip,rk3288-timer";
 217                 reg = <0xff810000 0x20>;
 218                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 220                 clock-names = "timer", "pclk";
 221         };
 222
 223         display-subsystem {
 224                 compatible = "rockchip,display-subsystem";
 225                 ports = <&vopl_out>, <&vopb_out>;
 226         };
 227
 228         sdmmc: dwmmc@ff0c0000 {
 229                 compatible = "rockchip,rk3288-dw-mshc";
 230                 clock-freq-min-max = <400000 150000000>;
 231                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 232                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 233                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 234                 fifo-depth = <0x100>;
 235                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 236                 reg = <0xff0c0000 0x4000>;
 237                 status = "disabled";
 238         };
 239
 240         sdio0: dwmmc@ff0d0000 {
 241                 compatible = "rockchip,rk3288-dw-mshc";
 242                 clock-freq-min-max = <400000 150000000>;
 243                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 244                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 245                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 246                 fifo-depth = <0x100>;
 247                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 248                 reg = <0xff0d0000 0x4000>;
 249                 status = "disabled";
 250         };
 251
 252         sdio1: dwmmc@ff0e0000 {
 253                 compatible = "rockchip,rk3288-dw-mshc";
 254                 clock-freq-min-max = <400000 150000000>;
 255                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 256                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 257                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 258                 fifo-depth = <0x100>;
 259                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 260                 reg = <0xff0e0000 0x4000>;
 261                 status = "disabled";
 262         };
 263
 264         emmc: dwmmc@ff0f0000 {
 265                 compatible = "rockchip,rk3288-dw-mshc";
 266                 clock-freq-min-max = <400000 150000000>;
 267                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 268                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 272                 reg = <0xff0f0000 0x4000>;
 273                 status = "disabled";
 274         };
 275
 276         saradc: saradc@ff100000 {
 277                 compatible = "rockchip,saradc";
 278                 reg = <0xff100000 0x100>;
 279                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 280                 #io-channel-cells = <1>;
 281                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 282                 clock-names = "saradc", "apb_pclk";
 283                 resets = <&cru SRST_SARADC>;
 284                 reset-names = "saradc-apb";
 285                 status = "disabled";
 286         };
 287
 288         spi0: spi@ff110000 {
 289                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 290                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 291                 clock-names = "spiclk", "apb_pclk";
 292                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 293                 dma-names = "tx", "rx";
 294                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 295                 pinctrl-names = "default";
 296                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 297                 reg = <0xff110000 0x1000>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 status = "disabled";
 301         };
 302
 303         spi1: spi@ff120000 {
 304                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 305                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 306                 clock-names = "spiclk", "apb_pclk";
 307                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 308                 dma-names = "tx", "rx";
 309                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 310                 pinctrl-names = "default";
 311                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 312                 reg = <0xff120000 0x1000>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 status = "disabled";
 316         };
 317
 318         spi2: spi@ff130000 {
 319                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 320                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 321                 clock-names = "spiclk", "apb_pclk";
 322                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 323                 dma-names = "tx", "rx";
 324                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 327                 reg = <0xff130000 0x1000>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         i2c1: i2c@ff140000 {
 334                 compatible = "rockchip,rk3288-i2c";
 335                 reg = <0xff140000 0x1000>;
 336                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 clock-names = "i2c";
 340                 clocks = <&cru PCLK_I2C1>;
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&i2c1_xfer>;
 343                 status = "disabled";
 344         };
 345
 346         i2c3: i2c@ff150000 {
 347                 compatible = "rockchip,rk3288-i2c";
 348                 reg = <0xff150000 0x1000>;
 349                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 clock-names = "i2c";
 353                 clocks = <&cru PCLK_I2C3>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&i2c3_xfer>;
 356                 status = "disabled";
 357         };
 358
 359         i2c4: i2c@ff160000 {
 360                 compatible = "rockchip,rk3288-i2c";
 361                 reg = <0xff160000 0x1000>;
 362                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 363                 #address-cells = <1>;
 364                 #size-cells = <0>;
 365                 clock-names = "i2c";
 366                 clocks = <&cru PCLK_I2C4>;
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&i2c4_xfer>;
 369                 status = "disabled";
 370         };
 371
 372         i2c5: i2c@ff170000 {
 373                 compatible = "rockchip,rk3288-i2c";
 374                 reg = <0xff170000 0x1000>;
 375                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 clock-names = "i2c";
 379                 clocks = <&cru PCLK_I2C5>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&i2c5_xfer>;
 382                 status = "disabled";
 383         };
 384
 385         uart0: serial@ff180000 {
 386                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 387                 reg = <0xff180000 0x100>;
 388                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 389                 reg-shift = <2>;
 390                 reg-io-width = <4>;
 391                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 392                 clock-names = "baudclk", "apb_pclk";
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart0_xfer>;
 395                 status = "disabled";
 396         };
 397
 398         uart1: serial@ff190000 {
 399                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 400                 reg = <0xff190000 0x100>;
 401                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 402                 reg-shift = <2>;
 403                 reg-io-width = <4>;
 404                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 405                 clock-names = "baudclk", "apb_pclk";
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&uart1_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         uart2: serial@ff690000 {
 412                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 413                 reg = <0xff690000 0x100>;
 414                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 415                 reg-shift = <2>;
 416                 reg-io-width = <4>;
 417                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 418                 clock-names = "baudclk", "apb_pclk";
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&uart2_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         uart3: serial@ff1b0000 {
 425                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 426                 reg = <0xff1b0000 0x100>;
 427                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 428                 reg-shift = <2>;
 429                 reg-io-width = <4>;
 430                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 431                 clock-names = "baudclk", "apb_pclk";
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&uart3_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         uart4: serial@ff1c0000 {
 438                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 439                 reg = <0xff1c0000 0x100>;
 440                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 441                 reg-shift = <2>;
 442                 reg-io-width = <4>;
 443                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 444                 clock-names = "baudclk", "apb_pclk";
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&uart4_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         thermal-zones {
 451                 reserve_thermal: reserve_thermal {
 452                         polling-delay-passive = <1000>; /* milliseconds */
 453                         polling-delay = <5000>; /* milliseconds */
 454
 455                         thermal-sensors = <&tsadc 0>;
 456                 };
 457
 458                 cpu_thermal: cpu_thermal {
 459                         polling-delay-passive = <100>; /* milliseconds */
 460                         polling-delay = <5000>; /* milliseconds */
 461
 462                         thermal-sensors = <&tsadc 1>;
 463
 464                         trips {
 465                                 cpu_alert0: cpu_alert0 {
 466                                         temperature = <70000>; /* millicelsius */
 467                                         hysteresis = <2000>; /* millicelsius */
 468                                         type = "passive";
 469                                 };
 470                                 cpu_alert1: cpu_alert1 {
 471                                         temperature = <75000>; /* millicelsius */
 472                                         hysteresis = <2000>; /* millicelsius */
 473                                         type = "passive";
 474                                 };
 475                                 cpu_crit: cpu_crit {
 476                                         temperature = <90000>; /* millicelsius */
 477                                         hysteresis = <2000>; /* millicelsius */
 478                                         type = "critical";
 479                                 };
 480                         };
 481
 482                         cooling-maps {
 483                                 map0 {
 484                                         trip = <&cpu_alert0>;
 485                                         cooling-device =
 486                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 487                                 };
 488                                 map1 {
 489                                         trip = <&cpu_alert1>;
 490                                         cooling-device =
 491                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 492                                 };
 493                         };
 494                 };
 495
 496                 gpu_thermal: gpu_thermal {
 497                         polling-delay-passive = <100>; /* milliseconds */
 498                         polling-delay = <5000>; /* milliseconds */
 499
 500                         thermal-sensors = <&tsadc 2>;
 501
 502                         trips {
 503                                 gpu_alert0: gpu_alert0 {
 504                                         temperature = <70000>; /* millicelsius */
 505                                         hysteresis = <2000>; /* millicelsius */
 506                                         type = "passive";
 507                                 };
 508                                 gpu_crit: gpu_crit {
 509                                         temperature = <90000>; /* millicelsius */
 510                                         hysteresis = <2000>; /* millicelsius */
 511                                         type = "critical";
 512                                 };
 513                         };
 514
 515                         cooling-maps {
 516                                 map0 {
 517                                         trip = <&gpu_alert0>;
 518                                         cooling-device =
 519                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 520                                 };
 521                         };
 522                 };
 523         };
 524
 525         tsadc: tsadc@ff280000 {
 526                 compatible = "rockchip,rk3288-tsadc";
 527                 reg = <0xff280000 0x100>;
 528                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 529                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 530                 clock-names = "tsadc", "apb_pclk";
 531                 resets = <&cru SRST_TSADC>;
 532                 reset-names = "tsadc-apb";
 533                 pinctrl-names = "init", "default", "sleep";
 534                 pinctrl-0 = <&otp_gpio>;
 535                 pinctrl-1 = <&otp_out>;
 536                 pinctrl-2 = <&otp_gpio>;
 537                 #thermal-sensor-cells = <1>;
 538                 rockchip,hw-tshut-temp = <95000>;
 539                 status = "disabled";
 540         };
 541
 542         gmac: ethernet@ff290000 {
 543                 compatible = "rockchip,rk3288-gmac";
 544                 reg = <0xff290000 0x10000>;
 545                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 546                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 547                 interrupt-names = "macirq", "eth_wake_irq";
 548                 rockchip,grf = <&grf>;
 549                 clocks = <&cru SCLK_MAC>,
 550                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 551                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 552                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 553                 clock-names = "stmmaceth",
 554                         "mac_clk_rx", "mac_clk_tx",
 555                         "clk_mac_ref", "clk_mac_refout",
 556                         "aclk_mac", "pclk_mac";
 557                 resets = <&cru SRST_MAC>;
 558                 reset-names = "stmmaceth";
 559                 status = "disabled";
 560         };
 561
 562         usb_host0_ehci: usb@ff500000 {
 563                 compatible = "generic-ehci";
 564                 reg = <0xff500000 0x100>;
 565                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 566                 clocks = <&cru HCLK_USBHOST0>;
 567                 clock-names = "usbhost";
 568                 phys = <&usbphy1>;
 569                 phy-names = "usb";
 570                 status = "disabled";
 571         };
 572
 573         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 574
 575         usb_host1: usb@ff540000 {
 576                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 577                                 "snps,dwc2";
 578                 reg = <0xff540000 0x40000>;
 579                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 580                 clocks = <&cru HCLK_USBHOST1>;
 581                 clock-names = "otg";
 582                 dr_mode = "host";
 583                 phys = <&usbphy2>;
 584                 phy-names = "usb2-phy";
 585                 status = "disabled";
 586         };
 587
 588         usb_otg: usb@ff580000 {
 589                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 590                                 "snps,dwc2";
 591                 reg = <0xff580000 0x40000>;
 592                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&cru HCLK_OTG0>;
 594                 clock-names = "otg";
 595                 dr_mode = "otg";
 596                 g-np-tx-fifo-size = <16>;
 597                 g-rx-fifo-size = <275>;
 598                 g-tx-fifo-size = <256 128 128 64 64 32>;
 599                 g-use-dma;
 600                 phys = <&usbphy0>;
 601                 phy-names = "usb2-phy";
 602                 status = "disabled";
 603         };
 604
 605         usb_hsic: usb@ff5c0000 {
 606                 compatible = "generic-ehci";
 607                 reg = <0xff5c0000 0x100>;
 608                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&cru HCLK_HSIC>;
 610                 clock-names = "usbhost";
 611                 status = "disabled";
 612         };
 613
 614         i2c0: i2c@ff650000 {
 615                 compatible = "rockchip,rk3288-i2c";
 616                 reg = <0xff650000 0x1000>;
 617                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 clock-names = "i2c";
 621                 clocks = <&cru PCLK_I2C0>;
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&i2c0_xfer>;
 624                 status = "disabled";
 625         };
 626
 627         i2c2: i2c@ff660000 {
 628                 compatible = "rockchip,rk3288-i2c";
 629                 reg = <0xff660000 0x1000>;
 630                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 clock-names = "i2c";
 634                 clocks = <&cru PCLK_I2C2>;
 635                 pinctrl-names = "default";
 636                 pinctrl-0 = <&i2c2_xfer>;
 637                 status = "disabled";
 638         };
 639
 640         pwm0: pwm@ff680000 {
 641                 compatible = "rockchip,rk3288-pwm";
 642                 reg = <0xff680000 0x10>;
 643                 #pwm-cells = <3>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&pwm0_pin>;
 646                 clocks = <&cru PCLK_PWM>;
 647                 clock-names = "pwm";
 648                 status = "disabled";
 649         };
 650
 651         pwm1: pwm@ff680010 {
 652                 compatible = "rockchip,rk3288-pwm";
 653                 reg = <0xff680010 0x10>;
 654                 #pwm-cells = <3>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&pwm1_pin>;
 657                 clocks = <&cru PCLK_PWM>;
 658                 clock-names = "pwm";
 659                 status = "disabled";
 660         };
 661
 662         pwm2: pwm@ff680020 {
 663                 compatible = "rockchip,rk3288-pwm";
 664                 reg = <0xff680020 0x10>;
 665                 #pwm-cells = <3>;
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&pwm2_pin>;
 668                 clocks = <&cru PCLK_PWM>;
 669                 clock-names = "pwm";
 670                 status = "disabled";
 671         };
 672
 673         pwm3: pwm@ff680030 {
 674                 compatible = "rockchip,rk3288-pwm";
 675                 reg = <0xff680030 0x10>;
 676                 #pwm-cells = <2>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&pwm3_pin>;
 679                 clocks = <&cru PCLK_PWM>;
 680                 clock-names = "pwm";
 681                 status = "disabled";
 682         };
 683
 684         bus_intmem@ff700000 {
 685                 compatible = "mmio-sram";
 686                 reg = <0xff700000 0x18000>;
 687                 #address-cells = <1>;
 688                 #size-cells = <1>;
 689                 ranges = <0 0xff700000 0x18000>;
 690                 smp-sram@0 {
 691                         compatible = "rockchip,rk3066-smp-sram";
 692                         reg = <0x00 0x10>;
 693                 };
 694         };
 695
 696         sram@ff720000 {
 697                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 698                 reg = <0xff720000 0x1000>;
 699         };
 700
 701         pmu: power-management@ff730000 {
 702                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 703                 reg = <0xff730000 0x100>;
 704
 705                 power: power-controller {
 706                         compatible = "rockchip,rk3288-power-controller";
 707                         #power-domain-cells = <1>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710
 711                         assigned-clocks = <&cru SCLK_EDP_24M>;
 712                         assigned-clock-parents = <&xin24m>;
 713
 714                         /*
 715                          * Note: Although SCLK_* are the working clocks
 716                          * of device without including on the NOC, needed for
 717                          * synchronous reset.
 718                          *
 719                          * The clocks on the which NOC:
 720                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 721                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 722                          * ACLK_RGA is on ACLK_RGA_NIU.
 723                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 724                          *
 725                          * Which clock are device clocks:
 726                          *      clocks          devices
 727                          *      *_IEP           IEP:Image Enhancement Processor
 728                          *      *_ISP           ISP:Image Signal Processing
 729                          *      *_VIP           VIP:Video Input Processor
 730                          *      *_VOP*          VOP:Visual Output Processor
 731                          *      *_RGA           RGA
 732                          *      *_EDP*          EDP
 733                          *      *_LVDS_*        LVDS
 734                          *      *_HDMI          HDMI
 735                          *      *_MIPI_*        MIPI
 736                          */
 737                         pd_vio@RK3288_PD_VIO {
 738                                 reg = <RK3288_PD_VIO>;
 739                                 clocks = <&cru ACLK_IEP>,
 740                                          <&cru ACLK_ISP>,
 741                                          <&cru ACLK_RGA>,
 742                                          <&cru ACLK_VIP>,
 743                                          <&cru ACLK_VOP0>,
 744                                          <&cru ACLK_VOP1>,
 745                                          <&cru DCLK_VOP0>,
 746                                          <&cru DCLK_VOP1>,
 747                                          <&cru HCLK_IEP>,
 748                                          <&cru HCLK_ISP>,
 749                                          <&cru HCLK_RGA>,
 750                                          <&cru HCLK_VIP>,
 751                                          <&cru HCLK_VOP0>,
 752                                          <&cru HCLK_VOP1>,
 753                                          <&cru PCLK_EDP_CTRL>,
 754                                          <&cru PCLK_HDMI_CTRL>,
 755                                          <&cru PCLK_LVDS_PHY>,
 756                                          <&cru PCLK_MIPI_CSI>,
 757                                          <&cru PCLK_MIPI_DSI0>,
 758                                          <&cru PCLK_MIPI_DSI1>,
 759                                          <&cru SCLK_EDP_24M>,
 760                                          <&cru SCLK_EDP>,
 761                                          <&cru SCLK_ISP_JPE>,
 762                                          <&cru SCLK_ISP>,
 763                                          <&cru SCLK_RGA>;
 764                         };
 765
 766                         /*
 767                          * Note: The following 3 are HEVC(H.265) clocks,
 768                          * and on the ACLK_HEVC_NIU (NOC).
 769                          */
 770                         pd_hevc@RK3288_PD_HEVC {
 771                                 reg = <RK3288_PD_HEVC>;
 772                                 clocks = <&cru ACLK_HEVC>,
 773                                          <&cru SCLK_HEVC_CABAC>,
 774                                          <&cru SCLK_HEVC_CORE>;
 775                         };
 776
 777                         /*
 778                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 779                          * (video endecoder & decoder) clocks that on the
 780                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 781                          */
 782                         pd_video@RK3288_PD_VIDEO {
 783                                 reg = <RK3288_PD_VIDEO>;
 784                                 clocks = <&cru ACLK_VCODEC>,
 785                                          <&cru HCLK_VCODEC>;
 786                         };
 787
 788                         /*
 789                          * Note: ACLK_GPU is the GPU clock,
 790                          * and on the ACLK_GPU_NIU (NOC).
 791                          */
 792                         pd_gpu@RK3288_PD_GPU {
 793                                 reg = <RK3288_PD_GPU>;
 794                                 clocks = <&cru ACLK_GPU>;
 795                         };
 796                 };
 797
 798                 reboot-mode {
 799                         compatible = "syscon-reboot-mode";
 800                         offset = <0x94>;
 801                         mode-normal = <BOOT_NORMAL>;
 802                         mode-recovery = <BOOT_RECOVERY>;
 803                         mode-bootloader = <BOOT_FASTBOOT>;
 804                         mode-loader = <BOOT_BL_DOWNLOAD>;
 805                 };
 806         };
 807
 808         sgrf: syscon@ff740000 {
 809                 compatible = "rockchip,rk3288-sgrf", "syscon";
 810                 reg = <0xff740000 0x1000>;
 811         };
 812
 813         cru: clock-controller@ff760000 {
 814                 compatible = "rockchip,rk3288-cru";
 815                 reg = <0xff760000 0x1000>;
 816                 rockchip,grf = <&grf>;
 817                 #clock-cells = <1>;
 818                 #reset-cells = <1>;
 819                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 820                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 821                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 822                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 823                                   <&cru PCLK_PERI>;
 824                 assigned-clock-rates = <594000000>, <400000000>,
 825                                        <500000000>, <300000000>,
 826                                        <150000000>, <75000000>,
 827                                        <300000000>, <150000000>,
 828                                        <75000000>;
 829         };
 830
 831         grf: syscon@ff770000 {
 832                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 833                 reg = <0xff770000 0x1000>;
 834
 835                 edp_phy: edp-phy {
 836                         compatible = "rockchip,rk3288-dp-phy";
 837                         clocks = <&cru SCLK_EDP_24M>;
 838                         clock-names = "24m";
 839                         #phy-cells = <0>;
 840                         status = "disabled";
 841                 };
 842
 843                 io_domains: io-domains {
 844                         compatible = "rockchip,rk3288-io-voltage-domain";
 845                         status = "disabled";
 846                 };
 847
 848                 usbphy: usbphy {
 849                         compatible = "rockchip,rk3288-usb-phy";
 850                         #address-cells = <1>;
 851                         #size-cells = <0>;
 852                         status = "disabled";
 853
 854                         usbphy0: usb-phy@320 {
 855                                 #phy-cells = <0>;
 856                                 reg = <0x320>;
 857                                 clocks = <&cru SCLK_OTGPHY0>;
 858                                 clock-names = "phyclk";
 859                                 #clock-cells = <0>;
 860                         };
 861
 862                         usbphy1: usb-phy@334 {
 863                                 #phy-cells = <0>;
 864                                 reg = <0x334>;
 865                                 clocks = <&cru SCLK_OTGPHY1>;
 866                                 clock-names = "phyclk";
 867                                 #clock-cells = <0>;
 868                         };
 869
 870                         usbphy2: usb-phy@348 {
 871                                 #phy-cells = <0>;
 872                                 reg = <0x348>;
 873                                 clocks = <&cru SCLK_OTGPHY2>;
 874                                 clock-names = "phyclk";
 875                                 #clock-cells = <0>;
 876                         };
 877                 };
 878         };
 879
 880         wdt: watchdog@ff800000 {
 881                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 882                 reg = <0xff800000 0x100>;
 883                 clocks = <&cru PCLK_WDT>;
 884                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 885                 status = "disabled";
 886         };
 887
 888         spdif: sound@ff88b0000 {
 889                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 890                 reg = <0xff8b0000 0x10000>;
 891                 #sound-dai-cells = <0>;
 892                 clock-names = "hclk", "mclk";
 893                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 894                 dmas = <&dmac_bus_s 3>;
 895                 dma-names = "tx";
 896                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 897                 pinctrl-names = "default";
 898                 pinctrl-0 = <&spdif_tx>;
 899                 rockchip,grf = <&grf>;
 900                 status = "disabled";
 901         };
 902
 903         i2s: i2s@ff890000 {
 904                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 905                 reg = <0xff890000 0x10000>;
 906                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 907                 #address-cells = <1>;
 908                 #size-cells = <0>;
 909                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 910                 dma-names = "tx", "rx";
 911                 clock-names = "i2s_hclk", "i2s_clk";
 912                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 913                 pinctrl-names = "default";
 914                 pinctrl-0 = <&i2s0_bus>;
 915                 rockchip,playback-channels = <8>;
 916                 rockchip,capture-channels = <2>;
 917                 status = "disabled";
 918         };
 919
 920         crypto: cypto-controller@ff8a0000 {
 921                 compatible = "rockchip,rk3288-crypto";
 922                 reg = <0xff8a0000 0x4000>;
 923                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 924                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 925                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 926                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 927                 resets = <&cru SRST_CRYPTO>;
 928                 reset-names = "crypto-rst";
 929                 status = "okay";
 930         };
 931
 932         vopb: vop@ff930000 {
 933                 compatible = "rockchip,rk3288-vop";
 934                 reg = <0xff930000 0x19c>;
 935                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 936                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 937                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 938                 power-domains = <&power RK3288_PD_VIO>;
 939                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 940                 reset-names = "axi", "ahb", "dclk";
 941                 iommus = <&vopb_mmu>;
 942                 status = "disabled";
 943
 944                 vopb_out: port {
 945                         #address-cells = <1>;
 946                         #size-cells = <0>;
 947
 948                         vopb_out_hdmi: endpoint@0 {
 949                                 reg = <0>;
 950                                 remote-endpoint = <&hdmi_in_vopb>;
 951                         };
 952
 953                         vopb_out_edp: endpoint@1 {
 954                                 reg = <1>;
 955                                 remote-endpoint = <&edp_in_vopb>;
 956                         };
 957
 958                         vopb_out_mipi: endpoint@2 {
 959                                 reg = <2>;
 960                                 remote-endpoint = <&mipi_in_vopb>;
 961                         };
 962                 };
 963         };
 964
 965         vopb_mmu: iommu@ff930300 {
 966                 compatible = "rockchip,iommu";
 967                 reg = <0xff930300 0x100>;
 968                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 969                 interrupt-names = "vopb_mmu";
 970                 power-domains = <&power RK3288_PD_VIO>;
 971                 #iommu-cells = <0>;
 972                 status = "disabled";
 973         };
 974
 975         vopl: vop@ff940000 {
 976                 compatible = "rockchip,rk3288-vop";
 977                 reg = <0xff940000 0x19c>;
 978                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 979                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 980                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 981                 power-domains = <&power RK3288_PD_VIO>;
 982                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 983                 reset-names = "axi", "ahb", "dclk";
 984                 iommus = <&vopl_mmu>;
 985                 status = "disabled";
 986
 987                 vopl_out: port {
 988                         #address-cells = <1>;
 989                         #size-cells = <0>;
 990
 991                         vopl_out_hdmi: endpoint@0 {
 992                                 reg = <0>;
 993                                 remote-endpoint = <&hdmi_in_vopl>;
 994                         };
 995
 996                         vopl_out_edp: endpoint@1 {
 997                                 reg = <1>;
 998                                 remote-endpoint = <&edp_in_vopl>;
 999                         };
1000
1001                         vopl_out_mipi: endpoint@2 {
1002                                 reg = <2>;
1003                                 remote-endpoint = <&mipi_in_vopl>;
1004                         };
1005                 };
1006         };
1007
1008         vopl_mmu: iommu@ff940300 {
1009                 compatible = "rockchip,iommu";
1010                 reg = <0xff940300 0x100>;
1011                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1012                 interrupt-names = "vopl_mmu";
1013                 power-domains = <&power RK3288_PD_VIO>;
1014                 #iommu-cells = <0>;
1015                 status = "disabled";
1016         };
1017
1018         mipi_dsi: mipi@ff960000 {
1019                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1020                 reg = <0xff960000 0x4000>;
1021                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1022                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1023                 clock-names = "ref", "pclk";
1024                 power-domains = <&power RK3288_PD_VIO>;
1025                 rockchip,grf = <&grf>;
1026                 #address-cells = <1>;
1027                 #size-cells = <0>;
1028                 status = "disabled";
1029
1030                 ports {
1031                         mipi_in: port {
1032                                 #address-cells = <1>;
1033                                 #size-cells = <0>;
1034                                 mipi_in_vopb: endpoint@0 {
1035                                         reg = <0>;
1036                                         remote-endpoint = <&vopb_out_mipi>;
1037                                 };
1038                                 mipi_in_vopl: endpoint@1 {
1039                                         reg = <1>;
1040                                         remote-endpoint = <&vopl_out_mipi>;
1041                                 };
1042                         };
1043                 };
1044         };
1045
1046         edp: dp@ff970000 {
1047                 compatible = "rockchip,rk3288-dp";
1048                 reg = <0xff970000 0x4000>;
1049                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1050                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1051                 clock-names = "dp", "pclk";
1052                 phys = <&edp_phy>;
1053                 phy-names = "dp";
1054                 resets = <&cru SRST_EDP>;
1055                 reset-names = "dp";
1056                 rockchip,grf = <&grf>;
1057                 status = "disabled";
1058
1059                 ports {
1060                         #address-cells = <1>;
1061                         #size-cells = <0>;
1062                         edp_in: port@0 {
1063                                 reg = <0>;
1064                                 #address-cells = <1>;
1065                                 #size-cells = <0>;
1066                                 edp_in_vopb: endpoint@0 {
1067                                         reg = <0>;
1068                                         remote-endpoint = <&vopb_out_edp>;
1069                                 };
1070                                 edp_in_vopl: endpoint@1 {
1071                                         reg = <1>;
1072                                         remote-endpoint = <&vopl_out_edp>;
1073                                 };
1074                         };
1075                 };
1076         };
1077
1078         hdmi: hdmi@ff980000 {
1079                 compatible = "rockchip,rk3288-dw-hdmi";
1080                 reg = <0xff980000 0x20000>;
1081                 reg-io-width = <4>;
1082                 rockchip,grf = <&grf>;
1083                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1084                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1085                 clock-names = "iahb", "isfr";
1086                 power-domains = <&power RK3288_PD_VIO>;
1087                 status = "disabled";
1088
1089                 ports {
1090                         hdmi_in: port {
1091                                 #address-cells = <1>;
1092                                 #size-cells = <0>;
1093                                 hdmi_in_vopb: endpoint@0 {
1094                                         reg = <0>;
1095                                         remote-endpoint = <&vopb_out_hdmi>;
1096                                 };
1097                                 hdmi_in_vopl: endpoint@1 {
1098                                         reg = <1>;
1099                                         remote-endpoint = <&vopl_out_hdmi>;
1100                                 };
1101                         };
1102                 };
1103         };
1104
1105         gic: interrupt-controller@ffc01000 {
1106                 compatible = "arm,gic-400";
1107                 interrupt-controller;
1108                 #interrupt-cells = <3>;
1109                 #address-cells = <0>;
1110
1111                 reg = <0xffc01000 0x1000>,
1112                       <0xffc02000 0x1000>,
1113                       <0xffc04000 0x2000>,
1114                       <0xffc06000 0x2000>;
1115                 interrupts = <GIC_PPI 9 0xf04>;
1116         };
1117
1118         efuse: efuse@ffb40000 {
1119                 compatible = "rockchip,rockchip-efuse";
1120                 reg = <0xffb40000 0x20>;
1121                 #address-cells = <1>;
1122                 #size-cells = <1>;
1123                 clocks = <&cru PCLK_EFUSE256>;
1124                 clock-names = "pclk_efuse";
1125
1126                 cpu_leakage: cpu_leakage@17 {
1127                         reg = <0x17 0x1>;
1128                 };
1129         };
1130
1131         pinctrl: pinctrl {
1132                 compatible = "rockchip,rk3288-pinctrl";
1133                 rockchip,grf = <&grf>;
1134                 rockchip,pmu = <&pmu>;
1135                 #address-cells = <1>;
1136                 #size-cells = <1>;
1137                 ranges;
1138
1139                 gpio0: gpio0@ff750000 {
1140                         compatible = "rockchip,gpio-bank";
1141                         reg =   <0xff750000 0x100>;
1142                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1143                         clocks = <&cru PCLK_GPIO0>;
1144
1145                         gpio-controller;
1146                         #gpio-cells = <2>;
1147
1148                         interrupt-controller;
1149                         #interrupt-cells = <2>;
1150                 };
1151
1152                 gpio1: gpio1@ff780000 {
1153                         compatible = "rockchip,gpio-bank";
1154                         reg = <0xff780000 0x100>;
1155                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1156                         clocks = <&cru PCLK_GPIO1>;
1157
1158                         gpio-controller;
1159                         #gpio-cells = <2>;
1160
1161                         interrupt-controller;
1162                         #interrupt-cells = <2>;
1163                 };
1164
1165                 gpio2: gpio2@ff790000 {
1166                         compatible = "rockchip,gpio-bank";
1167                         reg = <0xff790000 0x100>;
1168                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1169                         clocks = <&cru PCLK_GPIO2>;
1170
1171                         gpio-controller;
1172                         #gpio-cells = <2>;
1173
1174                         interrupt-controller;
1175                         #interrupt-cells = <2>;
1176                 };
1177
1178                 gpio3: gpio3@ff7a0000 {
1179                         compatible = "rockchip,gpio-bank";
1180                         reg = <0xff7a0000 0x100>;
1181                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1182                         clocks = <&cru PCLK_GPIO3>;
1183
1184                         gpio-controller;
1185                         #gpio-cells = <2>;
1186
1187                         interrupt-controller;
1188                         #interrupt-cells = <2>;
1189                 };
1190
1191                 gpio4: gpio4@ff7b0000 {
1192                         compatible = "rockchip,gpio-bank";
1193                         reg = <0xff7b0000 0x100>;
1194                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1195                         clocks = <&cru PCLK_GPIO4>;
1196
1197                         gpio-controller;
1198                         #gpio-cells = <2>;
1199
1200                         interrupt-controller;
1201                         #interrupt-cells = <2>;
1202                 };
1203
1204                 gpio5: gpio5@ff7c0000 {
1205                         compatible = "rockchip,gpio-bank";
1206                         reg = <0xff7c0000 0x100>;
1207                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1208                         clocks = <&cru PCLK_GPIO5>;
1209
1210                         gpio-controller;
1211                         #gpio-cells = <2>;
1212
1213                         interrupt-controller;
1214                         #interrupt-cells = <2>;
1215                 };
1216
1217                 gpio6: gpio6@ff7d0000 {
1218                         compatible = "rockchip,gpio-bank";
1219                         reg = <0xff7d0000 0x100>;
1220                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1221                         clocks = <&cru PCLK_GPIO6>;
1222
1223                         gpio-controller;
1224                         #gpio-cells = <2>;
1225
1226                         interrupt-controller;
1227                         #interrupt-cells = <2>;
1228                 };
1229
1230                 gpio7: gpio7@ff7e0000 {
1231                         compatible = "rockchip,gpio-bank";
1232                         reg = <0xff7e0000 0x100>;
1233                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1234                         clocks = <&cru PCLK_GPIO7>;
1235
1236                         gpio-controller;
1237                         #gpio-cells = <2>;
1238
1239                         interrupt-controller;
1240                         #interrupt-cells = <2>;
1241                 };
1242
1243                 gpio8: gpio8@ff7f0000 {
1244                         compatible = "rockchip,gpio-bank";
1245                         reg = <0xff7f0000 0x100>;
1246                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1247                         clocks = <&cru PCLK_GPIO8>;
1248
1249                         gpio-controller;
1250                         #gpio-cells = <2>;
1251
1252                         interrupt-controller;
1253                         #interrupt-cells = <2>;
1254                 };
1255
1256                 hdmi {
1257                         hdmi_ddc: hdmi-ddc {
1258                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1259                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1260                         };
1261                 };
1262
1263                 pcfg_pull_up: pcfg-pull-up {
1264                         bias-pull-up;
1265                 };
1266
1267                 pcfg_pull_down: pcfg-pull-down {
1268                         bias-pull-down;
1269                 };
1270
1271                 pcfg_pull_none: pcfg-pull-none {
1272                         bias-disable;
1273                 };
1274
1275                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1276                         bias-disable;
1277                         drive-strength = <12>;
1278                 };
1279
1280                 sleep {
1281                         global_pwroff: global-pwroff {
1282                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1283                         };
1284
1285                         ddrio_pwroff: ddrio-pwroff {
1286                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1287                         };
1288
1289                         ddr0_retention: ddr0-retention {
1290                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1291                         };
1292
1293                         ddr1_retention: ddr1-retention {
1294                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1295                         };
1296                 };
1297
1298                 edp {
1299                         edp_hpd: edp-hpd {
1300                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1301                         };
1302                 };
1303
1304                 i2c0 {
1305                         i2c0_xfer: i2c0-xfer {
1306                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1307                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1308                         };
1309                 };
1310
1311                 i2c1 {
1312                         i2c1_xfer: i2c1-xfer {
1313                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1314                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 i2c2 {
1319                         i2c2_xfer: i2c2-xfer {
1320                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1321                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 i2c3 {
1326                         i2c3_xfer: i2c3-xfer {
1327                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1328                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1329                         };
1330                 };
1331
1332                 i2c4 {
1333                         i2c4_xfer: i2c4-xfer {
1334                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1335                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1336                         };
1337                 };
1338
1339                 i2c5 {
1340                         i2c5_xfer: i2c5-xfer {
1341                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1342                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1343                         };
1344                 };
1345
1346                 i2s0 {
1347                         i2s0_bus: i2s0-bus {
1348                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1349                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1350                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1351                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1352                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1353                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1354                         };
1355                 };
1356
1357                 sdmmc {
1358                         sdmmc_clk: sdmmc-clk {
1359                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1360                         };
1361
1362                         sdmmc_cmd: sdmmc-cmd {
1363                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1364                         };
1365
1366                         sdmmc_cd: sdmmc-cd {
1367                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1368                         };
1369
1370                         sdmmc_bus1: sdmmc-bus1 {
1371                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1372                         };
1373
1374                         sdmmc_bus4: sdmmc-bus4 {
1375                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1376                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1377                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1378                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1379                         };
1380                 };
1381
1382                 sdio0 {
1383                         sdio0_bus1: sdio0-bus1 {
1384                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386
1387                         sdio0_bus4: sdio0-bus4 {
1388                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1389                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1390                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1391                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1392                         };
1393
1394                         sdio0_cmd: sdio0-cmd {
1395                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1396                         };
1397
1398                         sdio0_clk: sdio0-clk {
1399                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1400                         };
1401
1402                         sdio0_cd: sdio0-cd {
1403                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1404                         };
1405
1406                         sdio0_wp: sdio0-wp {
1407                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1408                         };
1409
1410                         sdio0_pwr: sdio0-pwr {
1411                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1412                         };
1413
1414                         sdio0_bkpwr: sdio0-bkpwr {
1415                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1416                         };
1417
1418                         sdio0_int: sdio0-int {
1419                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1420                         };
1421                 };
1422
1423                 sdio1 {
1424                         sdio1_bus1: sdio1-bus1 {
1425                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1426                         };
1427
1428                         sdio1_bus4: sdio1-bus4 {
1429                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1430                                                 <3 25 4 &pcfg_pull_up>,
1431                                                 <3 26 4 &pcfg_pull_up>,
1432                                                 <3 27 4 &pcfg_pull_up>;
1433                         };
1434
1435                         sdio1_cd: sdio1-cd {
1436                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1437                         };
1438
1439                         sdio1_wp: sdio1-wp {
1440                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1441                         };
1442
1443                         sdio1_bkpwr: sdio1-bkpwr {
1444                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1445                         };
1446
1447                         sdio1_int: sdio1-int {
1448                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1449                         };
1450
1451                         sdio1_cmd: sdio1-cmd {
1452                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1453                         };
1454
1455                         sdio1_clk: sdio1-clk {
1456                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1457                         };
1458
1459                         sdio1_pwr: sdio1-pwr {
1460                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1461                         };
1462                 };
1463
1464                 emmc {
1465                         emmc_clk: emmc-clk {
1466                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1467                         };
1468
1469                         emmc_cmd: emmc-cmd {
1470                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1471                         };
1472
1473                         emmc_pwr: emmc-pwr {
1474                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1475                         };
1476
1477                         emmc_bus1: emmc-bus1 {
1478                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1479                         };
1480
1481                         emmc_bus4: emmc-bus4 {
1482                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1483                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1484                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1485                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1486                         };
1487
1488                         emmc_bus8: emmc-bus8 {
1489                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1490                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1491                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1492                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1493                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1494                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1495                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1496                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1497                         };
1498                 };
1499
1500                 spi0 {
1501                         spi0_clk: spi0-clk {
1502                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1503                         };
1504                         spi0_cs0: spi0-cs0 {
1505                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1506                         };
1507                         spi0_tx: spi0-tx {
1508                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1509                         };
1510                         spi0_rx: spi0-rx {
1511                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1512                         };
1513                         spi0_cs1: spi0-cs1 {
1514                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1515                         };
1516                 };
1517                 spi1 {
1518                         spi1_clk: spi1-clk {
1519                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1520                         };
1521                         spi1_cs0: spi1-cs0 {
1522                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1523                         };
1524                         spi1_rx: spi1-rx {
1525                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1526                         };
1527                         spi1_tx: spi1-tx {
1528                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1529                         };
1530                 };
1531
1532                 spi2 {
1533                         spi2_cs1: spi2-cs1 {
1534                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1535                         };
1536                         spi2_clk: spi2-clk {
1537                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1538                         };
1539                         spi2_cs0: spi2-cs0 {
1540                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1541                         };
1542                         spi2_rx: spi2-rx {
1543                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1544                         };
1545                         spi2_tx: spi2-tx {
1546                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1547                         };
1548                 };
1549
1550                 uart0 {
1551                         uart0_xfer: uart0-xfer {
1552                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1553                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1554                         };
1555
1556                         uart0_cts: uart0-cts {
1557                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1558                         };
1559
1560                         uart0_rts: uart0-rts {
1561                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1562                         };
1563                 };
1564
1565                 uart1 {
1566                         uart1_xfer: uart1-xfer {
1567                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1568                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1569                         };
1570
1571                         uart1_cts: uart1-cts {
1572                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         uart1_rts: uart1-rts {
1576                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578                 };
1579
1580                 uart2 {
1581                         uart2_xfer: uart2-xfer {
1582                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1583                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1584                         };
1585                         /* no rts / cts for uart2 */
1586                 };
1587
1588                 uart3 {
1589                         uart3_xfer: uart3-xfer {
1590                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1591                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1592                         };
1593
1594                         uart3_cts: uart3-cts {
1595                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1596                         };
1597
1598                         uart3_rts: uart3-rts {
1599                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1600                         };
1601                 };
1602
1603                 uart4 {
1604                         uart4_xfer: uart4-xfer {
1605                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1606                                                 <5 13 3 &pcfg_pull_none>;
1607                         };
1608
1609                         uart4_cts: uart4-cts {
1610                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1611                         };
1612
1613                         uart4_rts: uart4-rts {
1614                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 tsadc {
1619                         otp_gpio: otp-gpio {
1620                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1621                         };
1622
1623                         otp_out: otp-out {
1624                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1625                         };
1626                 };
1627
1628                 pwm0 {
1629                         pwm0_pin: pwm0-pin {
1630                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1631                         };
1632                 };
1633
1634                 pwm1 {
1635                         pwm1_pin: pwm1-pin {
1636                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1637                         };
1638                 };
1639
1640                 pwm2 {
1641                         pwm2_pin: pwm2-pin {
1642                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1643                         };
1644                 };
1645
1646                 pwm3 {
1647                         pwm3_pin: pwm3-pin {
1648                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1649                         };
1650                 };
1651
1652                 gmac {
1653                         rgmii_pins: rgmii-pins {
1654                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1655                                                 <3 31 3 &pcfg_pull_none>,
1656                                                 <3 26 3 &pcfg_pull_none>,
1657                                                 <3 27 3 &pcfg_pull_none>,
1658                                                 <3 28 3 &pcfg_pull_none_12ma>,
1659                                                 <3 29 3 &pcfg_pull_none_12ma>,
1660                                                 <3 24 3 &pcfg_pull_none_12ma>,
1661                                                 <3 25 3 &pcfg_pull_none_12ma>,
1662                                                 <4 0 3 &pcfg_pull_none>,
1663                                                 <4 5 3 &pcfg_pull_none>,
1664                                                 <4 6 3 &pcfg_pull_none>,
1665                                                 <4 9 3 &pcfg_pull_none_12ma>,
1666                                                 <4 4 3 &pcfg_pull_none_12ma>,
1667                                                 <4 1 3 &pcfg_pull_none>,
1668                                                 <4 3 3 &pcfg_pull_none>;
1669                         };
1670
1671                         rmii_pins: rmii-pins {
1672                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1673                                                 <3 31 3 &pcfg_pull_none>,
1674                                                 <3 28 3 &pcfg_pull_none>,
1675                                                 <3 29 3 &pcfg_pull_none>,
1676                                                 <4 0 3 &pcfg_pull_none>,
1677                                                 <4 5 3 &pcfg_pull_none>,
1678                                                 <4 4 3 &pcfg_pull_none>,
1679                                                 <4 1 3 &pcfg_pull_none>,
1680                                                 <4 2 3 &pcfg_pull_none>,
1681                                                 <4 3 3 &pcfg_pull_none>;
1682                         };
1683                 };
1684
1685                 spdif {
1686                         spdif_tx: spdif-tx {
1687                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1688                         };
1689                 };
1690         };
1691 };