1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Veyron (and derivatives) board device tree source
5 * Copyright 2015 Google, Inc
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288.dtsi"
14 stdout-path = "serial2:115200n8";
18 * The default coreboot on veyron devices ignores memory@0 nodes
19 * and would instead create another memory node.
22 device_type = "memory";
23 reg = <0x0 0x0 0x0 0x80000000>;
26 gpio_keys: gpio-keys {
27 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pwr_key_l>;
33 gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
34 linux,code = <KEY_POWER>;
35 debounce-interval = <100>;
41 compatible = "gpio-restart";
42 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&ap_warm_reset_h>;
48 emmc_pwrseq: emmc-pwrseq {
49 compatible = "mmc-pwrseq-emmc";
50 pinctrl-0 = <&emmc_reset>;
51 pinctrl-names = "default";
52 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
55 sdio_pwrseq: sdio-pwrseq {
56 compatible = "mmc-pwrseq-simple";
57 clocks = <&rk808 RK808_CLKOUT1>;
58 clock-names = "ext_clock";
59 pinctrl-names = "default";
60 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
63 * Depending on the actual card populated GPIO4 D4 and D5
64 * correspond to one of these signals on the module:
67 * - SDIO_RESET_L_WL_REG_ON
68 * - PDN (power down when low)
71 * - BT_I2S_WS_BT_RFDISABLE_L
74 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
75 <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
79 compatible = "regulator-fixed";
80 regulator-name = "vcc_5v";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
87 vcc33_sys: vcc33-sys {
88 compatible = "regulator-fixed";
89 regulator-name = "vcc33_sys";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
96 vcc50_hdmi: vcc50-hdmi {
97 compatible = "regulator-fixed";
98 regulator-name = "vcc50_hdmi";
101 vin-supply = <&vcc_5v>;
104 vdd_logic: vdd-logic {
105 compatible = "pwm-regulator";
106 regulator-name = "vdd_logic";
108 pwms = <&pwm1 0 1994 0>;
109 pwm-supply = <&vcc33_sys>;
111 pwm-dutycycle-range = <0x7b 0>;
112 pwm-dutycycle-unit = <0x94>;
116 regulator-min-microvolt = <950000>;
117 regulator-max-microvolt = <1350000>;
118 regulator-ramp-delay = <4000>;
123 cpu0-supply = <&vdd_cpu>;
126 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
128 /delete-node/ opp-312000000;
131 opp-microvolt = <1250000>;
134 opp-microvolt = <1300000>;
137 opp-hz = /bits/ 64 <1704000000>;
138 opp-microvolt = <1350000>;
141 opp-hz = /bits/ 64 <1800000000>;
142 opp-microvolt = <1400000>;
151 rockchip,default-sample-phase = <158>;
154 mmc-pwrseq = <&emmc_pwrseq>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
161 mali-supply = <&vdd_gpu>;
166 ddc-i2c-bus = <&i2c5>;
173 clock-frequency = <400000>;
174 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
175 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
178 compatible = "rockchip,rk808";
180 clock-output-names = "xin32k", "wifibt_32kin";
181 interrupt-parent = <&gpio0>;
182 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pmic_int_l>;
185 rockchip,system-power-controller;
189 vcc1-supply = <&vcc33_sys>;
190 vcc2-supply = <&vcc33_sys>;
191 vcc3-supply = <&vcc33_sys>;
192 vcc4-supply = <&vcc33_sys>;
193 vcc6-supply = <&vcc_5v>;
194 vcc7-supply = <&vcc33_sys>;
195 vcc8-supply = <&vcc33_sys>;
196 vcc12-supply = <&vcc_18>;
197 vddio-supply = <&vcc33_io>;
201 regulator-name = "vdd_arm";
204 regulator-min-microvolt = <750000>;
205 regulator-max-microvolt = <1450000>;
206 regulator-ramp-delay = <6001>;
207 regulator-state-mem {
208 regulator-off-in-suspend;
213 regulator-name = "vdd_gpu";
216 regulator-min-microvolt = <800000>;
217 regulator-max-microvolt = <1250000>;
218 regulator-ramp-delay = <6001>;
219 regulator-state-mem {
220 regulator-off-in-suspend;
224 vcc135_ddr: DCDC_REG3 {
225 regulator-name = "vcc135_ddr";
228 regulator-state-mem {
229 regulator-on-in-suspend;
234 * vcc_18 has several aliases. (vcc18_flashio and
235 * vcc18_wl). We'll add those aliases here just to
236 * make it easier to follow the schematic. The signals
237 * are actually hooked together and only separated for
238 * power measurement purposes).
240 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
241 regulator-name = "vcc_18";
244 regulator-min-microvolt = <1800000>;
245 regulator-max-microvolt = <1800000>;
246 regulator-state-mem {
247 regulator-on-in-suspend;
248 regulator-suspend-microvolt = <1800000>;
253 * Note that both vcc33_io and vcc33_pmuio are always
254 * powered together. To simplify the logic in the dts
255 * we just refer to vcc33_io every time something is
256 * powered from vcc33_pmuio. In fact, on later boards
257 * (such as danger) they're the same net.
260 regulator-name = "vcc33_io";
263 regulator-min-microvolt = <3300000>;
264 regulator-max-microvolt = <3300000>;
265 regulator-state-mem {
266 regulator-on-in-suspend;
267 regulator-suspend-microvolt = <3300000>;
272 regulator-name = "vdd_10";
275 regulator-min-microvolt = <1000000>;
276 regulator-max-microvolt = <1000000>;
277 regulator-state-mem {
278 regulator-on-in-suspend;
279 regulator-suspend-microvolt = <1000000>;
283 vdd10_lcd_pwren_h: LDO_REG7 {
284 regulator-name = "vdd10_lcd_pwren_h";
287 regulator-min-microvolt = <2500000>;
288 regulator-max-microvolt = <2500000>;
289 regulator-state-mem {
290 regulator-off-in-suspend;
294 vcc33_lcd: SWITCH_REG1 {
295 regulator-name = "vcc33_lcd";
298 regulator-state-mem {
299 regulator-off-in-suspend;
309 clock-frequency = <400000>;
310 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
311 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
314 compatible = "infineon,slb9645tt";
316 powered-while-suspended;
323 /* 100kHz since 4.7k resistors don't rise fast enough */
324 clock-frequency = <100000>;
325 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
326 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
332 clock-frequency = <400000>;
333 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
334 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
340 clock-frequency = <100000>;
341 i2c-scl-falling-time-ns = <300>;
342 i2c-scl-rising-time-ns = <1000>;
348 bb-supply = <&vcc33_io>;
349 dvp-supply = <&vcc_18>;
350 flash0-supply = <&vcc18_flashio>;
351 gpio1830-supply = <&vcc33_io>;
352 gpio30-supply = <&vcc33_io>;
353 lcdc-supply = <&vcc33_lcd>;
354 wifi-supply = <&vcc18_wl>;
367 keep-power-in-suspend;
368 mmc-pwrseq = <&sdio_pwrseq>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
376 vmmc-supply = <&vcc33_sys>;
377 vqmmc-supply = <&vcc18_wl>;
383 rx-sample-delay-ns = <12>;
386 compatible = "jedec,spi-nor";
387 spi-max-frequency = <50000000>;
395 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
396 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
402 /* Pins don't include flow control by default; add that in */
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
422 needs-reset-on-resume;
427 snps,need-phy-for-wake;
433 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
434 assigned-clock-parents = <&usbphy0>;
436 snps,need-phy-for-wake;
452 pinctrl-names = "default", "sleep";
454 /* Common for sleep and wake, but no owners */
460 /* Common for sleep and wake, but no owners */
466 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
468 drive-strength = <8>;
471 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
473 drive-strength = <8>;
476 pcfg_output_high: pcfg-output-high {
480 pcfg_output_low: pcfg-output-low {
485 pwr_key_l: pwr-key-l {
486 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
491 emmc_reset: emmc-reset {
492 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
496 * We run eMMC at max speed; bump up drive strength.
497 * We also have external pulls, so disable the internal ones.
500 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
504 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
507 emmc_bus8: emmc-bus8 {
508 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
509 <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
510 <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
511 <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
512 <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
513 <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
514 <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
515 <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
520 pmic_int_l: pmic-int-l {
521 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
526 ap_warm_reset_h: ap-warm-reset-h {
527 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
532 rec_mode_l: rec-mode-l {
533 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
538 wifi_enable_h: wifienable-h {
539 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
542 /* NOTE: mislabelled on schematic; should be bt_enable_h */
543 bt_enable_l: bt-enable-l {
544 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
548 * We run sdio0 at max speed; bump up drive strength.
549 * We also have external pulls, so disable the internal ones.
551 sdio0_bus4: sdio0-bus4 {
552 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
553 <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
554 <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
555 <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
558 sdio0_cmd: sdio0-cmd {
559 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
562 sdio0_clk: sdio0-clk {
563 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
568 tpm_int_h: tpm-int-h {
569 rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
575 rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;