arch/arm/boot/dts/rk3288-veyron.dtsi

   1 /*
   2  * Google Veyron (and derivatives) board device tree source
   3  *
   4  * Copyright 2015 Google, Inc
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *  Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/rockchip,rk808.h>
  46 #include <dt-bindings/input/input.h>
  47 #include "rk3288.dtsi"
  48
  49 / {
  50         memory@0 {
  51                 device_type = "memory";
  52                 reg = <0x0 0x80000000>;
  53         };
  54
  55         gpio_keys: gpio-keys {
  56                 compatible = "gpio-keys";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pwr_key_l>;
  62                 power {
  63                         label = "Power";
  64                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  65                         linux,code = <KEY_POWER>;
  66                         debounce-interval = <100>;
  67                         wakeup-source;
  68                 };
  69         };
  70
  71         gpio-restart {
  72                 compatible = "gpio-restart";
  73                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&ap_warm_reset_h>;
  76                 priority = <200>;
  77         };
  78
  79         emmc_pwrseq: emmc-pwrseq {
  80                 compatible = "mmc-pwrseq-emmc";
  81                 pinctrl-0 = <&emmc_reset>;
  82                 pinctrl-names = "default";
  83                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  84         };
  85
  86         sdio_pwrseq: sdio-pwrseq {
  87                 compatible = "mmc-pwrseq-simple";
  88                 clocks = <&rk808 RK808_CLKOUT1>;
  89                 clock-names = "ext_clock";
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  92
  93                 /*
  94                  * On the module itself this is one of these (depending
  95                  * on the actual card populated):
  96                  * - SDIO_RESET_L_WL_REG_ON
  97                  * - PDN (power down when low)
  98                  */
  99                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         vcc_5v: vcc-5v {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vcc_5v";
 105                 regulator-always-on;
 106                 regulator-boot-on;
 107                 regulator-min-microvolt = <5000000>;
 108                 regulator-max-microvolt = <5000000>;
 109         };
 110
 111         vcc33_sys: vcc33-sys {
 112                 compatible = "regulator-fixed";
 113                 regulator-name = "vcc33_sys";
 114                 regulator-always-on;
 115                 regulator-boot-on;
 116                 regulator-min-microvolt = <3300000>;
 117                 regulator-max-microvolt = <3300000>;
 118         };
 119
 120         vcc50_hdmi: vcc50-hdmi {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "vcc50_hdmi";
 123                 regulator-always-on;
 124                 regulator-boot-on;
 125                 vin-supply = <&vcc_5v>;
 126         };
 127 };
 128
 129 &cpu0 {
 130         cpu0-supply = <&vdd_cpu>;
 131         operating-points = <
 132                 /* KHz    uV */
 133                 1800000 1400000
 134                 1704000 1350000
 135                 1608000 1300000
 136                 1512000 1250000
 137                 1416000 1200000
 138                 1200000 1100000
 139                 1008000 1050000
 140                  816000 1000000
 141                  696000  950000
 142                  600000  900000
 143                  408000  900000
 144                  216000  900000
 145                  126000  900000
 146         >;
 147 };
 148
 149 &emmc {
 150         status = "okay";
 151
 152         bus-width = <8>;
 153         cap-mmc-highspeed;
 154         rockchip,default-sample-phase = <158>;
 155         disable-wp;
 156         mmc-hs200-1_8v;
 157         mmc-pwrseq = <&emmc_pwrseq>;
 158         non-removable;
 159         num-slots = <1>;
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 162 };
 163
 164 &gpu {
 165         mali-supply = <&vdd_gpu>;
 166         status = "okay";
 167 };
 168
 169 &hdmi {
 170         ddc-i2c-bus = <&i2c5>;
 171         status = "okay";
 172 };
 173
 174 &i2c0 {
 175         status = "okay";
 176
 177         clock-frequency = <400000>;
 178         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 179         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 180
 181         rk808: pmic@1b {
 182                 compatible = "rockchip,rk808";
 183                 reg = <0x1b>;
 184                 clock-output-names = "xin32k", "wifibt_32kin";
 185                 interrupt-parent = <&gpio0>;
 186                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 187                 pinctrl-names = "default";
 188                 pinctrl-0 = <&pmic_int_l>;
 189                 rockchip,system-power-controller;
 190                 wakeup-source;
 191                 #clock-cells = <1>;
 192
 193                 vcc1-supply = <&vcc33_sys>;
 194                 vcc2-supply = <&vcc33_sys>;
 195                 vcc3-supply = <&vcc33_sys>;
 196                 vcc4-supply = <&vcc33_sys>;
 197                 vcc6-supply = <&vcc_5v>;
 198                 vcc7-supply = <&vcc33_sys>;
 199                 vcc8-supply = <&vcc33_sys>;
 200                 vcc12-supply = <&vcc_18>;
 201                 vddio-supply = <&vcc33_io>;
 202
 203                 regulators {
 204                         vdd_cpu: DCDC_REG1 {
 205                                 regulator-name = "vdd_arm";
 206                                 regulator-always-on;
 207                                 regulator-boot-on;
 208                                 regulator-min-microvolt = <750000>;
 209                                 regulator-max-microvolt = <1450000>;
 210                                 regulator-ramp-delay = <6001>;
 211                                 regulator-state-mem {
 212                                         regulator-off-in-suspend;
 213                                 };
 214                         };
 215
 216                         vdd_gpu: DCDC_REG2 {
 217                                 regulator-name = "vdd_gpu";
 218                                 regulator-always-on;
 219                                 regulator-boot-on;
 220                                 regulator-min-microvolt = <800000>;
 221                                 regulator-max-microvolt = <1250000>;
 222                                 regulator-ramp-delay = <6001>;
 223                                 regulator-state-mem {
 224                                         regulator-on-in-suspend;
 225                                         regulator-suspend-microvolt = <1000000>;
 226                                 };
 227                         };
 228
 229                         vcc135_ddr: DCDC_REG3 {
 230                                 regulator-name = "vcc135_ddr";
 231                                 regulator-always-on;
 232                                 regulator-boot-on;
 233                                 regulator-state-mem {
 234                                         regulator-on-in-suspend;
 235                                 };
 236                         };
 237
 238                         /*
 239                          * vcc_18 has several aliases.  (vcc18_flashio and
 240                          * vcc18_wl).  We'll add those aliases here just to
 241                          * make it easier to follow the schematic.  The signals
 242                          * are actually hooked together and only separated for
 243                          * power measurement purposes).
 244                          */
 245                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 246                                 regulator-name = "vcc_18";
 247                                 regulator-always-on;
 248                                 regulator-boot-on;
 249                                 regulator-min-microvolt = <1800000>;
 250                                 regulator-max-microvolt = <1800000>;
 251                                 regulator-state-mem {
 252                                         regulator-on-in-suspend;
 253                                         regulator-suspend-microvolt = <1800000>;
 254                                 };
 255                         };
 256
 257                         /*
 258                          * Note that both vcc33_io and vcc33_pmuio are always
 259                          * powered together. To simplify the logic in the dts
 260                          * we just refer to vcc33_io every time something is
 261                          * powered from vcc33_pmuio. In fact, on later boards
 262                          * (such as danger) they're the same net.
 263                          */
 264                         vcc33_io: LDO_REG1 {
 265                                 regulator-name = "vcc33_io";
 266                                 regulator-always-on;
 267                                 regulator-boot-on;
 268                                 regulator-min-microvolt = <3300000>;
 269                                 regulator-max-microvolt = <3300000>;
 270                                 regulator-state-mem {
 271                                         regulator-on-in-suspend;
 272                                         regulator-suspend-microvolt = <3300000>;
 273                                 };
 274                         };
 275
 276                         vdd_10: LDO_REG3 {
 277                                 regulator-name = "vdd_10";
 278                                 regulator-always-on;
 279                                 regulator-boot-on;
 280                                 regulator-min-microvolt = <1000000>;
 281                                 regulator-max-microvolt = <1000000>;
 282                                 regulator-state-mem {
 283                                         regulator-on-in-suspend;
 284                                         regulator-suspend-microvolt = <1000000>;
 285                                 };
 286                         };
 287
 288                         vdd10_lcd_pwren_h: LDO_REG7 {
 289                                 regulator-name = "vdd10_lcd_pwren_h";
 290                                 regulator-always-on;
 291                                 regulator-boot-on;
 292                                 regulator-min-microvolt = <2500000>;
 293                                 regulator-max-microvolt = <2500000>;
 294                                 regulator-state-mem {
 295                                         regulator-off-in-suspend;
 296                                 };
 297                         };
 298
 299                         vcc33_lcd: SWITCH_REG1 {
 300                                 regulator-name = "vcc33_lcd";
 301                                 regulator-always-on;
 302                                 regulator-boot-on;
 303                                 regulator-state-mem {
 304                                         regulator-off-in-suspend;
 305                                 };
 306                         };
 307                 };
 308         };
 309 };
 310
 311 &i2c1 {
 312         status = "okay";
 313
 314         clock-frequency = <400000>;
 315         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 316         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 317
 318         tpm: tpm@20 {
 319                 compatible = "infineon,slb9645tt";
 320                 reg = <0x20>;
 321                 powered-while-suspended;
 322         };
 323 };
 324
 325 &i2c2 {
 326         status = "okay";
 327
 328         /* 100kHz since 4.7k resistors don't rise fast enough */
 329         clock-frequency = <100000>;
 330         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 331         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 332 };
 333
 334 &i2c4 {
 335         status = "okay";
 336
 337         clock-frequency = <400000>;
 338         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 339         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 340 };
 341
 342 &i2c5 {
 343         status = "okay";
 344
 345         clock-frequency = <100000>;
 346         i2c-scl-falling-time-ns = <300>;
 347         i2c-scl-rising-time-ns = <1000>;
 348 };
 349
 350 &io_domains {
 351         status = "okay";
 352
 353         bb-supply = <&vcc33_io>;
 354         dvp-supply = <&vcc_18>;
 355         flash0-supply = <&vcc18_flashio>;
 356         gpio1830-supply = <&vcc33_io>;
 357         gpio30-supply = <&vcc33_io>;
 358         lcdc-supply = <&vcc33_lcd>;
 359         wifi-supply = <&vcc18_wl>;
 360 };
 361
 362 &pwm1 {
 363         status = "okay";
 364 };
 365
 366 &sdio0 {
 367         status = "okay";
 368
 369         bus-width = <4>;
 370         cap-sd-highspeed;
 371         cap-sdio-irq;
 372         keep-power-in-suspend;
 373         mmc-pwrseq = <&sdio_pwrseq>;
 374         non-removable;
 375         num-slots = <1>;
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 378         sd-uhs-sdr12;
 379         sd-uhs-sdr25;
 380         sd-uhs-sdr50;
 381         sd-uhs-sdr104;
 382         vmmc-supply = <&vcc33_sys>;
 383         vqmmc-supply = <&vcc18_wl>;
 384 };
 385
 386 &spi2 {
 387         status = "okay";
 388
 389         rx-sample-delay-ns = <12>;
 390
 391         flash@0 {
 392                 compatible = "jedec,spi-nor";
 393                 spi-max-frequency = <50000000>;
 394                 reg = <0>;
 395         };
 396 };
 397
 398 &tsadc {
 399         status = "okay";
 400
 401         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 402         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 403 };
 404
 405 &uart0 {
 406         status = "okay";
 407
 408         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 409         assigned-clocks = <&cru SCLK_UART0>;
 410         assigned-clock-rates = <48000000>;
 411
 412         /* Pins don't include flow control by default; add that in */
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 415 };
 416
 417 &uart1 {
 418         status = "okay";
 419 };
 420
 421 &uart2 {
 422         status = "okay";
 423 };
 424
 425 &usbphy {
 426         status = "okay";
 427 };
 428
 429 &usb_host0_ehci {
 430         status = "okay";
 431
 432         needs-reset-on-resume;
 433 };
 434
 435 &usb_host1 {
 436         status = "okay";
 437 };
 438
 439 &usb_otg {
 440         status = "okay";
 441
 442         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 443         assigned-clock-parents = <&usbphy0>;
 444         dr_mode = "host";
 445 };
 446
 447 &vopb {
 448         status = "okay";
 449 };
 450
 451 &vopb_mmu {
 452         status = "okay";
 453 };
 454
 455 &wdt {
 456         status = "okay";
 457 };
 458
 459 &pinctrl {
 460         pinctrl-names = "default", "sleep";
 461         pinctrl-0 = <
 462                 /* Common for sleep and wake, but no owners */
 463                 &global_pwroff
 464         >;
 465         pinctrl-1 = <
 466                 /* Common for sleep and wake, but no owners */
 467                 &global_pwroff
 468         >;
 469
 470         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 471                 bias-disable;
 472                 drive-strength = <8>;
 473         };
 474
 475         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 476                 bias-pull-up;
 477                 drive-strength = <8>;
 478         };
 479
 480         pcfg_output_high: pcfg-output-high {
 481                 output-high;
 482         };
 483
 484         pcfg_output_low: pcfg-output-low {
 485                 output-low;
 486         };
 487
 488         buttons {
 489                 pwr_key_l: pwr-key-l {
 490                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 491                 };
 492         };
 493
 494         emmc {
 495                 emmc_reset: emmc-reset {
 496                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 497                 };
 498
 499                 /*
 500                  * We run eMMC at max speed; bump up drive strength.
 501                  * We also have external pulls, so disable the internal ones.
 502                  */
 503                 emmc_clk: emmc-clk {
 504                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 505                 };
 506
 507                 emmc_cmd: emmc-cmd {
 508                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 509                 };
 510
 511                 emmc_bus8: emmc-bus8 {
 512                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 513                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 514                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 515                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 516                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 517                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 518                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 519                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 520                 };
 521         };
 522
 523         pmic {
 524                 pmic_int_l: pmic-int-l {
 525                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 526                 };
 527         };
 528
 529         reboot {
 530                 ap_warm_reset_h: ap-warm-reset-h {
 531                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 532                 };
 533         };
 534
 535         recovery-switch {
 536                 rec_mode_l: rec-mode-l {
 537                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 538                 };
 539         };
 540
 541         sdio0 {
 542                 wifi_enable_h: wifienable-h {
 543                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 544                 };
 545
 546                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 547                 bt_enable_l: bt-enable-l {
 548                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 549                 };
 550
 551                 /*
 552                  * We run sdio0 at max speed; bump up drive strength.
 553                  * We also have external pulls, so disable the internal ones.
 554                  */
 555                 sdio0_bus4: sdio0-bus4 {
 556                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 557                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 558                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 559                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 560                 };
 561
 562                 sdio0_cmd: sdio0-cmd {
 563                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 564                 };
 565
 566                 sdio0_clk: sdio0-clk {
 567                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 568                 };
 569         };
 570
 571         tpm {
 572                 tpm_int_h: tpm-int-h {
 573                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 574                 };
 575         };
 576
 577         write-protect {
 578                 fw_wp_ap: fw-wp-ap {
 579                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 580                 };
 581         };
 582 };