arch/arm/boot/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         chosen {
  14                 stdout-path = "serial2:115200n8";
  15         };
  16
  17         /*
  18          * The default coreboot on veyron devices ignores memory@0 nodes
  19          * and would instead create another memory node.
  20          */
  21         memory {
  22                 device_type = "memory";
  23                 reg = <0x0 0x0 0x0 0x80000000>;
  24         };
  25
  26         gpio_keys: gpio-keys {
  27                 compatible = "gpio-keys";
  28
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pwr_key_l>;
  31                 power {
  32                         label = "Power";
  33                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_POWER>;
  35                         debounce-interval = <100>;
  36                         wakeup-source;
  37                 };
  38         };
  39
  40         gpio-restart {
  41                 compatible = "gpio-restart";
  42                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&ap_warm_reset_h>;
  45                 priority = <200>;
  46         };
  47
  48         emmc_pwrseq: emmc-pwrseq {
  49                 compatible = "mmc-pwrseq-emmc";
  50                 pinctrl-0 = <&emmc_reset>;
  51                 pinctrl-names = "default";
  52                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  53         };
  54
  55         sdio_pwrseq: sdio-pwrseq {
  56                 compatible = "mmc-pwrseq-simple";
  57                 clocks = <&rk808 RK808_CLKOUT1>;
  58                 clock-names = "ext_clock";
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  61
  62                 /*
  63                  * On the module itself this is one of these (depending
  64                  * on the actual card populated):
  65                  * - SDIO_RESET_L_WL_REG_ON
  66                  * - PDN (power down when low)
  67                  */
  68                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
  69         };
  70
  71         vcc_5v: vcc-5v {
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "vcc_5v";
  74                 regulator-always-on;
  75                 regulator-boot-on;
  76                 regulator-min-microvolt = <5000000>;
  77                 regulator-max-microvolt = <5000000>;
  78         };
  79
  80         vcc33_sys: vcc33-sys {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "vcc33_sys";
  83                 regulator-always-on;
  84                 regulator-boot-on;
  85                 regulator-min-microvolt = <3300000>;
  86                 regulator-max-microvolt = <3300000>;
  87         };
  88
  89         vcc50_hdmi: vcc50-hdmi {
  90                 compatible = "regulator-fixed";
  91                 regulator-name = "vcc50_hdmi";
  92                 regulator-always-on;
  93                 regulator-boot-on;
  94                 vin-supply = <&vcc_5v>;
  95         };
  96 };
  97
  98 &cpu0 {
  99         cpu0-supply = <&vdd_cpu>;
 100 };
 101
 102 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
 103 &cpu_opp_table {
 104         /delete-node/ opp-312000000;
 105
 106         opp-1512000000 {
 107                 opp-microvolt = <1250000>;
 108         };
 109         opp-1608000000 {
 110                 opp-microvolt = <1300000>;
 111         };
 112         opp-1704000000 {
 113                 opp-hz = /bits/ 64 <1704000000>;
 114                 opp-microvolt = <1350000>;
 115         };
 116         opp-1800000000 {
 117                 opp-hz = /bits/ 64 <1800000000>;
 118                 opp-microvolt = <1400000>;
 119         };
 120 };
 121
 122 &emmc {
 123         status = "okay";
 124
 125         bus-width = <8>;
 126         cap-mmc-highspeed;
 127         rockchip,default-sample-phase = <158>;
 128         disable-wp;
 129         mmc-hs200-1_8v;
 130         mmc-pwrseq = <&emmc_pwrseq>;
 131         non-removable;
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 134 };
 135
 136 &gpu {
 137         mali-supply = <&vdd_gpu>;
 138         status = "okay";
 139 };
 140
 141 &hdmi {
 142         ddc-i2c-bus = <&i2c5>;
 143         status = "okay";
 144 };
 145
 146 &i2c0 {
 147         status = "okay";
 148
 149         clock-frequency = <400000>;
 150         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 151         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 152
 153         rk808: pmic@1b {
 154                 compatible = "rockchip,rk808";
 155                 reg = <0x1b>;
 156                 clock-output-names = "xin32k", "wifibt_32kin";
 157                 interrupt-parent = <&gpio0>;
 158                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 159                 pinctrl-names = "default";
 160                 pinctrl-0 = <&pmic_int_l>;
 161                 rockchip,system-power-controller;
 162                 wakeup-source;
 163                 #clock-cells = <1>;
 164
 165                 vcc1-supply = <&vcc33_sys>;
 166                 vcc2-supply = <&vcc33_sys>;
 167                 vcc3-supply = <&vcc33_sys>;
 168                 vcc4-supply = <&vcc33_sys>;
 169                 vcc6-supply = <&vcc_5v>;
 170                 vcc7-supply = <&vcc33_sys>;
 171                 vcc8-supply = <&vcc33_sys>;
 172                 vcc12-supply = <&vcc_18>;
 173                 vddio-supply = <&vcc33_io>;
 174
 175                 regulators {
 176                         vdd_cpu: DCDC_REG1 {
 177                                 regulator-name = "vdd_arm";
 178                                 regulator-always-on;
 179                                 regulator-boot-on;
 180                                 regulator-min-microvolt = <750000>;
 181                                 regulator-max-microvolt = <1450000>;
 182                                 regulator-ramp-delay = <6001>;
 183                                 regulator-state-mem {
 184                                         regulator-off-in-suspend;
 185                                 };
 186                         };
 187
 188                         vdd_gpu: DCDC_REG2 {
 189                                 regulator-name = "vdd_gpu";
 190                                 regulator-always-on;
 191                                 regulator-boot-on;
 192                                 regulator-min-microvolt = <800000>;
 193                                 regulator-max-microvolt = <1250000>;
 194                                 regulator-ramp-delay = <6001>;
 195                                 regulator-state-mem {
 196                                         regulator-on-in-suspend;
 197                                         regulator-suspend-microvolt = <1000000>;
 198                                 };
 199                         };
 200
 201                         vcc135_ddr: DCDC_REG3 {
 202                                 regulator-name = "vcc135_ddr";
 203                                 regulator-always-on;
 204                                 regulator-boot-on;
 205                                 regulator-state-mem {
 206                                         regulator-on-in-suspend;
 207                                 };
 208                         };
 209
 210                         /*
 211                          * vcc_18 has several aliases.  (vcc18_flashio and
 212                          * vcc18_wl).  We'll add those aliases here just to
 213                          * make it easier to follow the schematic.  The signals
 214                          * are actually hooked together and only separated for
 215                          * power measurement purposes).
 216                          */
 217                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 218                                 regulator-name = "vcc_18";
 219                                 regulator-always-on;
 220                                 regulator-boot-on;
 221                                 regulator-min-microvolt = <1800000>;
 222                                 regulator-max-microvolt = <1800000>;
 223                                 regulator-state-mem {
 224                                         regulator-on-in-suspend;
 225                                         regulator-suspend-microvolt = <1800000>;
 226                                 };
 227                         };
 228
 229                         /*
 230                          * Note that both vcc33_io and vcc33_pmuio are always
 231                          * powered together. To simplify the logic in the dts
 232                          * we just refer to vcc33_io every time something is
 233                          * powered from vcc33_pmuio. In fact, on later boards
 234                          * (such as danger) they're the same net.
 235                          */
 236                         vcc33_io: LDO_REG1 {
 237                                 regulator-name = "vcc33_io";
 238                                 regulator-always-on;
 239                                 regulator-boot-on;
 240                                 regulator-min-microvolt = <3300000>;
 241                                 regulator-max-microvolt = <3300000>;
 242                                 regulator-state-mem {
 243                                         regulator-on-in-suspend;
 244                                         regulator-suspend-microvolt = <3300000>;
 245                                 };
 246                         };
 247
 248                         vdd_10: LDO_REG3 {
 249                                 regulator-name = "vdd_10";
 250                                 regulator-always-on;
 251                                 regulator-boot-on;
 252                                 regulator-min-microvolt = <1000000>;
 253                                 regulator-max-microvolt = <1000000>;
 254                                 regulator-state-mem {
 255                                         regulator-on-in-suspend;
 256                                         regulator-suspend-microvolt = <1000000>;
 257                                 };
 258                         };
 259
 260                         vdd10_lcd_pwren_h: LDO_REG7 {
 261                                 regulator-name = "vdd10_lcd_pwren_h";
 262                                 regulator-always-on;
 263                                 regulator-boot-on;
 264                                 regulator-min-microvolt = <2500000>;
 265                                 regulator-max-microvolt = <2500000>;
 266                                 regulator-state-mem {
 267                                         regulator-off-in-suspend;
 268                                 };
 269                         };
 270
 271                         vcc33_lcd: SWITCH_REG1 {
 272                                 regulator-name = "vcc33_lcd";
 273                                 regulator-always-on;
 274                                 regulator-boot-on;
 275                                 regulator-state-mem {
 276                                         regulator-off-in-suspend;
 277                                 };
 278                         };
 279                 };
 280         };
 281 };
 282
 283 &i2c1 {
 284         status = "okay";
 285
 286         clock-frequency = <400000>;
 287         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 288         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 289
 290         tpm: tpm@20 {
 291                 compatible = "infineon,slb9645tt";
 292                 reg = <0x20>;
 293                 powered-while-suspended;
 294         };
 295 };
 296
 297 &i2c2 {
 298         status = "okay";
 299
 300         /* 100kHz since 4.7k resistors don't rise fast enough */
 301         clock-frequency = <100000>;
 302         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 303         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 304 };
 305
 306 &i2c4 {
 307         status = "okay";
 308
 309         clock-frequency = <400000>;
 310         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 311         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 312 };
 313
 314 &i2c5 {
 315         status = "okay";
 316
 317         clock-frequency = <100000>;
 318         i2c-scl-falling-time-ns = <300>;
 319         i2c-scl-rising-time-ns = <1000>;
 320 };
 321
 322 &io_domains {
 323         status = "okay";
 324
 325         bb-supply = <&vcc33_io>;
 326         dvp-supply = <&vcc_18>;
 327         flash0-supply = <&vcc18_flashio>;
 328         gpio1830-supply = <&vcc33_io>;
 329         gpio30-supply = <&vcc33_io>;
 330         lcdc-supply = <&vcc33_lcd>;
 331         wifi-supply = <&vcc18_wl>;
 332 };
 333
 334 &pwm1 {
 335         status = "okay";
 336 };
 337
 338 &sdio0 {
 339         status = "okay";
 340
 341         bus-width = <4>;
 342         cap-sd-highspeed;
 343         cap-sdio-irq;
 344         keep-power-in-suspend;
 345         mmc-pwrseq = <&sdio_pwrseq>;
 346         non-removable;
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 349         sd-uhs-sdr12;
 350         sd-uhs-sdr25;
 351         sd-uhs-sdr50;
 352         sd-uhs-sdr104;
 353         vmmc-supply = <&vcc33_sys>;
 354         vqmmc-supply = <&vcc18_wl>;
 355 };
 356
 357 &spi2 {
 358         status = "okay";
 359
 360         rx-sample-delay-ns = <12>;
 361
 362         flash@0 {
 363                 compatible = "jedec,spi-nor";
 364                 spi-max-frequency = <50000000>;
 365                 reg = <0>;
 366         };
 367 };
 368
 369 &tsadc {
 370         status = "okay";
 371
 372         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 373         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 374 };
 375
 376 &uart0 {
 377         status = "okay";
 378
 379         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 380         assigned-clocks = <&cru SCLK_UART0>;
 381         assigned-clock-rates = <48000000>;
 382
 383         /* Pins don't include flow control by default; add that in */
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 386 };
 387
 388 &uart1 {
 389         status = "okay";
 390 };
 391
 392 &uart2 {
 393         status = "okay";
 394 };
 395
 396 &usbphy {
 397         status = "okay";
 398 };
 399
 400 &usb_host0_ehci {
 401         status = "okay";
 402
 403         needs-reset-on-resume;
 404 };
 405
 406 &usb_host1 {
 407         status = "okay";
 408 };
 409
 410 &usb_otg {
 411         status = "okay";
 412
 413         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 414         assigned-clock-parents = <&usbphy0>;
 415         dr_mode = "host";
 416 };
 417
 418 &vopb {
 419         status = "okay";
 420 };
 421
 422 &vopb_mmu {
 423         status = "okay";
 424 };
 425
 426 &wdt {
 427         status = "okay";
 428 };
 429
 430 &pinctrl {
 431         pinctrl-names = "default", "sleep";
 432         pinctrl-0 = <
 433                 /* Common for sleep and wake, but no owners */
 434                 &global_pwroff
 435         >;
 436         pinctrl-1 = <
 437                 /* Common for sleep and wake, but no owners */
 438                 &global_pwroff
 439         >;
 440
 441         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 442                 bias-disable;
 443                 drive-strength = <8>;
 444         };
 445
 446         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 447                 bias-pull-up;
 448                 drive-strength = <8>;
 449         };
 450
 451         pcfg_output_high: pcfg-output-high {
 452                 output-high;
 453         };
 454
 455         pcfg_output_low: pcfg-output-low {
 456                 output-low;
 457         };
 458
 459         buttons {
 460                 pwr_key_l: pwr-key-l {
 461                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 462                 };
 463         };
 464
 465         emmc {
 466                 emmc_reset: emmc-reset {
 467                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 468                 };
 469
 470                 /*
 471                  * We run eMMC at max speed; bump up drive strength.
 472                  * We also have external pulls, so disable the internal ones.
 473                  */
 474                 emmc_clk: emmc-clk {
 475                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 476                 };
 477
 478                 emmc_cmd: emmc-cmd {
 479                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 480                 };
 481
 482                 emmc_bus8: emmc-bus8 {
 483                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 484                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 485                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 486                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 487                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 488                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 489                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 490                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 491                 };
 492         };
 493
 494         pmic {
 495                 pmic_int_l: pmic-int-l {
 496                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 497                 };
 498         };
 499
 500         reboot {
 501                 ap_warm_reset_h: ap-warm-reset-h {
 502                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 503                 };
 504         };
 505
 506         recovery-switch {
 507                 rec_mode_l: rec-mode-l {
 508                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 509                 };
 510         };
 511
 512         sdio0 {
 513                 wifi_enable_h: wifienable-h {
 514                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 515                 };
 516
 517                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 518                 bt_enable_l: bt-enable-l {
 519                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 520                 };
 521
 522                 /*
 523                  * We run sdio0 at max speed; bump up drive strength.
 524                  * We also have external pulls, so disable the internal ones.
 525                  */
 526                 sdio0_bus4: sdio0-bus4 {
 527                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 528                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 529                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 530                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 531                 };
 532
 533                 sdio0_cmd: sdio0-cmd {
 534                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 535                 };
 536
 537                 sdio0_clk: sdio0-clk {
 538                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 539                 };
 540         };
 541
 542         tpm {
 543                 tpm_int_h: tpm-int-h {
 544                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 545                 };
 546         };
 547
 548         write-protect {
 549                 fw_wp_ap: fw-wp-ap {
 550                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 551                 };
 552         };
 553 };