Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / rk3288-veyron.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Google Veyron (and derivatives) board device tree source
4  *
5  * Copyright 2015 Google, Inc
6  */
7
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288.dtsi"
11
12 / {
13         chosen {
14                 stdout-path = "serial2:115200n8";
15         };
16
17         /*
18          * The default coreboot on veyron devices ignores memory@0 nodes
19          * and would instead create another memory node.
20          */
21         memory {
22                 device_type = "memory";
23                 reg = <0x0 0x0 0x0 0x80000000>;
24         };
25
26         gpio_keys: gpio-keys {
27                 compatible = "gpio-keys";
28
29                 pinctrl-names = "default";
30                 pinctrl-0 = <&pwr_key_l>;
31                 power {
32                         label = "Power";
33                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
34                         linux,code = <KEY_POWER>;
35                         debounce-interval = <100>;
36                         wakeup-source;
37                 };
38         };
39
40         gpio-restart {
41                 compatible = "gpio-restart";
42                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
43                 pinctrl-names = "default";
44                 pinctrl-0 = <&ap_warm_reset_h>;
45                 priority = <200>;
46         };
47
48         emmc_pwrseq: emmc-pwrseq {
49                 compatible = "mmc-pwrseq-emmc";
50                 pinctrl-0 = <&emmc_reset>;
51                 pinctrl-names = "default";
52                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
53         };
54
55         sdio_pwrseq: sdio-pwrseq {
56                 compatible = "mmc-pwrseq-simple";
57                 clocks = <&rk808 RK808_CLKOUT1>;
58                 clock-names = "ext_clock";
59                 pinctrl-names = "default";
60                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
61
62                 /*
63                  * Depending on the actual card populated GPIO4 D4 and D5
64                  * correspond to one of these signals on the module:
65                  *
66                  * D4:
67                  * - SDIO_RESET_L_WL_REG_ON
68                  * - PDN (power down when low)
69                  *
70                  * D5:
71                  * - BT_I2S_WS_BT_RFDISABLE_L
72                  * - No connect
73                  */
74                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
75                               <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
76         };
77
78         vcc_5v: vcc-5v {
79                 compatible = "regulator-fixed";
80                 regulator-name = "vcc_5v";
81                 regulator-always-on;
82                 regulator-boot-on;
83                 regulator-min-microvolt = <5000000>;
84                 regulator-max-microvolt = <5000000>;
85         };
86
87         vcc33_sys: vcc33-sys {
88                 compatible = "regulator-fixed";
89                 regulator-name = "vcc33_sys";
90                 regulator-always-on;
91                 regulator-boot-on;
92                 regulator-min-microvolt = <3300000>;
93                 regulator-max-microvolt = <3300000>;
94         };
95
96         vcc50_hdmi: vcc50-hdmi {
97                 compatible = "regulator-fixed";
98                 regulator-name = "vcc50_hdmi";
99                 regulator-always-on;
100                 regulator-boot-on;
101                 vin-supply = <&vcc_5v>;
102         };
103
104         vdd_logic: vdd-logic {
105                 compatible = "pwm-regulator";
106                 regulator-name = "vdd_logic";
107
108                 pwms = <&pwm1 0 1994 0>;
109                 pwm-supply = <&vcc33_sys>;
110
111                 pwm-dutycycle-range = <0x7b 0>;
112                 pwm-dutycycle-unit = <0x94>;
113
114                 regulator-always-on;
115                 regulator-boot-on;
116                 regulator-min-microvolt = <950000>;
117                 regulator-max-microvolt = <1350000>;
118                 regulator-ramp-delay = <4000>;
119         };
120 };
121
122 &cpu0 {
123         cpu0-supply = <&vdd_cpu>;
124 };
125
126 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
127 &cpu_opp_table {
128         /delete-node/ opp-312000000;
129
130         opp-1512000000 {
131                 opp-microvolt = <1250000>;
132         };
133         opp-1608000000 {
134                 opp-microvolt = <1300000>;
135         };
136         opp-1704000000 {
137                 opp-hz = /bits/ 64 <1704000000>;
138                 opp-microvolt = <1350000>;
139         };
140         opp-1800000000 {
141                 opp-hz = /bits/ 64 <1800000000>;
142                 opp-microvolt = <1400000>;
143         };
144 };
145
146 &emmc {
147         status = "okay";
148
149         bus-width = <8>;
150         cap-mmc-highspeed;
151         rockchip,default-sample-phase = <158>;
152         disable-wp;
153         mmc-hs200-1_8v;
154         mmc-pwrseq = <&emmc_pwrseq>;
155         non-removable;
156         pinctrl-names = "default";
157         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
158 };
159
160 &gpu {
161         mali-supply = <&vdd_gpu>;
162         status = "okay";
163 };
164
165 &hdmi {
166         ddc-i2c-bus = <&i2c5>;
167         status = "okay";
168 };
169
170 &i2c0 {
171         status = "okay";
172
173         clock-frequency = <400000>;
174         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
175         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
176
177         rk808: pmic@1b {
178                 compatible = "rockchip,rk808";
179                 reg = <0x1b>;
180                 clock-output-names = "xin32k", "wifibt_32kin";
181                 interrupt-parent = <&gpio0>;
182                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
183                 pinctrl-names = "default";
184                 pinctrl-0 = <&pmic_int_l>;
185                 rockchip,system-power-controller;
186                 wakeup-source;
187                 #clock-cells = <1>;
188
189                 vcc1-supply = <&vcc33_sys>;
190                 vcc2-supply = <&vcc33_sys>;
191                 vcc3-supply = <&vcc33_sys>;
192                 vcc4-supply = <&vcc33_sys>;
193                 vcc6-supply = <&vcc_5v>;
194                 vcc7-supply = <&vcc33_sys>;
195                 vcc8-supply = <&vcc33_sys>;
196                 vcc12-supply = <&vcc_18>;
197                 vddio-supply = <&vcc33_io>;
198
199                 regulators {
200                         vdd_cpu: DCDC_REG1 {
201                                 regulator-name = "vdd_arm";
202                                 regulator-always-on;
203                                 regulator-boot-on;
204                                 regulator-min-microvolt = <750000>;
205                                 regulator-max-microvolt = <1450000>;
206                                 regulator-ramp-delay = <6001>;
207                                 regulator-state-mem {
208                                         regulator-off-in-suspend;
209                                 };
210                         };
211
212                         vdd_gpu: DCDC_REG2 {
213                                 regulator-name = "vdd_gpu";
214                                 regulator-always-on;
215                                 regulator-boot-on;
216                                 regulator-min-microvolt = <800000>;
217                                 regulator-max-microvolt = <1250000>;
218                                 regulator-ramp-delay = <6001>;
219                                 regulator-state-mem {
220                                         regulator-off-in-suspend;
221                                 };
222                         };
223
224                         vcc135_ddr: DCDC_REG3 {
225                                 regulator-name = "vcc135_ddr";
226                                 regulator-always-on;
227                                 regulator-boot-on;
228                                 regulator-state-mem {
229                                         regulator-on-in-suspend;
230                                 };
231                         };
232
233                         /*
234                          * vcc_18 has several aliases.  (vcc18_flashio and
235                          * vcc18_wl).  We'll add those aliases here just to
236                          * make it easier to follow the schematic.  The signals
237                          * are actually hooked together and only separated for
238                          * power measurement purposes).
239                          */
240                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
241                                 regulator-name = "vcc_18";
242                                 regulator-always-on;
243                                 regulator-boot-on;
244                                 regulator-min-microvolt = <1800000>;
245                                 regulator-max-microvolt = <1800000>;
246                                 regulator-state-mem {
247                                         regulator-on-in-suspend;
248                                         regulator-suspend-microvolt = <1800000>;
249                                 };
250                         };
251
252                         /*
253                          * Note that both vcc33_io and vcc33_pmuio are always
254                          * powered together. To simplify the logic in the dts
255                          * we just refer to vcc33_io every time something is
256                          * powered from vcc33_pmuio. In fact, on later boards
257                          * (such as danger) they're the same net.
258                          */
259                         vcc33_io: LDO_REG1 {
260                                 regulator-name = "vcc33_io";
261                                 regulator-always-on;
262                                 regulator-boot-on;
263                                 regulator-min-microvolt = <3300000>;
264                                 regulator-max-microvolt = <3300000>;
265                                 regulator-state-mem {
266                                         regulator-on-in-suspend;
267                                         regulator-suspend-microvolt = <3300000>;
268                                 };
269                         };
270
271                         vdd_10: LDO_REG3 {
272                                 regulator-name = "vdd_10";
273                                 regulator-always-on;
274                                 regulator-boot-on;
275                                 regulator-min-microvolt = <1000000>;
276                                 regulator-max-microvolt = <1000000>;
277                                 regulator-state-mem {
278                                         regulator-on-in-suspend;
279                                         regulator-suspend-microvolt = <1000000>;
280                                 };
281                         };
282
283                         vdd10_lcd_pwren_h: LDO_REG7 {
284                                 regulator-name = "vdd10_lcd_pwren_h";
285                                 regulator-always-on;
286                                 regulator-boot-on;
287                                 regulator-min-microvolt = <2500000>;
288                                 regulator-max-microvolt = <2500000>;
289                                 regulator-state-mem {
290                                         regulator-off-in-suspend;
291                                 };
292                         };
293
294                         vcc33_lcd: SWITCH_REG1 {
295                                 regulator-name = "vcc33_lcd";
296                                 regulator-always-on;
297                                 regulator-boot-on;
298                                 regulator-state-mem {
299                                         regulator-off-in-suspend;
300                                 };
301                         };
302                 };
303         };
304 };
305
306 &i2c1 {
307         status = "okay";
308
309         clock-frequency = <400000>;
310         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
311         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
312
313         tpm: tpm@20 {
314                 compatible = "infineon,slb9645tt";
315                 reg = <0x20>;
316                 powered-while-suspended;
317         };
318 };
319
320 &i2c2 {
321         status = "okay";
322
323         /* 100kHz since 4.7k resistors don't rise fast enough */
324         clock-frequency = <100000>;
325         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
326         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
327 };
328
329 &i2c4 {
330         status = "okay";
331
332         clock-frequency = <400000>;
333         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
334         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
335 };
336
337 &i2c5 {
338         status = "okay";
339
340         clock-frequency = <100000>;
341         i2c-scl-falling-time-ns = <300>;
342         i2c-scl-rising-time-ns = <1000>;
343 };
344
345 &io_domains {
346         status = "okay";
347
348         bb-supply = <&vcc33_io>;
349         dvp-supply = <&vcc_18>;
350         flash0-supply = <&vcc18_flashio>;
351         gpio1830-supply = <&vcc33_io>;
352         gpio30-supply = <&vcc33_io>;
353         lcdc-supply = <&vcc33_lcd>;
354         wifi-supply = <&vcc18_wl>;
355 };
356
357 &pwm1 {
358         status = "okay";
359 };
360
361 &sdio0 {
362         status = "okay";
363
364         bus-width = <4>;
365         cap-sd-highspeed;
366         cap-sdio-irq;
367         keep-power-in-suspend;
368         mmc-pwrseq = <&sdio_pwrseq>;
369         non-removable;
370         pinctrl-names = "default";
371         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
372         sd-uhs-sdr12;
373         sd-uhs-sdr25;
374         sd-uhs-sdr50;
375         sd-uhs-sdr104;
376         vmmc-supply = <&vcc33_sys>;
377         vqmmc-supply = <&vcc18_wl>;
378 };
379
380 &spi2 {
381         status = "okay";
382
383         rx-sample-delay-ns = <12>;
384
385         flash@0 {
386                 compatible = "jedec,spi-nor";
387                 spi-max-frequency = <50000000>;
388                 reg = <0>;
389         };
390 };
391
392 &tsadc {
393         status = "okay";
394
395         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
396         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
397 };
398
399 &uart0 {
400         status = "okay";
401
402         /* Pins don't include flow control by default; add that in */
403         pinctrl-names = "default";
404         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
405 };
406
407 &uart1 {
408         status = "okay";
409 };
410
411 &uart2 {
412         status = "okay";
413 };
414
415 &usbphy {
416         status = "okay";
417 };
418
419 &usb_host0_ehci {
420         status = "okay";
421
422         needs-reset-on-resume;
423 };
424
425 &usb_host1 {
426         status = "okay";
427 };
428
429 &usb_otg {
430         status = "okay";
431
432         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
433         assigned-clock-parents = <&usbphy0>;
434         dr_mode = "host";
435 };
436
437 &vopb {
438         status = "okay";
439 };
440
441 &vopb_mmu {
442         status = "okay";
443 };
444
445 &wdt {
446         status = "okay";
447 };
448
449 &pinctrl {
450         pinctrl-names = "default", "sleep";
451         pinctrl-0 = <
452                 /* Common for sleep and wake, but no owners */
453                 &ddr0_retention
454                 &ddrio_pwroff
455                 &global_pwroff
456         >;
457         pinctrl-1 = <
458                 /* Common for sleep and wake, but no owners */
459                 &ddr0_retention
460                 &ddrio_pwroff
461                 &global_pwroff
462         >;
463
464         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
465                 bias-disable;
466                 drive-strength = <8>;
467         };
468
469         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
470                 bias-pull-up;
471                 drive-strength = <8>;
472         };
473
474         pcfg_output_high: pcfg-output-high {
475                 output-high;
476         };
477
478         pcfg_output_low: pcfg-output-low {
479                 output-low;
480         };
481
482         buttons {
483                 pwr_key_l: pwr-key-l {
484                         rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
485                 };
486         };
487
488         emmc {
489                 emmc_reset: emmc-reset {
490                         rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
491                 };
492
493                 /*
494                  * We run eMMC at max speed; bump up drive strength.
495                  * We also have external pulls, so disable the internal ones.
496                  */
497                 emmc_clk: emmc-clk {
498                         rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
499                 };
500
501                 emmc_cmd: emmc-cmd {
502                         rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
503                 };
504
505                 emmc_bus8: emmc-bus8 {
506                         rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
507                                         <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
508                                         <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
509                                         <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
510                                         <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
511                                         <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
512                                         <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
513                                         <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
514                 };
515         };
516
517         pmic {
518                 pmic_int_l: pmic-int-l {
519                         rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
520                 };
521         };
522
523         reboot {
524                 ap_warm_reset_h: ap-warm-reset-h {
525                         rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
526                 };
527         };
528
529         recovery-switch {
530                 rec_mode_l: rec-mode-l {
531                         rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
532                 };
533         };
534
535         sdio0 {
536                 wifi_enable_h: wifienable-h {
537                         rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
538                 };
539
540                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
541                 bt_enable_l: bt-enable-l {
542                         rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
543                 };
544
545                 /*
546                  * We run sdio0 at max speed; bump up drive strength.
547                  * We also have external pulls, so disable the internal ones.
548                  */
549                 sdio0_bus4: sdio0-bus4 {
550                         rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
551                                         <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
552                                         <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
553                                         <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
554                 };
555
556                 sdio0_cmd: sdio0-cmd {
557                         rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
558                 };
559
560                 sdio0_clk: sdio0-clk {
561                         rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
562                 };
563         };
564
565         tpm {
566                 tpm_int_h: tpm-int-h {
567                         rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
568                 };
569         };
570
571         write-protect {
572                 fw_wp_ap: fw-wp-ap {
573                         rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
574                 };
575         };
576 };