arch/arm/boot/dts/rk3288-veyron-speedy.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron Speedy Rev 1+ board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9 #include "rk3288-veyron-chromebook.dtsi"
  10 #include "cros-ec-sbs.dtsi"
  11
  12 / {
  13         model = "Google Speedy";
  14         compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
  15                      "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
  16                      "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
  17                      "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
  18                      "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
  19
  20         panel_regulator: panel-regulator {
  21                 compatible = "regulator-fixed";
  22                 enable-active-high;
  23                 gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&lcd_enable_h>;
  26                 regulator-name = "panel_regulator";
  27                 startup-delay-us = <100000>;
  28                 vin-supply = <&vcc33_sys>;
  29         };
  30
  31         vcc18_lcd: vcc18-lcd {
  32                 compatible = "regulator-fixed";
  33                 enable-active-high;
  34                 gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
  35                 pinctrl-names = "default";
  36                 pinctrl-0 = <&avdd_1v8_disp_en>;
  37                 regulator-name = "vcc18_lcd";
  38                 regulator-always-on;
  39                 regulator-boot-on;
  40                 vin-supply = <&vcc18_wl>;
  41         };
  42
  43         backlight_regulator: backlight-regulator {
  44                 compatible = "regulator-fixed";
  45                 enable-active-high;
  46                 gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
  47                 pinctrl-names = "default";
  48                 pinctrl-0 = <&bl_pwr_en>;
  49                 regulator-name = "backlight_regulator";
  50                 vin-supply = <&vcc33_sys>;
  51                 startup-delay-us = <15000>;
  52         };
  53 };
  54
  55 &backlight {
  56         power-supply = <&backlight_regulator>;
  57 };
  58
  59 &cpu_alert0 {
  60         temperature = <65000>;
  61 };
  62
  63 &cpu_alert1 {
  64         temperature = <70000>;
  65 };
  66
  67 &edp {
  68         /delete-property/pinctrl-names;
  69         /delete-property/pinctrl-0;
  70
  71         force-hpd;
  72 };
  73
  74 &panel {
  75         power-supply= <&panel_regulator>;
  76 };
  77
  78 &rk808 {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pmic_int_l>;
  81 };
  82
  83 &sdmmc {
  84         disable-wp;
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
  87                         &sdmmc_bus4>;
  88 };
  89
  90 &vcc_5v {
  91         enable-active-high;
  92         gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&drv_5v>;
  95 };
  96
  97 &vcc50_hdmi {
  98         enable-active-high;
  99         gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&vcc50_hdmi_en>;
 102 };
 103
 104 &pinctrl {
 105         backlight {
 106                 bl_pwr_en: bl_pwr_en {
 107                         rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
 108                 };
 109         };
 110
 111         buck-5v {
 112                 drv_5v: drv-5v {
 113                         rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
 114                 };
 115         };
 116
 117         hdmi {
 118                 vcc50_hdmi_en: vcc50-hdmi-en {
 119                         rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
 120                 };
 121         };
 122
 123         lcd {
 124                 lcd_enable_h: lcd-en {
 125                         rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
 126                 };
 127
 128                 avdd_1v8_disp_en: avdd-1v8-disp-en {
 129                         rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
 130                 };
 131         };
 132
 133         pmic {
 134                 dvs_1: dvs-1 {
 135                         rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
 136                 };
 137
 138                 dvs_2: dvs-2 {
 139                         rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
 140                 };
 141         };
 142 };