arch/arm/boot/dts/rk3288-veyron-speedy.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron Speedy Rev 1+ board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9 #include "rk3288-veyron-chromebook.dtsi"
  10 #include "cros-ec-sbs.dtsi"
  11
  12 / {
  13         model = "Google Speedy";
  14         compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
  15                      "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
  16                      "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
  17                      "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
  18                      "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
  19
  20         panel_regulator: panel-regulator {
  21                 compatible = "regulator-fixed";
  22                 enable-active-high;
  23                 gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&lcd_enable_h>;
  26                 regulator-name = "panel_regulator";
  27                 startup-delay-us = <100000>;
  28                 vin-supply = <&vcc33_sys>;
  29         };
  30
  31         vcc18_lcd: vcc18-lcd {
  32                 compatible = "regulator-fixed";
  33                 enable-active-high;
  34                 gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
  35                 pinctrl-names = "default";
  36                 pinctrl-0 = <&avdd_1v8_disp_en>;
  37                 regulator-name = "vcc18_lcd";
  38                 regulator-always-on;
  39                 regulator-boot-on;
  40                 vin-supply = <&vcc18_wl>;
  41         };
  42
  43         backlight_regulator: backlight-regulator {
  44                 compatible = "regulator-fixed";
  45                 enable-active-high;
  46                 gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
  47                 pinctrl-names = "default";
  48                 pinctrl-0 = <&bl_pwr_en>;
  49                 regulator-name = "backlight_regulator";
  50                 vin-supply = <&vcc33_sys>;
  51                 startup-delay-us = <15000>;
  52         };
  53 };
  54
  55 &backlight {
  56         power-supply = <&backlight_regulator>;
  57 };
  58
  59 &cpu_alert0 {
  60         temperature = <65000>;
  61 };
  62
  63 &cpu_alert1 {
  64         temperature = <70000>;
  65 };
  66
  67 &cpu_crit {
  68         temperature = <90000>;
  69 };
  70
  71 &edp {
  72         /delete-property/pinctrl-names;
  73         /delete-property/pinctrl-0;
  74
  75         force-hpd;
  76 };
  77
  78 &gpu_alert0 {
  79         temperature = <80000>;
  80 };
  81
  82 &gpu_crit {
  83         temperature = <90000>;
  84 };
  85
  86 &panel {
  87         power-supply= <&panel_regulator>;
  88 };
  89
  90 &rk808 {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pmic_int_l>;
  93 };
  94
  95 &sdmmc {
  96         disable-wp;
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
  99                         &sdmmc_bus4>;
 100 };
 101
 102 &vcc_5v {
 103         enable-active-high;
 104         gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&drv_5v>;
 107 };
 108
 109 &vcc50_hdmi {
 110         enable-active-high;
 111         gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&vcc50_hdmi_en>;
 114 };
 115
 116 &gpio0 {
 117         gpio-line-names = "PMIC_SLEEP_AP",
 118                           "DDRIO_PWROFF",
 119                           "DDRIO_RETEN",
 120                           "TS3A227E_INT_L",
 121                           "PMIC_INT_L",
 122                           "PWR_KEY_L",
 123                           "AP_LID_INT_L",
 124                           "EC_IN_RW",
 125
 126                           "AC_PRESENT_AP",
 127                           /*
 128                            * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
 129                            * it REC_MODE_L.
 130                            */
 131                           "RECOVERY_SW_L",
 132                           "OTP_OUT",
 133                           "HOST1_PWR_EN",
 134                           "USBOTG_PWREN_H",
 135                           "AP_WARM_RESET_H",
 136                           "nFALUT2",
 137                           "I2C0_SDA_PMIC",
 138
 139                           "I2C0_SCL_PMIC",
 140                           "SUSPEND_L",
 141                           "USB_INT";
 142 };
 143
 144 &gpio2 {
 145         gpio-line-names = "CONFIG0",
 146                           "CONFIG1",
 147                           "CONFIG2",
 148                           "",
 149                           "",
 150                           "",
 151                           "",
 152                           "CONFIG3",
 153
 154                           "PWRLIMIT#_CPU",
 155                           "EMMC_RST_L",
 156                           "",
 157                           "",
 158                           "BL_PWR_EN",
 159                           "AVDD_1V8_DISP_EN";
 160 };
 161
 162 &gpio3 {
 163         gpio-line-names = "FLASH0_D0",
 164                           "FLASH0_D1",
 165                           "FLASH0_D2",
 166                           "FLASH0_D3",
 167                           "FLASH0_D4",
 168                           "FLASH0_D5",
 169                           "FLASH0_D6",
 170                           "FLASH0_D7",
 171
 172                           "",
 173                           "",
 174                           "",
 175                           "",
 176                           "",
 177                           "",
 178                           "",
 179                           "",
 180
 181                           "FLASH0_CS2/EMMC_CMD",
 182                           "",
 183                           "FLASH0_DQS/EMMC_CLKO";
 184 };
 185
 186 &gpio4 {
 187         gpio-line-names = "",
 188                           "",
 189                           "",
 190                           "",
 191                           "",
 192                           "",
 193                           "",
 194                           "",
 195
 196                           "",
 197                           "",
 198                           "",
 199                           "",
 200                           "",
 201                           "",
 202                           "",
 203                           "",
 204
 205                           "UART0_RXD",
 206                           "UART0_TXD",
 207                           "UART0_CTS",
 208                           "UART0_RTS",
 209                           "SDIO0_D0",
 210                           "SDIO0_D1",
 211                           "SDIO0_D2",
 212                           "SDIO0_D3",
 213
 214                           "SDIO0_CMD",
 215                           "SDIO0_CLK",
 216                           "BT_DEV_WAKE",
 217                           "",
 218                           "WIFI_ENABLE_H",
 219                           "BT_ENABLE_L",
 220                           "WIFI_HOST_WAKE",
 221                           "BT_HOST_WAKE";
 222 };
 223
 224 &gpio5 {
 225         gpio-line-names = "",
 226                           "",
 227                           "",
 228                           "",
 229                           "",
 230                           "",
 231                           "",
 232                           "",
 233
 234                           "",
 235                           "",
 236                           "",
 237                           "",
 238                           "SPI0_CLK",
 239                           "SPI0_CS0",
 240                           "SPI0_TXD",
 241                           "SPI0_RXD",
 242
 243                           "",
 244                           "",
 245                           "",
 246                           "VCC50_HDMI_EN";
 247 };
 248
 249 &gpio6 {
 250         gpio-line-names = "I2S0_SCLK",
 251                           "I2S0_LRCK_RX",
 252                           "I2S0_LRCK_TX",
 253                           "I2S0_SDI",
 254                           "I2S0_SDO0",
 255                           "HP_DET_H",
 256                           "ALS_INT",            /* not connected */
 257                           "INT_CODEC",
 258
 259                           "I2S0_CLK",
 260                           "I2C2_SDA",
 261                           "I2C2_SCL",
 262                           "MICDET",
 263                           "",
 264                           "",
 265                           "",
 266                           "",
 267
 268                           "SDMMC_D0",
 269                           "SDMMC_D1",
 270                           "SDMMC_D2",
 271                           "SDMMC_D3",
 272                           "SDMMC_CLK",
 273                           "SDMMC_CMD";
 274 };
 275
 276 &gpio7 {
 277         gpio-line-names = "LCDC_BL",
 278                           "PWM_LOG",
 279                           "BL_EN",
 280                           "TRACKPAD_INT",
 281                           "TPM_INT_H",
 282                           "SDMMC_DET_L",
 283                           /*
 284                            * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
 285                            * it FW_WP_AP.
 286                            */
 287                           "AP_FLASH_WP_L",
 288                           "EC_INT",
 289
 290                           "CPU_NMI",
 291                           "DVS_OK",
 292                           "",
 293                           "EDP_HOTPLUG",
 294                           "DVS1",
 295                           "nFALUT1",
 296                           "LCD_EN",
 297                           "DVS2",
 298
 299                           "VCC5V_GOOD_H",
 300                           "I2C4_SDA_TP",
 301                           "I2C4_SCL_TP",
 302                           "I2C5_SDA_HDMI",
 303                           "I2C5_SCL_HDMI",
 304                           "5V_DRV",
 305                           "UART2_RXD",
 306                           "UART2_TXD";
 307 };
 308
 309 &gpio8 {
 310         gpio-line-names = "RAM_ID0",
 311                           "RAM_ID1",
 312                           "RAM_ID2",
 313                           "RAM_ID3",
 314                           "I2C1_SDA_TPM",
 315                           "I2C1_SCL_TPM",
 316                           "SPI2_CLK",
 317                           "SPI2_CS0",
 318
 319                           "SPI2_RXD",
 320                           "SPI2_TXD";
 321 };
 322
 323 &pinctrl {
 324         backlight {
 325                 bl_pwr_en: bl_pwr_en {
 326                         rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
 327                 };
 328         };
 329
 330         buck-5v {
 331                 drv_5v: drv-5v {
 332                         rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 333                 };
 334         };
 335
 336         hdmi {
 337                 vcc50_hdmi_en: vcc50-hdmi-en {
 338                         rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
 339                 };
 340         };
 341
 342         lcd {
 343                 lcd_enable_h: lcd-en {
 344                         rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 345                 };
 346
 347                 avdd_1v8_disp_en: avdd-1v8-disp-en {
 348                         rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 349                 };
 350         };
 351
 352         pmic {
 353                 dvs_1: dvs-1 {
 354                         rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
 355                 };
 356
 357                 dvs_2: dvs-2 {
 358                         rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
 359                 };
 360         };
 361 };