arch/arm/boot/dts/rk322x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 / {
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@f00 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0xf00>;
  68                         resets = <&cru SRST_CORE0>;
  69                         operating-points = <
  70                                 /* KHz    uV */
  71                                  816000 1000000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77
  78                 cpu1: cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                         resets = <&cru SRST_CORE1>;
  83                 };
  84
  85                 cpu2: cpu@f02 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0xf02>;
  89                         resets = <&cru SRST_CORE2>;
  90                 };
  91
  92                 cpu3: cpu@f03 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a7";
  95                         reg = <0xf03>;
  96                         resets = <&cru SRST_CORE3>;
  97                 };
  98         };
  99
 100         amba {
 101                 compatible = "simple-bus";
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 ranges;
 105
 106                 pdma: pdma@110f0000 {
 107                         compatible = "arm,pl330", "arm,primecell";
 108                         reg = <0x110f0000 0x4000>;
 109                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 110                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 111                         #dma-cells = <1>;
 112                         clocks = <&cru ACLK_DMAC>;
 113                         clock-names = "apb_pclk";
 114                 };
 115         };
 116
 117         arm-pmu {
 118                 compatible = "arm,cortex-a7-pmu";
 119                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 123                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv7-timer";
 128                 arm,cpu-registers-not-fw-configured;
 129                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 131                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 132                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 133                 clock-frequency = <24000000>;
 134         };
 135
 136         xin24m: oscillator {
 137                 compatible = "fixed-clock";
 138                 clock-frequency = <24000000>;
 139                 clock-output-names = "xin24m";
 140                 #clock-cells = <0>;
 141         };
 142
 143         i2s1: i2s1@100b0000 {
 144                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 145                 reg = <0x100b0000 0x4000>;
 146                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149                 clock-names = "i2s_clk", "i2s_hclk";
 150                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 151                 dmas = <&pdma 14>, <&pdma 15>;
 152                 dma-names = "tx", "rx";
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&i2s1_bus>;
 155                 status = "disabled";
 156         };
 157
 158         i2s0: i2s0@100c0000 {
 159                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 160                 reg = <0x100c0000 0x4000>;
 161                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 162                 #address-cells = <1>;
 163                 #size-cells = <0>;
 164                 clock-names = "i2s_clk", "i2s_hclk";
 165                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 166                 dmas = <&pdma 11>, <&pdma 12>;
 167                 dma-names = "tx", "rx";
 168                 status = "disabled";
 169         };
 170
 171         i2s2: i2s2@100e0000 {
 172                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 173                 reg = <0x100e0000 0x4000>;
 174                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 175                 #address-cells = <1>;
 176                 #size-cells = <0>;
 177                 clock-names = "i2s_clk", "i2s_hclk";
 178                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 179                 dmas = <&pdma 0>, <&pdma 1>;
 180                 dma-names = "tx", "rx";
 181                 status = "disabled";
 182         };
 183
 184         grf: syscon@11000000 {
 185                 compatible = "syscon";
 186                 reg = <0x11000000 0x1000>;
 187         };
 188
 189         uart0: serial@11010000 {
 190                 compatible = "snps,dw-apb-uart";
 191                 reg = <0x11010000 0x100>;
 192                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 193                 clock-frequency = <24000000>;
 194                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 195                 clock-names = "baudclk", "apb_pclk";
 196                 pinctrl-names = "default";
 197                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 198                 reg-shift = <2>;
 199                 reg-io-width = <4>;
 200                 status = "disabled";
 201         };
 202
 203         uart1: serial@11020000 {
 204                 compatible = "snps,dw-apb-uart";
 205                 reg = <0x11020000 0x100>;
 206                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 207                 clock-frequency = <24000000>;
 208                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 209                 clock-names = "baudclk", "apb_pclk";
 210                 pinctrl-names = "default";
 211                 pinctrl-0 = <&uart1_xfer>;
 212                 reg-shift = <2>;
 213                 reg-io-width = <4>;
 214                 status = "disabled";
 215         };
 216
 217         uart2: serial@11030000 {
 218                 compatible = "snps,dw-apb-uart";
 219                 reg = <0x11030000 0x100>;
 220                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 221                 clock-frequency = <24000000>;
 222                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 223                 clock-names = "baudclk", "apb_pclk";
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&uart2_xfer>;
 226                 reg-shift = <2>;
 227                 reg-io-width = <4>;
 228                 status = "disabled";
 229         };
 230
 231         i2c0: i2c@11050000 {
 232                 compatible = "rockchip,rk3228-i2c";
 233                 reg = <0x11050000 0x1000>;
 234                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 235                 #address-cells = <1>;
 236                 #size-cells = <0>;
 237                 clock-names = "i2c";
 238                 clocks = <&cru PCLK_I2C0>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&i2c0_xfer>;
 241                 status = "disabled";
 242         };
 243
 244         i2c1: i2c@11060000 {
 245                 compatible = "rockchip,rk3228-i2c";
 246                 reg = <0x11060000 0x1000>;
 247                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250                 clock-names = "i2c";
 251                 clocks = <&cru PCLK_I2C1>;
 252                 pinctrl-names = "default";
 253                 pinctrl-0 = <&i2c1_xfer>;
 254                 status = "disabled";
 255         };
 256
 257         i2c2: i2c@11070000 {
 258                 compatible = "rockchip,rk3228-i2c";
 259                 reg = <0x11070000 0x1000>;
 260                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 clock-names = "i2c";
 264                 clocks = <&cru PCLK_I2C2>;
 265                 pinctrl-names = "default";
 266                 pinctrl-0 = <&i2c2_xfer>;
 267                 status = "disabled";
 268         };
 269
 270         i2c3: i2c@11080000 {
 271                 compatible = "rockchip,rk3228-i2c";
 272                 reg = <0x11080000 0x1000>;
 273                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 clock-names = "i2c";
 277                 clocks = <&cru PCLK_I2C3>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&i2c3_xfer>;
 280                 status = "disabled";
 281         };
 282
 283         pwm0: pwm@110b0000 {
 284                 compatible = "rockchip,rk3288-pwm";
 285                 reg = <0x110b0000 0x10>;
 286                 #pwm-cells = <3>;
 287                 clocks = <&cru PCLK_PWM>;
 288                 clock-names = "pwm";
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&pwm0_pin>;
 291                 status = "disabled";
 292         };
 293
 294         pwm1: pwm@110b0010 {
 295                 compatible = "rockchip,rk3288-pwm";
 296                 reg = <0x110b0010 0x10>;
 297                 #pwm-cells = <3>;
 298                 clocks = <&cru PCLK_PWM>;
 299                 clock-names = "pwm";
 300                 pinctrl-names = "default";
 301                 pinctrl-0 = <&pwm1_pin>;
 302                 status = "disabled";
 303         };
 304
 305         pwm2: pwm@110b0020 {
 306                 compatible = "rockchip,rk3288-pwm";
 307                 reg = <0x110b0020 0x10>;
 308                 #pwm-cells = <3>;
 309                 clocks = <&cru PCLK_PWM>;
 310                 clock-names = "pwm";
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&pwm2_pin>;
 313                 status = "disabled";
 314         };
 315
 316         pwm3: pwm@110b0030 {
 317                 compatible = "rockchip,rk3288-pwm";
 318                 reg = <0x110b0030 0x10>;
 319                 #pwm-cells = <2>;
 320                 clocks = <&cru PCLK_PWM>;
 321                 clock-names = "pwm";
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&pwm3_pin>;
 324                 status = "disabled";
 325         };
 326
 327         timer: timer@110c0000 {
 328                 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
 329                 reg = <0x110c0000 0x20>;
 330                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 332                 clock-names = "timer", "pclk";
 333         };
 334
 335         cru: clock-controller@110e0000 {
 336                 compatible = "rockchip,rk3228-cru";
 337                 reg = <0x110e0000 0x1000>;
 338                 rockchip,grf = <&grf>;
 339                 #clock-cells = <1>;
 340                 #reset-cells = <1>;
 341                 assigned-clocks = <&cru PLL_GPLL>;
 342                 assigned-clock-rates = <594000000>;
 343         };
 344
 345         thermal-zones {
 346                 cpu_thermal: cpu-thermal {
 347                         polling-delay-passive = <100>; /* milliseconds */
 348                         polling-delay = <5000>; /* milliseconds */
 349
 350                         thermal-sensors = <&tsadc 0>;
 351
 352                         trips {
 353                                 cpu_alert0: cpu_alert0 {
 354                                         temperature = <70000>; /* millicelsius */
 355                                         hysteresis = <2000>; /* millicelsius */
 356                                         type = "passive";
 357                                 };
 358                                 cpu_alert1: cpu_alert1 {
 359                                         temperature = <75000>; /* millicelsius */
 360                                         hysteresis = <2000>; /* millicelsius */
 361                                         type = "passive";
 362                                 };
 363                                 cpu_crit: cpu_crit {
 364                                         temperature = <90000>; /* millicelsius */
 365                                         hysteresis = <2000>; /* millicelsius */
 366                                         type = "critical";
 367                                 };
 368                         };
 369
 370                         cooling-maps {
 371                                 map0 {
 372                                         trip = <&cpu_alert0>;
 373                                         cooling-device =
 374                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 375                                 };
 376                                 map1 {
 377                                         trip = <&cpu_alert1>;
 378                                         cooling-device =
 379                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 380                                 };
 381                         };
 382                 };
 383         };
 384
 385         tsadc: tsadc@11150000 {
 386                 compatible = "rockchip,rk3228-tsadc";
 387                 reg = <0x11150000 0x100>;
 388                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 390                 clock-names = "tsadc", "apb_pclk";
 391                 resets = <&cru SRST_TSADC>;
 392                 reset-names = "tsadc-apb";
 393                 pinctrl-names = "init", "default", "sleep";
 394                 pinctrl-0 = <&otp_gpio>;
 395                 pinctrl-1 = <&otp_out>;
 396                 pinctrl-2 = <&otp_gpio>;
 397                 #thermal-sensor-cells = <0>;
 398                 rockchip,hw-tshut-temp = <95000>;
 399                 status = "disabled";
 400         };
 401
 402         emmc: dwmmc@30020000 {
 403                 compatible = "rockchip,rk3288-dw-mshc";
 404                 reg = <0x30020000 0x4000>;
 405                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 406                 clock-frequency = <37500000>;
 407                 max-frequency = <37500000>;
 408                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 409                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 410                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 411                 bus-width = <8>;
 412                 default-sample-phase = <158>;
 413                 num-slots = <1>;
 414                 fifo-depth = <0x100>;
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 417                 resets = <&cru SRST_EMMC>;
 418                 reset-names = "reset";
 419                 status = "disabled";
 420         };
 421
 422         gmac: ethernet@30200000 {
 423                 compatible = "rockchip,rk3228-gmac";
 424                 reg = <0x30200000 0x10000>;
 425                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 426                 interrupt-names = "macirq";
 427                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 428                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 429                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 430                         <&cru PCLK_GMAC>;
 431                 clock-names = "stmmaceth", "mac_clk_rx",
 432                         "mac_clk_tx", "clk_mac_ref",
 433                         "clk_mac_refout", "aclk_mac",
 434                         "pclk_mac";
 435                 resets = <&cru SRST_GMAC>;
 436                 reset-names = "stmmaceth";
 437                 rockchip,grf = <&grf>;
 438                 status = "disabled";
 439         };
 440
 441         gic: interrupt-controller@32010000 {
 442                 compatible = "arm,gic-400";
 443                 interrupt-controller;
 444                 #interrupt-cells = <3>;
 445                 #address-cells = <0>;
 446
 447                 reg = <0x32011000 0x1000>,
 448                       <0x32012000 0x2000>,
 449                       <0x32014000 0x2000>,
 450                       <0x32016000 0x2000>;
 451                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 452         };
 453
 454         pinctrl: pinctrl {
 455                 compatible = "rockchip,rk3228-pinctrl";
 456                 rockchip,grf = <&grf>;
 457                 #address-cells = <1>;
 458                 #size-cells = <1>;
 459                 ranges;
 460
 461                 gpio0: gpio0@11110000 {
 462                         compatible = "rockchip,gpio-bank";
 463                         reg = <0x11110000 0x100>;
 464                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 465                         clocks = <&cru PCLK_GPIO0>;
 466
 467                         gpio-controller;
 468                         #gpio-cells = <2>;
 469
 470                         interrupt-controller;
 471                         #interrupt-cells = <2>;
 472                 };
 473
 474                 gpio1: gpio1@11120000 {
 475                         compatible = "rockchip,gpio-bank";
 476                         reg = <0x11120000 0x100>;
 477                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&cru PCLK_GPIO1>;
 479
 480                         gpio-controller;
 481                         #gpio-cells = <2>;
 482
 483                         interrupt-controller;
 484                         #interrupt-cells = <2>;
 485                 };
 486
 487                 gpio2: gpio2@11130000 {
 488                         compatible = "rockchip,gpio-bank";
 489                         reg = <0x11130000 0x100>;
 490                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&cru PCLK_GPIO2>;
 492
 493                         gpio-controller;
 494                         #gpio-cells = <2>;
 495
 496                         interrupt-controller;
 497                         #interrupt-cells = <2>;
 498                 };
 499
 500                 gpio3: gpio3@11140000 {
 501                         compatible = "rockchip,gpio-bank";
 502                         reg = <0x11140000 0x100>;
 503                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&cru PCLK_GPIO3>;
 505
 506                         gpio-controller;
 507                         #gpio-cells = <2>;
 508
 509                         interrupt-controller;
 510                         #interrupt-cells = <2>;
 511                 };
 512
 513                 pcfg_pull_up: pcfg-pull-up {
 514                         bias-pull-up;
 515                 };
 516
 517                 pcfg_pull_down: pcfg-pull-down {
 518                         bias-pull-down;
 519                 };
 520
 521                 pcfg_pull_none: pcfg-pull-none {
 522                         bias-disable;
 523                 };
 524
 525                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 526                         drive-strength = <12>;
 527                 };
 528
 529                 emmc {
 530                         emmc_clk: emmc-clk {
 531                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 532                         };
 533
 534                         emmc_cmd: emmc-cmd {
 535                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 536                         };
 537
 538                         emmc_bus8: emmc-bus8 {
 539                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 540                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 541                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 542                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 543                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 544                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 545                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 546                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 547                         };
 548                 };
 549
 550                 gmac {
 551                         rgmii_pins: rgmii-pins {
 552                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 553                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 554                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 555                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 556                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 557                                                 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 558                                                 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 559                                                 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 560                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 561                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 562                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 563                                                 <2 21 RK_FUNC_2 &pcfg_pull_none>,
 564                                                 <2 20 RK_FUNC_2 &pcfg_pull_none>,
 565                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>,
 566                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>;
 567                         };
 568
 569                         rmii_pins: rmii-pins {
 570                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 571                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 572                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 573                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 574                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 575                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 576                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 577                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 578                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
 579                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>;
 580                         };
 581
 582                         phy_pins: phy-pins {
 583                                 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
 584                                                 <2 8 RK_FUNC_2 &pcfg_pull_none>;
 585                         };
 586                 };
 587
 588                 i2c0 {
 589                         i2c0_xfer: i2c0-xfer {
 590                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 591                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 592                         };
 593                 };
 594
 595                 i2c1 {
 596                         i2c1_xfer: i2c1-xfer {
 597                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 598                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 599                         };
 600                 };
 601
 602                 i2c2 {
 603                         i2c2_xfer: i2c2-xfer {
 604                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 605                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 606                         };
 607                 };
 608
 609                 i2c3 {
 610                         i2c3_xfer: i2c3-xfer {
 611                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 612                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 613                         };
 614                 };
 615
 616                 i2s1 {
 617                         i2s1_bus: i2s1-bus {
 618                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
 619                                                 <0 9 RK_FUNC_1 &pcfg_pull_none>,
 620                                                 <0 11 RK_FUNC_1 &pcfg_pull_none>,
 621                                                 <0 12 RK_FUNC_1 &pcfg_pull_none>,
 622                                                 <0 13 RK_FUNC_1 &pcfg_pull_none>,
 623                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,
 624                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,
 625                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,
 626                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;
 627                         };
 628                 };
 629
 630                 pwm0 {
 631                         pwm0_pin: pwm0-pin {
 632                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
 633                         };
 634                 };
 635
 636                 pwm1 {
 637                         pwm1_pin: pwm1-pin {
 638                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
 639                         };
 640                 };
 641
 642                 pwm2 {
 643                         pwm2_pin: pwm2-pin {
 644                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
 645                         };
 646                 };
 647
 648                 pwm3 {
 649                         pwm3_pin: pwm3-pin {
 650                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
 651                         };
 652                 };
 653
 654                 tsadc {
 655                         otp_gpio: otp-gpio {
 656                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
 657                         };
 658
 659                         otp_out: otp-out {
 660                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
 661                         };
 662                 };
 663
 664                 uart0 {
 665                         uart0_xfer: uart0-xfer {
 666                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
 667                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
 668                         };
 669
 670                         uart0_cts: uart0-cts {
 671                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
 672                         };
 673
 674                         uart0_rts: uart0-rts {
 675                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
 676                         };
 677                 };
 678
 679                 uart1 {
 680                         uart1_xfer: uart1-xfer {
 681                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
 682                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
 683                         };
 684
 685                         uart1_cts: uart1-cts {
 686                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
 687                         };
 688
 689                         uart1_rts: uart1-rts {
 690                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
 691                         };
 692                 };
 693
 694                 uart2 {
 695                         uart2_xfer: uart2-xfer {
 696                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
 697                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 698                         };
 699
 700                         uart2_cts: uart2-cts {
 701                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
 702                         };
 703
 704                         uart2_rts: uart2-rts {
 705                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 706                         };
 707                 };
 708         };
 709 };