arch/arm/boot/dts/rk3228.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         compatible = "rockchip,rk3228";
  50
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57         };
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@f00 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a7";
  66                         reg = <0xf00>;
  67                         resets = <&cru SRST_CORE0>;
  68                         operating-points = <
  69                                 /* KHz    uV */
  70                                  816000 1000000
  71                         >;
  72                         clock-latency = <40000>;
  73                         clocks = <&cru ARMCLK>;
  74                 };
  75
  76                 cpu1: cpu@f01 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf01>;
  80                         resets = <&cru SRST_CORE1>;
  81                 };
  82
  83                 cpu2: cpu@f02 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a7";
  86                         reg = <0xf02>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89
  90                 cpu3: cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                         resets = <&cru SRST_CORE3>;
  95                 };
  96         };
  97
  98         amba {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 pdma: pdma@110f0000 {
 105                         compatible = "arm,pl330", "arm,primecell";
 106                         reg = <0x110f0000 0x4000>;
 107                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 108                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 109                         #dma-cells = <1>;
 110                         clocks = <&cru ACLK_DMAC>;
 111                         clock-names = "apb_pclk";
 112                 };
 113         };
 114
 115         arm-pmu {
 116                 compatible = "arm,cortex-a7-pmu";
 117                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 119                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 121                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 122         };
 123
 124         timer {
 125                 compatible = "arm,armv7-timer";
 126                 arm,cpu-registers-not-fw-configured;
 127                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 131                 clock-frequency = <24000000>;
 132         };
 133
 134         xin24m: oscillator {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <24000000>;
 137                 clock-output-names = "xin24m";
 138                 #clock-cells = <0>;
 139         };
 140
 141         grf: syscon@11000000 {
 142                 compatible = "syscon";
 143                 reg = <0x11000000 0x1000>;
 144         };
 145
 146         uart0: serial@11010000 {
 147                 compatible = "snps,dw-apb-uart";
 148                 reg = <0x11010000 0x100>;
 149                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 150                 clock-frequency = <24000000>;
 151                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 152                 clock-names = "baudclk", "apb_pclk";
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 155                 reg-shift = <2>;
 156                 reg-io-width = <4>;
 157                 status = "disabled";
 158         };
 159
 160         uart1: serial@11020000 {
 161                 compatible = "snps,dw-apb-uart";
 162                 reg = <0x11020000 0x100>;
 163                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 164                 clock-frequency = <24000000>;
 165                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 166                 clock-names = "baudclk", "apb_pclk";
 167                 pinctrl-names = "default";
 168                 pinctrl-0 = <&uart1_xfer>;
 169                 reg-shift = <2>;
 170                 reg-io-width = <4>;
 171                 status = "disabled";
 172         };
 173
 174         uart2: serial@11030000 {
 175                 compatible = "snps,dw-apb-uart";
 176                 reg = <0x11030000 0x100>;
 177                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 178                 clock-frequency = <24000000>;
 179                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 180                 clock-names = "baudclk", "apb_pclk";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&uart2_xfer>;
 183                 reg-shift = <2>;
 184                 reg-io-width = <4>;
 185                 status = "disabled";
 186         };
 187
 188         pwm0: pwm@110b0000 {
 189                 compatible = "rockchip,rk3288-pwm";
 190                 reg = <0x110b0000 0x10>;
 191                 #pwm-cells = <3>;
 192                 clocks = <&cru PCLK_PWM>;
 193                 clock-names = "pwm";
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&pwm0_pin>;
 196                 status = "disabled";
 197         };
 198
 199         pwm1: pwm@110b0010 {
 200                 compatible = "rockchip,rk3288-pwm";
 201                 reg = <0x110b0010 0x10>;
 202                 #pwm-cells = <3>;
 203                 clocks = <&cru PCLK_PWM>;
 204                 clock-names = "pwm";
 205                 pinctrl-names = "default";
 206                 pinctrl-0 = <&pwm1_pin>;
 207                 status = "disabled";
 208         };
 209
 210         pwm2: pwm@110b0020 {
 211                 compatible = "rockchip,rk3288-pwm";
 212                 reg = <0x110b0020 0x10>;
 213                 #pwm-cells = <3>;
 214                 clocks = <&cru PCLK_PWM>;
 215                 clock-names = "pwm";
 216                 pinctrl-names = "default";
 217                 pinctrl-0 = <&pwm2_pin>;
 218                 status = "disabled";
 219         };
 220
 221         pwm3: pwm@110b0030 {
 222                 compatible = "rockchip,rk3288-pwm";
 223                 reg = <0x110b0030 0x10>;
 224                 #pwm-cells = <2>;
 225                 clocks = <&cru PCLK_PWM>;
 226                 clock-names = "pwm";
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&pwm3_pin>;
 229                 status = "disabled";
 230         };
 231
 232         timer: timer@110c0000 {
 233                 compatible = "rockchip,rk3288-timer";
 234                 reg = <0x110c0000 0x20>;
 235                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 237                 clock-names = "timer", "pclk";
 238         };
 239
 240         cru: clock-controller@110e0000 {
 241                 compatible = "rockchip,rk3228-cru";
 242                 reg = <0x110e0000 0x1000>;
 243                 rockchip,grf = <&grf>;
 244                 #clock-cells = <1>;
 245                 #reset-cells = <1>;
 246                 assigned-clocks = <&cru PLL_GPLL>;
 247                 assigned-clock-rates = <594000000>;
 248         };
 249
 250         emmc: dwmmc@30020000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 reg = <0x30020000 0x4000>;
 253                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 254                 clock-frequency = <37500000>;
 255                 clock-freq-min-max = <400000 37500000>;
 256                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 257                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 258                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 259                 bus-width = <8>;
 260                 default-sample-phase = <158>;
 261                 num-slots = <1>;
 262                 fifo-depth = <0x100>;
 263                 pinctrl-names = "default";
 264                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 265                 status = "disabled";
 266         };
 267
 268         gic: interrupt-controller@32010000 {
 269                 compatible = "arm,gic-400";
 270                 interrupt-controller;
 271                 #interrupt-cells = <3>;
 272                 #address-cells = <0>;
 273
 274                 reg = <0x32011000 0x1000>,
 275                       <0x32012000 0x1000>,
 276                       <0x32014000 0x2000>,
 277                       <0x32016000 0x2000>;
 278                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 279         };
 280
 281         pinctrl: pinctrl {
 282                 compatible = "rockchip,rk3228-pinctrl";
 283                 rockchip,grf = <&grf>;
 284                 #address-cells = <1>;
 285                 #size-cells = <1>;
 286                 ranges;
 287
 288                 gpio0: gpio0@11110000 {
 289                         compatible = "rockchip,gpio-bank";
 290                         reg = <0x11110000 0x100>;
 291                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&cru PCLK_GPIO0>;
 293
 294                         gpio-controller;
 295                         #gpio-cells = <2>;
 296
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio1: gpio1@11120000 {
 302                         compatible = "rockchip,gpio-bank";
 303                         reg = <0x11120000 0x100>;
 304                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&cru PCLK_GPIO1>;
 306
 307                         gpio-controller;
 308                         #gpio-cells = <2>;
 309
 310                         interrupt-controller;
 311                         #interrupt-cells = <2>;
 312                 };
 313
 314                 gpio2: gpio2@11130000 {
 315                         compatible = "rockchip,gpio-bank";
 316                         reg = <0x11130000 0x100>;
 317                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&cru PCLK_GPIO2>;
 319
 320                         gpio-controller;
 321                         #gpio-cells = <2>;
 322
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                 };
 326
 327                 gpio3: gpio3@11140000 {
 328                         compatible = "rockchip,gpio-bank";
 329                         reg = <0x11140000 0x100>;
 330                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&cru PCLK_GPIO3>;
 332
 333                         gpio-controller;
 334                         #gpio-cells = <2>;
 335
 336                         interrupt-controller;
 337                         #interrupt-cells = <2>;
 338                 };
 339
 340                 pcfg_pull_up: pcfg-pull-up {
 341                         bias-pull-up;
 342                 };
 343
 344                 pcfg_pull_down: pcfg-pull-down {
 345                         bias-pull-down;
 346                 };
 347
 348                 pcfg_pull_none: pcfg-pull-none {
 349                         bias-disable;
 350                 };
 351
 352                 emmc {
 353                         emmc_clk: emmc-clk {
 354                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 355                         };
 356
 357                         emmc_cmd: emmc-cmd {
 358                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 359                         };
 360
 361                         emmc_bus8: emmc-bus8 {
 362                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 363                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 364                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 365                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 366                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 367                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 368                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 369                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 370                         };
 371                 };
 372
 373                 pwm0 {
 374                         pwm0_pin: pwm0-pin {
 375                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
 376                         };
 377                 };
 378
 379                 pwm1 {
 380                         pwm1_pin: pwm1-pin {
 381                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
 382                         };
 383                 };
 384
 385                 pwm2 {
 386                         pwm2_pin: pwm2-pin {
 387                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
 388                         };
 389                 };
 390
 391                 pwm3 {
 392                         pwm3_pin: pwm3-pin {
 393                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
 394                         };
 395                 };
 396
 397                 uart0 {
 398                         uart0_xfer: uart0-xfer {
 399                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
 400                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
 401                         };
 402
 403                         uart0_cts: uart0-cts {
 404                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
 405                         };
 406
 407                         uart0_rts: uart0-rts {
 408                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
 409                         };
 410                 };
 411
 412                 uart1 {
 413                         uart1_xfer: uart1-xfer {
 414                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
 415                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
 416                         };
 417
 418                         uart1_cts: uart1-cts {
 419                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
 420                         };
 421
 422                         uart1_rts: uart1-rts {
 423                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
 424                         };
 425                 };
 426
 427                 uart2 {
 428                         uart2_xfer: uart2-xfer {
 429                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
 430                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 431                         };
 432
 433                         uart2_cts: uart2-cts {
 434                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
 435                         };
 436
 437                         uart2_rts: uart2-rts {
 438                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 439                         };
 440                 };
 441         };
 442 };