1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include "rk3xxx.dtsi"
13 compatible = "rockchip,rk3188";
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
36 clock-latency = <40000>;
37 clocks = <&cru ARMCLK>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
60 compatible = "rockchip,display-subsystem";
61 ports = <&vop0_out>, <&vop1_out>;
65 compatible = "mmio-sram";
66 reg = <0x10080000 0x8000>;
69 ranges = <0 0x10080000 0x8000>;
72 compatible = "rockchip,rk3066-smp-sram";
78 compatible = "rockchip,rk3188-vop";
79 reg = <0x1010c000 0x1000>;
80 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
82 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
83 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
84 reset-names = "axi", "ahb", "dclk";
94 compatible = "rockchip,rk3188-vop";
95 reg = <0x1010e000 0x1000>;
96 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
98 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
99 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
100 reset-names = "axi", "ahb", "dclk";
104 #address-cells = <1>;
109 timer3: timer@2000e000 {
110 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
111 reg = <0x2000e000 0x20>;
112 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
114 clock-names = "timer", "pclk";
117 timer6: timer@200380a0 {
118 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
119 reg = <0x200380a0 0x20>;
120 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
122 clock-names = "timer", "pclk";
126 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
127 reg = <0x1011a000 0x2000>;
128 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
129 #address-cells = <1>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&i2s0_bus>;
133 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
134 dma-names = "tx", "rx";
135 clock-names = "i2s_hclk", "i2s_clk";
136 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
137 rockchip,playback-channels = <2>;
138 rockchip,capture-channels = <2>;
142 spdif: sound@1011e000 {
143 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
144 reg = <0x1011e000 0x2000>;
145 #sound-dai-cells = <0>;
146 clock-names = "hclk", "mclk";
147 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&spdif_tx>;
156 cru: clock-controller@20000000 {
157 compatible = "rockchip,rk3188-cru";
158 reg = <0x20000000 0x1000>;
159 rockchip,grf = <&grf>;
165 efuse: efuse@20010000 {
166 compatible = "rockchip,rk3188-efuse";
167 reg = <0x20010000 0x4000>;
168 #address-cells = <1>;
170 clocks = <&cru PCLK_EFUSE>;
171 clock-names = "pclk_efuse";
173 cpu_leakage: cpu_leakage@17 {
179 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
180 rockchip,grf = <&grf>;
181 #address-cells = <1>;
185 usbphy0: usb-phy@10c {
188 clocks = <&cru SCLK_OTGPHY0>;
189 clock-names = "phyclk";
193 usbphy1: usb-phy@11c {
196 clocks = <&cru SCLK_OTGPHY1>;
197 clock-names = "phyclk";
203 compatible = "rockchip,rk3188-pinctrl";
204 rockchip,grf = <&grf>;
205 rockchip,pmu = <&pmu>;
207 #address-cells = <1>;
211 gpio0: gpio0@2000a000 {
212 compatible = "rockchip,rk3188-gpio-bank0";
213 reg = <0x2000a000 0x100>;
214 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru PCLK_GPIO0>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
224 gpio1: gpio1@2003c000 {
225 compatible = "rockchip,gpio-bank";
226 reg = <0x2003c000 0x100>;
227 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cru PCLK_GPIO1>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
237 gpio2: gpio2@2003e000 {
238 compatible = "rockchip,gpio-bank";
239 reg = <0x2003e000 0x100>;
240 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cru PCLK_GPIO2>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
250 gpio3: gpio3@20080000 {
251 compatible = "rockchip,gpio-bank";
252 reg = <0x20080000 0x100>;
253 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cru PCLK_GPIO3>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
263 pcfg_pull_up: pcfg_pull_up {
267 pcfg_pull_down: pcfg_pull_down {
271 pcfg_pull_none: pcfg_pull_none {
277 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
281 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
285 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
289 * The data pins are shared between nandc and emmc and
290 * not accessible through pinctrl. Also they should've
291 * been already set correctly by firmware, as
292 * flash/emmc is the boot-device.
297 emac_xfer: emac-xfer {
298 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
299 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
300 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
301 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
302 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
303 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
304 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
305 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
308 emac_mdio: emac-mdio {
309 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
310 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
315 i2c0_xfer: i2c0-xfer {
316 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
317 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
322 i2c1_xfer: i2c1-xfer {
323 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
324 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
329 i2c2_xfer: i2c2-xfer {
330 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
331 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
336 i2c3_xfer: i2c3-xfer {
337 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
338 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
343 i2c4_xfer: i2c4-xfer {
344 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
345 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
350 lcdc1_dclk: lcdc1-dclk {
351 rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
354 lcdc1_den: lcdc1-den {
355 rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
358 lcdc1_hsync: lcdc1-hsync {
359 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
362 lcdc1_vsync: lcdc1-vsync {
363 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
366 lcdc1_rgb24: ldcd1-rgb24 {
367 rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
368 <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
369 <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
370 <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
371 <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
372 <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
373 <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
374 <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
375 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
376 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
377 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
378 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
379 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
380 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
381 <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
382 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
383 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
384 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
385 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
386 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
387 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
388 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
389 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
390 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
396 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
402 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
408 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
414 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
420 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
423 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
426 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
429 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
432 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
438 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
441 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
444 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
447 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
450 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
455 uart0_xfer: uart0-xfer {
456 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
457 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
460 uart0_cts: uart0-cts {
461 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
464 uart0_rts: uart0-rts {
465 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
470 uart1_xfer: uart1-xfer {
471 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
472 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
475 uart1_cts: uart1-cts {
476 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
479 uart1_rts: uart1-rts {
480 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
485 uart2_xfer: uart2-xfer {
486 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
487 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
489 /* no rts / cts for uart2 */
493 uart3_xfer: uart3-xfer {
494 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
495 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
498 uart3_cts: uart3-cts {
499 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
502 uart3_rts: uart3-rts {
503 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
509 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
513 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
517 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
521 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
525 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
528 sd0_bus1: sd0-bus-width1 {
529 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
532 sd0_bus4: sd0-bus-width4 {
533 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
534 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
535 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
536 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
542 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
546 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
550 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
554 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
557 sd1_bus1: sd1-bus-width1 {
558 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
561 sd1_bus4: sd1-bus-width4 {
562 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
563 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
564 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
565 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
571 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
572 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
573 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
574 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
575 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
576 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
582 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
589 compatible = "rockchip,rk3188-emac";
593 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
598 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
602 compatible = "rockchip,rk3188-mali", "arm,mali-400";
603 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "gp",
626 compatible = "rockchip,rk3188-i2c";
627 pinctrl-names = "default";
628 pinctrl-0 = <&i2c0_xfer>;
632 compatible = "rockchip,rk3188-i2c";
633 pinctrl-names = "default";
634 pinctrl-0 = <&i2c1_xfer>;
638 compatible = "rockchip,rk3188-i2c";
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2c2_xfer>;
644 compatible = "rockchip,rk3188-i2c";
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c3_xfer>;
650 compatible = "rockchip,rk3188-i2c";
651 pinctrl-names = "default";
652 pinctrl-0 = <&i2c4_xfer>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm0_out>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pwm1_out>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&pwm2_out>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pwm3_out>;
676 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
677 pinctrl-names = "default";
678 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
682 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
683 pinctrl-names = "default";
684 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
688 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
689 pinctrl-names = "default";
690 pinctrl-0 = <&uart0_xfer>;
694 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
695 pinctrl-names = "default";
696 pinctrl-0 = <&uart1_xfer>;
700 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
701 pinctrl-names = "default";
702 pinctrl-0 = <&uart2_xfer>;
706 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
707 pinctrl-names = "default";
708 pinctrl-0 = <&uart3_xfer>;
712 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";