arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3188-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3188";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1608000 1350000
  65                                 1416000 1250000
  66                                 1200000 1150000
  67                                 1008000 1075000
  68                                  816000  975000
  69                                  600000  950000
  70                                  504000  925000
  71                                  312000  875000
  72                         >;
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76                 cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a9";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x1>;
  81                 };
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a9";
  85                         next-level-cache = <&L2>;
  86                         reg = <0x2>;
  87                 };
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a9";
  91                         next-level-cache = <&L2>;
  92                         reg = <0x3>;
  93                 };
  94         };
  95
  96         sram: sram@10080000 {
  97                 compatible = "mmio-sram";
  98                 reg = <0x10080000 0x8000>;
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges = <0 0x10080000 0x8000>;
 102
 103                 smp-sram@0 {
 104                         compatible = "rockchip,rk3066-smp-sram";
 105                         reg = <0x0 0x50>;
 106                 };
 107         };
 108
 109         timer3: timer@2000e000 {
 110                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 111                 reg = <0x2000e000 0x20>;
 112                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 113                 clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
 114                 clock-names = "timer", "pclk";
 115         };
 116
 117         timer6: timer@200380a0 {
 118                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
 119                 reg = <0x200380a0 0x20>;
 120                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 121                 clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
 122                 clock-names = "timer", "pclk";
 123         };
 124
 125         i2s0: i2s@1011a000 {
 126                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 127                 reg = <0x1011a000 0x2000>;
 128                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&i2s0_bus>;
 133                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 134                 dma-names = "tx", "rx";
 135                 clock-names = "i2s_hclk", "i2s_clk";
 136                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 137                 rockchip,playback-channels = <2>;
 138                 rockchip,capture-channels = <2>;
 139                 status = "disabled";
 140         };
 141
 142         spdif: sound@1011e000 {
 143                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 144                 reg = <0x1011e000 0x2000>;
 145                 #sound-dai-cells = <0>;
 146                 clock-names = "hclk", "mclk";
 147                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
 148                 dmas = <&dmac1_s 8>;
 149                 dma-names = "tx";
 150                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 151                 pinctrl-names = "default";
 152                 pinctrl-0 = <&spdif_tx>;
 153                 status = "disabled";
 154         };
 155
 156         cru: clock-controller@20000000 {
 157                 compatible = "rockchip,rk3188-cru";
 158                 reg = <0x20000000 0x1000>;
 159                 rockchip,grf = <&grf>;
 160
 161                 #clock-cells = <1>;
 162                 #reset-cells = <1>;
 163         };
 164
 165         efuse: efuse@20010000 {
 166                 compatible = "rockchip,rk3188-efuse";
 167                 reg = <0x20010000 0x4000>;
 168                 #address-cells = <1>;
 169                 #size-cells = <1>;
 170                 clocks = <&cru PCLK_EFUSE>;
 171                 clock-names = "pclk_efuse";
 172
 173                 cpu_leakage: cpu_leakage@17 {
 174                         reg = <0x17 0x1>;
 175                 };
 176         };
 177
 178         usbphy: phy {
 179                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 180                 rockchip,grf = <&grf>;
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 status = "disabled";
 184
 185                 usbphy0: usb-phy@10c {
 186                         #phy-cells = <0>;
 187                         reg = <0x10c>;
 188                         clocks = <&cru SCLK_OTGPHY0>;
 189                         clock-names = "phyclk";
 190                         #clock-cells = <0>;
 191                 };
 192
 193                 usbphy1: usb-phy@11c {
 194                         #phy-cells = <0>;
 195                         reg = <0x11c>;
 196                         clocks = <&cru SCLK_OTGPHY1>;
 197                         clock-names = "phyclk";
 198                         #clock-cells = <0>;
 199                 };
 200         };
 201
 202         pinctrl: pinctrl {
 203                 compatible = "rockchip,rk3188-pinctrl";
 204                 rockchip,grf = <&grf>;
 205                 rockchip,pmu = <&pmu>;
 206
 207                 #address-cells = <1>;
 208                 #size-cells = <1>;
 209                 ranges;
 210
 211                 gpio0: gpio0@2000a000 {
 212                         compatible = "rockchip,rk3188-gpio-bank0";
 213                         reg = <0x2000a000 0x100>;
 214                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&cru PCLK_GPIO0>;
 216
 217                         gpio-controller;
 218                         #gpio-cells = <2>;
 219
 220                         interrupt-controller;
 221                         #interrupt-cells = <2>;
 222                 };
 223
 224                 gpio1: gpio1@2003c000 {
 225                         compatible = "rockchip,gpio-bank";
 226                         reg = <0x2003c000 0x100>;
 227                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 228                         clocks = <&cru PCLK_GPIO1>;
 229
 230                         gpio-controller;
 231                         #gpio-cells = <2>;
 232
 233                         interrupt-controller;
 234                         #interrupt-cells = <2>;
 235                 };
 236
 237                 gpio2: gpio2@2003e000 {
 238                         compatible = "rockchip,gpio-bank";
 239                         reg = <0x2003e000 0x100>;
 240                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&cru PCLK_GPIO2>;
 242
 243                         gpio-controller;
 244                         #gpio-cells = <2>;
 245
 246                         interrupt-controller;
 247                         #interrupt-cells = <2>;
 248                 };
 249
 250                 gpio3: gpio3@20080000 {
 251                         compatible = "rockchip,gpio-bank";
 252                         reg = <0x20080000 0x100>;
 253                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&cru PCLK_GPIO3>;
 255
 256                         gpio-controller;
 257                         #gpio-cells = <2>;
 258
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                 };
 262
 263                 pcfg_pull_up: pcfg_pull_up {
 264                         bias-pull-up;
 265                 };
 266
 267                 pcfg_pull_down: pcfg_pull_down {
 268                         bias-pull-down;
 269                 };
 270
 271                 pcfg_pull_none: pcfg_pull_none {
 272                         bias-disable;
 273                 };
 274
 275                 emmc {
 276                         emmc_clk: emmc-clk {
 277                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 278                         };
 279
 280                         emmc_cmd: emmc-cmd {
 281                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 282                         };
 283
 284                         emmc_rst: emmc-rst {
 285                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 286                         };
 287
 288                         /*
 289                          * The data pins are shared between nandc and emmc and
 290                          * not accessible through pinctrl. Also they should've
 291                          * been already set correctly by firmware, as
 292                          * flash/emmc is the boot-device.
 293                          */
 294                 };
 295
 296                 emac {
 297                         emac_xfer: emac-xfer {
 298                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 299                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 300                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 301                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 302                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 303                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 304                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 305                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 306                         };
 307
 308                         emac_mdio: emac-mdio {
 309                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 310                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 311                         };
 312                 };
 313
 314                 i2c0 {
 315                         i2c0_xfer: i2c0-xfer {
 316                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 317                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 318                         };
 319                 };
 320
 321                 i2c1 {
 322                         i2c1_xfer: i2c1-xfer {
 323                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 324                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 325                         };
 326                 };
 327
 328                 i2c2 {
 329                         i2c2_xfer: i2c2-xfer {
 330                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 331                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 332                         };
 333                 };
 334
 335                 i2c3 {
 336                         i2c3_xfer: i2c3-xfer {
 337                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 338                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 339                         };
 340                 };
 341
 342                 i2c4 {
 343                         i2c4_xfer: i2c4-xfer {
 344                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 345                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 346                         };
 347                 };
 348
 349                 pwm0 {
 350                         pwm0_out: pwm0-out {
 351                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 352                         };
 353                 };
 354
 355                 pwm1 {
 356                         pwm1_out: pwm1-out {
 357                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 358                         };
 359                 };
 360
 361                 pwm2 {
 362                         pwm2_out: pwm2-out {
 363                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 364                         };
 365                 };
 366
 367                 pwm3 {
 368                         pwm3_out: pwm3-out {
 369                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 370                         };
 371                 };
 372
 373                 spi0 {
 374                         spi0_clk: spi0-clk {
 375                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 376                         };
 377                         spi0_cs0: spi0-cs0 {
 378                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 379                         };
 380                         spi0_tx: spi0-tx {
 381                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 382                         };
 383                         spi0_rx: spi0-rx {
 384                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 385                         };
 386                         spi0_cs1: spi0-cs1 {
 387                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 388                         };
 389                 };
 390
 391                 spi1 {
 392                         spi1_clk: spi1-clk {
 393                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 394                         };
 395                         spi1_cs0: spi1-cs0 {
 396                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 397                         };
 398                         spi1_rx: spi1-rx {
 399                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 400                         };
 401                         spi1_tx: spi1-tx {
 402                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 403                         };
 404                         spi1_cs1: spi1-cs1 {
 405                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 406                         };
 407                 };
 408
 409                 uart0 {
 410                         uart0_xfer: uart0-xfer {
 411                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 412                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 413                         };
 414
 415                         uart0_cts: uart0-cts {
 416                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 417                         };
 418
 419                         uart0_rts: uart0-rts {
 420                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 421                         };
 422                 };
 423
 424                 uart1 {
 425                         uart1_xfer: uart1-xfer {
 426                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 427                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 428                         };
 429
 430                         uart1_cts: uart1-cts {
 431                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 432                         };
 433
 434                         uart1_rts: uart1-rts {
 435                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 436                         };
 437                 };
 438
 439                 uart2 {
 440                         uart2_xfer: uart2-xfer {
 441                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 442                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 443                         };
 444                         /* no rts / cts for uart2 */
 445                 };
 446
 447                 uart3 {
 448                         uart3_xfer: uart3-xfer {
 449                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 450                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 451                         };
 452
 453                         uart3_cts: uart3-cts {
 454                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 455                         };
 456
 457                         uart3_rts: uart3-rts {
 458                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 459                         };
 460                 };
 461
 462                 sd0 {
 463                         sd0_clk: sd0-clk {
 464                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 465                         };
 466
 467                         sd0_cmd: sd0-cmd {
 468                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 469                         };
 470
 471                         sd0_cd: sd0-cd {
 472                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 473                         };
 474
 475                         sd0_wp: sd0-wp {
 476                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 477                         };
 478
 479                         sd0_pwr: sd0-pwr {
 480                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 481                         };
 482
 483                         sd0_bus1: sd0-bus-width1 {
 484                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 485                         };
 486
 487                         sd0_bus4: sd0-bus-width4 {
 488                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 489                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 490                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 491                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 492                         };
 493                 };
 494
 495                 sd1 {
 496                         sd1_clk: sd1-clk {
 497                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 498                         };
 499
 500                         sd1_cmd: sd1-cmd {
 501                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 502                         };
 503
 504                         sd1_cd: sd1-cd {
 505                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 506                         };
 507
 508                         sd1_wp: sd1-wp {
 509                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 510                         };
 511
 512                         sd1_bus1: sd1-bus-width1 {
 513                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 514                         };
 515
 516                         sd1_bus4: sd1-bus-width4 {
 517                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 518                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 519                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 520                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 521                         };
 522                 };
 523
 524                 i2s0 {
 525                         i2s0_bus: i2s0-bus {
 526                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 527                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 528                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 529                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 530                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 531                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 532                         };
 533                 };
 534
 535                 spdif {
 536                         spdif_tx: spdif-tx {
 537                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 538                         };
 539                 };
 540         };
 541 };
 542
 543 &emac {
 544         compatible = "rockchip,rk3188-emac";
 545 };
 546
 547 &global_timer {
 548         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 549         status = "disabled";
 550 };
 551
 552 &local_timer {
 553         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 554 };
 555
 556 &gpu {
 557         compatible = "rockchip,rk3188-mali", "arm,mali-400";
 558         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 559                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 560                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 561                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 562                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 563                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 564                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 565                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 566                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 567                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 568         interrupt-names = "gp",
 569                           "gpmmu",
 570                           "pp0",
 571                           "ppmmu0",
 572                           "pp1",
 573                           "ppmmu1",
 574                           "pp2",
 575                           "ppmmu2",
 576                           "pp3",
 577                           "ppmmu3";
 578 };
 579
 580 &i2c0 {
 581         compatible = "rockchip,rk3188-i2c";
 582         pinctrl-names = "default";
 583         pinctrl-0 = <&i2c0_xfer>;
 584 };
 585
 586 &i2c1 {
 587         compatible = "rockchip,rk3188-i2c";
 588         pinctrl-names = "default";
 589         pinctrl-0 = <&i2c1_xfer>;
 590 };
 591
 592 &i2c2 {
 593         compatible = "rockchip,rk3188-i2c";
 594         pinctrl-names = "default";
 595         pinctrl-0 = <&i2c2_xfer>;
 596 };
 597
 598 &i2c3 {
 599         compatible = "rockchip,rk3188-i2c";
 600         pinctrl-names = "default";
 601         pinctrl-0 = <&i2c3_xfer>;
 602 };
 603
 604 &i2c4 {
 605         compatible = "rockchip,rk3188-i2c";
 606         pinctrl-names = "default";
 607         pinctrl-0 = <&i2c4_xfer>;
 608 };
 609
 610 &pwm0 {
 611         pinctrl-names = "default";
 612         pinctrl-0 = <&pwm0_out>;
 613 };
 614
 615 &pwm1 {
 616         pinctrl-names = "default";
 617         pinctrl-0 = <&pwm1_out>;
 618 };
 619
 620 &pwm2 {
 621         pinctrl-names = "default";
 622         pinctrl-0 = <&pwm2_out>;
 623 };
 624
 625 &pwm3 {
 626         pinctrl-names = "default";
 627         pinctrl-0 = <&pwm3_out>;
 628 };
 629
 630 &spi0 {
 631         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 634 };
 635
 636 &spi1 {
 637         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 638         pinctrl-names = "default";
 639         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 640 };
 641
 642 &uart0 {
 643         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 644         pinctrl-names = "default";
 645         pinctrl-0 = <&uart0_xfer>;
 646 };
 647
 648 &uart1 {
 649         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 650         pinctrl-names = "default";
 651         pinctrl-0 = <&uart1_xfer>;
 652 };
 653
 654 &uart2 {
 655         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 656         pinctrl-names = "default";
 657         pinctrl-0 = <&uart2_xfer>;
 658 };
 659
 660 &uart3 {
 661         compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&uart3_xfer>;
 664 };
 665
 666 &wdt {
 667         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 668 };