arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3188-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3188";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1608000 1350000
  65                                 1416000 1250000
  66                                 1200000 1150000
  67                                 1008000 1075000
  68                                  816000  975000
  69                                  600000  950000
  70                                  504000  925000
  71                                  312000  875000
  72                         >;
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76                 cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a9";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x1>;
  81                 };
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a9";
  85                         next-level-cache = <&L2>;
  86                         reg = <0x2>;
  87                 };
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a9";
  91                         next-level-cache = <&L2>;
  92                         reg = <0x3>;
  93                 };
  94         };
  95
  96         sram: sram@10080000 {
  97                 compatible = "mmio-sram";
  98                 reg = <0x10080000 0x8000>;
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges = <0 0x10080000 0x8000>;
 102
 103                 smp-sram@0 {
 104                         compatible = "rockchip,rk3066-smp-sram";
 105                         reg = <0x0 0x50>;
 106                 };
 107         };
 108
 109         i2s0: i2s@1011a000 {
 110                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 111                 reg = <0x1011a000 0x2000>;
 112                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&i2s0_bus>;
 117                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 118                 dma-names = "tx", "rx";
 119                 clock-names = "i2s_hclk", "i2s_clk";
 120                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 121                 rockchip,playback-channels = <2>;
 122                 rockchip,capture-channels = <2>;
 123                 status = "disabled";
 124         };
 125
 126         spdif: sound@1011e000 {
 127                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 128                 reg = <0x1011e000 0x2000>;
 129                 #sound-dai-cells = <0>;
 130                 clock-names = "hclk", "mclk";
 131                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
 132                 dmas = <&dmac1_s 8>;
 133                 dma-names = "tx";
 134                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 135                 pinctrl-names = "default";
 136                 pinctrl-0 = <&spdif_tx>;
 137                 status = "disabled";
 138         };
 139
 140         cru: clock-controller@20000000 {
 141                 compatible = "rockchip,rk3188-cru";
 142                 reg = <0x20000000 0x1000>;
 143                 rockchip,grf = <&grf>;
 144
 145                 #clock-cells = <1>;
 146                 #reset-cells = <1>;
 147         };
 148
 149         efuse: efuse@20010000 {
 150                 compatible = "rockchip,rockchip-efuse";
 151                 reg = <0x20010000 0x4000>;
 152                 #address-cells = <1>;
 153                 #size-cells = <1>;
 154                 clocks = <&cru PCLK_EFUSE>;
 155                 clock-names = "pclk_efuse";
 156
 157                 cpu_leakage: cpu_leakage@17 {
 158                         reg = <0x17 0x1>;
 159                 };
 160         };
 161
 162         usbphy: phy {
 163                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 164                 rockchip,grf = <&grf>;
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 status = "disabled";
 168
 169                 usbphy0: usb-phy@10c {
 170                         #phy-cells = <0>;
 171                         reg = <0x10c>;
 172                         clocks = <&cru SCLK_OTGPHY0>;
 173                         clock-names = "phyclk";
 174                         #clock-cells = <0>;
 175                 };
 176
 177                 usbphy1: usb-phy@11c {
 178                         #phy-cells = <0>;
 179                         reg = <0x11c>;
 180                         clocks = <&cru SCLK_OTGPHY1>;
 181                         clock-names = "phyclk";
 182                         #clock-cells = <0>;
 183                 };
 184         };
 185
 186         pinctrl: pinctrl {
 187                 compatible = "rockchip,rk3188-pinctrl";
 188                 rockchip,grf = <&grf>;
 189                 rockchip,pmu = <&pmu>;
 190
 191                 #address-cells = <1>;
 192                 #size-cells = <1>;
 193                 ranges;
 194
 195                 gpio0: gpio0@2000a000 {
 196                         compatible = "rockchip,rk3188-gpio-bank0";
 197                         reg = <0x2000a000 0x100>;
 198                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 199                         clocks = <&cru PCLK_GPIO0>;
 200
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203
 204                         interrupt-controller;
 205                         #interrupt-cells = <2>;
 206                 };
 207
 208                 gpio1: gpio1@2003c000 {
 209                         compatible = "rockchip,gpio-bank";
 210                         reg = <0x2003c000 0x100>;
 211                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&cru PCLK_GPIO1>;
 213
 214                         gpio-controller;
 215                         #gpio-cells = <2>;
 216
 217                         interrupt-controller;
 218                         #interrupt-cells = <2>;
 219                 };
 220
 221                 gpio2: gpio2@2003e000 {
 222                         compatible = "rockchip,gpio-bank";
 223                         reg = <0x2003e000 0x100>;
 224                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&cru PCLK_GPIO2>;
 226
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229
 230                         interrupt-controller;
 231                         #interrupt-cells = <2>;
 232                 };
 233
 234                 gpio3: gpio3@20080000 {
 235                         compatible = "rockchip,gpio-bank";
 236                         reg = <0x20080000 0x100>;
 237                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&cru PCLK_GPIO3>;
 239
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242
 243                         interrupt-controller;
 244                         #interrupt-cells = <2>;
 245                 };
 246
 247                 pcfg_pull_up: pcfg_pull_up {
 248                         bias-pull-up;
 249                 };
 250
 251                 pcfg_pull_down: pcfg_pull_down {
 252                         bias-pull-down;
 253                 };
 254
 255                 pcfg_pull_none: pcfg_pull_none {
 256                         bias-disable;
 257                 };
 258
 259                 emmc {
 260                         emmc_clk: emmc-clk {
 261                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 262                         };
 263
 264                         emmc_cmd: emmc-cmd {
 265                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 266                         };
 267
 268                         emmc_rst: emmc-rst {
 269                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 270                         };
 271
 272                         /*
 273                          * The data pins are shared between nandc and emmc and
 274                          * not accessible through pinctrl. Also they should've
 275                          * been already set correctly by firmware, as
 276                          * flash/emmc is the boot-device.
 277                          */
 278                 };
 279
 280                 emac {
 281                         emac_xfer: emac-xfer {
 282                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 283                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 284                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 285                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 286                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 287                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 288                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 289                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 290                         };
 291
 292                         emac_mdio: emac-mdio {
 293                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 294                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 295                         };
 296                 };
 297
 298                 i2c0 {
 299                         i2c0_xfer: i2c0-xfer {
 300                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 301                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 302                         };
 303                 };
 304
 305                 i2c1 {
 306                         i2c1_xfer: i2c1-xfer {
 307                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 308                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 309                         };
 310                 };
 311
 312                 i2c2 {
 313                         i2c2_xfer: i2c2-xfer {
 314                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 315                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 316                         };
 317                 };
 318
 319                 i2c3 {
 320                         i2c3_xfer: i2c3-xfer {
 321                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 322                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 323                         };
 324                 };
 325
 326                 i2c4 {
 327                         i2c4_xfer: i2c4-xfer {
 328                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 329                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 330                         };
 331                 };
 332
 333                 pwm0 {
 334                         pwm0_out: pwm0-out {
 335                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 336                         };
 337                 };
 338
 339                 pwm1 {
 340                         pwm1_out: pwm1-out {
 341                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 342                         };
 343                 };
 344
 345                 pwm2 {
 346                         pwm2_out: pwm2-out {
 347                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 348                         };
 349                 };
 350
 351                 pwm3 {
 352                         pwm3_out: pwm3-out {
 353                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 354                         };
 355                 };
 356
 357                 spi0 {
 358                         spi0_clk: spi0-clk {
 359                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 360                         };
 361                         spi0_cs0: spi0-cs0 {
 362                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 363                         };
 364                         spi0_tx: spi0-tx {
 365                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 366                         };
 367                         spi0_rx: spi0-rx {
 368                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 369                         };
 370                         spi0_cs1: spi0-cs1 {
 371                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 372                         };
 373                 };
 374
 375                 spi1 {
 376                         spi1_clk: spi1-clk {
 377                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 378                         };
 379                         spi1_cs0: spi1-cs0 {
 380                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 381                         };
 382                         spi1_rx: spi1-rx {
 383                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 384                         };
 385                         spi1_tx: spi1-tx {
 386                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 387                         };
 388                         spi1_cs1: spi1-cs1 {
 389                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 390                         };
 391                 };
 392
 393                 uart0 {
 394                         uart0_xfer: uart0-xfer {
 395                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 396                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 397                         };
 398
 399                         uart0_cts: uart0-cts {
 400                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 401                         };
 402
 403                         uart0_rts: uart0-rts {
 404                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 405                         };
 406                 };
 407
 408                 uart1 {
 409                         uart1_xfer: uart1-xfer {
 410                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 411                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 412                         };
 413
 414                         uart1_cts: uart1-cts {
 415                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 416                         };
 417
 418                         uart1_rts: uart1-rts {
 419                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 420                         };
 421                 };
 422
 423                 uart2 {
 424                         uart2_xfer: uart2-xfer {
 425                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 426                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 427                         };
 428                         /* no rts / cts for uart2 */
 429                 };
 430
 431                 uart3 {
 432                         uart3_xfer: uart3-xfer {
 433                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 434                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 435                         };
 436
 437                         uart3_cts: uart3-cts {
 438                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 439                         };
 440
 441                         uart3_rts: uart3-rts {
 442                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 443                         };
 444                 };
 445
 446                 sd0 {
 447                         sd0_clk: sd0-clk {
 448                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 449                         };
 450
 451                         sd0_cmd: sd0-cmd {
 452                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 453                         };
 454
 455                         sd0_cd: sd0-cd {
 456                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 457                         };
 458
 459                         sd0_wp: sd0-wp {
 460                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 461                         };
 462
 463                         sd0_pwr: sd0-pwr {
 464                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 465                         };
 466
 467                         sd0_bus1: sd0-bus-width1 {
 468                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 469                         };
 470
 471                         sd0_bus4: sd0-bus-width4 {
 472                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 473                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 474                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 475                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 476                         };
 477                 };
 478
 479                 sd1 {
 480                         sd1_clk: sd1-clk {
 481                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 482                         };
 483
 484                         sd1_cmd: sd1-cmd {
 485                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 486                         };
 487
 488                         sd1_cd: sd1-cd {
 489                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 490                         };
 491
 492                         sd1_wp: sd1-wp {
 493                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 494                         };
 495
 496                         sd1_bus1: sd1-bus-width1 {
 497                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 498                         };
 499
 500                         sd1_bus4: sd1-bus-width4 {
 501                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 502                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 503                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 504                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 505                         };
 506                 };
 507
 508                 i2s0 {
 509                         i2s0_bus: i2s0-bus {
 510                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 511                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 512                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 513                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 514                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 515                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 516                         };
 517                 };
 518
 519                 spdif {
 520                         spdif_tx: spdif-tx {
 521                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 522                         };
 523                 };
 524         };
 525 };
 526
 527 &emac {
 528         compatible = "rockchip,rk3188-emac";
 529 };
 530
 531 &global_timer {
 532         interrupts = <GIC_PPI 11 0xf04>;
 533 };
 534
 535 &local_timer {
 536         interrupts = <GIC_PPI 13 0xf04>;
 537 };
 538
 539 &i2c0 {
 540         compatible = "rockchip,rk3188-i2c";
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&i2c0_xfer>;
 543 };
 544
 545 &i2c1 {
 546         compatible = "rockchip,rk3188-i2c";
 547         pinctrl-names = "default";
 548         pinctrl-0 = <&i2c1_xfer>;
 549 };
 550
 551 &i2c2 {
 552         compatible = "rockchip,rk3188-i2c";
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&i2c2_xfer>;
 555 };
 556
 557 &i2c3 {
 558         compatible = "rockchip,rk3188-i2c";
 559         pinctrl-names = "default";
 560         pinctrl-0 = <&i2c3_xfer>;
 561 };
 562
 563 &i2c4 {
 564         compatible = "rockchip,rk3188-i2c";
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&i2c4_xfer>;
 567 };
 568
 569 &pwm0 {
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&pwm0_out>;
 572 };
 573
 574 &pwm1 {
 575         pinctrl-names = "default";
 576         pinctrl-0 = <&pwm1_out>;
 577 };
 578
 579 &pwm2 {
 580         pinctrl-names = "default";
 581         pinctrl-0 = <&pwm2_out>;
 582 };
 583
 584 &pwm3 {
 585         pinctrl-names = "default";
 586         pinctrl-0 = <&pwm3_out>;
 587 };
 588
 589 &spi0 {
 590         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 593 };
 594
 595 &spi1 {
 596         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 599 };
 600
 601 &uart0 {
 602         pinctrl-names = "default";
 603         pinctrl-0 = <&uart0_xfer>;
 604 };
 605
 606 &uart1 {
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&uart1_xfer>;
 609 };
 610
 611 &uart2 {
 612         pinctrl-names = "default";
 613         pinctrl-0 = <&uart2_xfer>;
 614 };
 615
 616 &uart3 {
 617         pinctrl-names = "default";
 618         pinctrl-0 = <&uart3_xfer>;
 619 };
 620
 621 &wdt {
 622         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 623 };