arch/arm/boot/dts/rk3066a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/pinctrl/rockchip.h>
   9 #include <dt-bindings/clock/rk3066a-cru.h>
  10 #include <dt-bindings/power/rk3066-power.h>
  11 #include "rk3xxx.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3066a";
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19                 enable-method = "rockchip,rk3066-smp";
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x0>;
  26                         operating-points = <
  27                                 /* kHz    uV */
  28                                 1416000 1300000
  29                                 1200000 1175000
  30                                 1008000 1125000
  31                                 816000  1125000
  32                                 600000  1100000
  33                                 504000  1100000
  34                                 312000  1075000
  35                         >;
  36                         clock-latency = <40000>;
  37                         clocks = <&cru ARMCLK>;
  38                 };
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         next-level-cache = <&L2>;
  43                         reg = <0x1>;
  44                 };
  45         };
  46
  47         display-subsystem {
  48                 compatible = "rockchip,display-subsystem";
  49                 ports = <&vop0_out>, <&vop1_out>;
  50         };
  51
  52         sram: sram@10080000 {
  53                 compatible = "mmio-sram";
  54                 reg = <0x10080000 0x10000>;
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges = <0 0x10080000 0x10000>;
  58
  59                 smp-sram@0 {
  60                         compatible = "rockchip,rk3066-smp-sram";
  61                         reg = <0x0 0x50>;
  62                 };
  63         };
  64
  65         vop0: vop@1010c000 {
  66                 compatible = "rockchip,rk3066-vop";
  67                 reg = <0x1010c000 0x19c>;
  68                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  69                 clocks = <&cru ACLK_LCDC0>,
  70                          <&cru DCLK_LCDC0>,
  71                          <&cru HCLK_LCDC0>;
  72                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  73                 power-domains = <&power RK3066_PD_VIO>;
  74                 resets = <&cru SRST_LCDC0_AXI>,
  75                          <&cru SRST_LCDC0_AHB>,
  76                          <&cru SRST_LCDC0_DCLK>;
  77                 reset-names = "axi", "ahb", "dclk";
  78                 status = "disabled";
  79
  80                 vop0_out: port {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83                 };
  84         };
  85
  86         vop1: vop@1010e000 {
  87                 compatible = "rockchip,rk3066-vop";
  88                 reg = <0x1010e000 0x19c>;
  89                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  90                 clocks = <&cru ACLK_LCDC1>,
  91                          <&cru DCLK_LCDC1>,
  92                          <&cru HCLK_LCDC1>;
  93                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  94                 power-domains = <&power RK3066_PD_VIO>;
  95                 resets = <&cru SRST_LCDC1_AXI>,
  96                          <&cru SRST_LCDC1_AHB>,
  97                          <&cru SRST_LCDC1_DCLK>;
  98                 reset-names = "axi", "ahb", "dclk";
  99                 status = "disabled";
 100
 101                 vop1_out: port {
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                 };
 105         };
 106
 107         i2s0: i2s@10118000 {
 108                 compatible = "rockchip,rk3066-i2s";
 109                 reg = <0x10118000 0x2000>;
 110                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&i2s0_bus>;
 115                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
 116                 dma-names = "tx", "rx";
 117                 clock-names = "i2s_hclk", "i2s_clk";
 118                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 119                 rockchip,playback-channels = <8>;
 120                 rockchip,capture-channels = <2>;
 121                 #sound-dai-cells = <0>;
 122                 status = "disabled";
 123         };
 124
 125         i2s1: i2s@1011a000 {
 126                 compatible = "rockchip,rk3066-i2s";
 127                 reg = <0x1011a000 0x2000>;
 128                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&i2s1_bus>;
 133                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 134                 dma-names = "tx", "rx";
 135                 clock-names = "i2s_hclk", "i2s_clk";
 136                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
 137                 rockchip,playback-channels = <2>;
 138                 rockchip,capture-channels = <2>;
 139                 #sound-dai-cells = <0>;
 140                 status = "disabled";
 141         };
 142
 143         i2s2: i2s@1011c000 {
 144                 compatible = "rockchip,rk3066-i2s";
 145                 reg = <0x1011c000 0x2000>;
 146                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149                 pinctrl-names = "default";
 150                 pinctrl-0 = <&i2s2_bus>;
 151                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 152                 dma-names = "tx", "rx";
 153                 clock-names = "i2s_hclk", "i2s_clk";
 154                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 155                 rockchip,playback-channels = <2>;
 156                 rockchip,capture-channels = <2>;
 157                 #sound-dai-cells = <0>;
 158                 status = "disabled";
 159         };
 160
 161         cru: clock-controller@20000000 {
 162                 compatible = "rockchip,rk3066a-cru";
 163                 reg = <0x20000000 0x1000>;
 164                 rockchip,grf = <&grf>;
 165
 166                 #clock-cells = <1>;
 167                 #reset-cells = <1>;
 168                 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 169                                   <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 170                                   <&cru PCLK_CPU>, <&cru ACLK_PERI>,
 171                                   <&cru HCLK_PERI>, <&cru PCLK_PERI>;
 172                 assigned-clock-rates = <400000000>, <594000000>,
 173                                        <300000000>, <150000000>,
 174                                        <75000000>, <300000000>,
 175                                        <150000000>, <75000000>;
 176         };
 177
 178         timer@2000e000 {
 179                 compatible = "snps,dw-apb-timer-osc";
 180                 reg = <0x2000e000 0x100>;
 181                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 183                 clock-names = "timer", "pclk";
 184         };
 185
 186         efuse: efuse@20010000 {
 187                 compatible = "rockchip,rk3066a-efuse";
 188                 reg = <0x20010000 0x4000>;
 189                 #address-cells = <1>;
 190                 #size-cells = <1>;
 191                 clocks = <&cru PCLK_EFUSE>;
 192                 clock-names = "pclk_efuse";
 193
 194                 cpu_leakage: cpu_leakage@17 {
 195                         reg = <0x17 0x1>;
 196                 };
 197         };
 198
 199         timer@20038000 {
 200                 compatible = "snps,dw-apb-timer-osc";
 201                 reg = <0x20038000 0x100>;
 202                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 204                 clock-names = "timer", "pclk";
 205         };
 206
 207         timer@2003a000 {
 208                 compatible = "snps,dw-apb-timer-osc";
 209                 reg = <0x2003a000 0x100>;
 210                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 212                 clock-names = "timer", "pclk";
 213         };
 214
 215         tsadc: tsadc@20060000 {
 216                 compatible = "rockchip,rk3066-tsadc";
 217                 reg = <0x20060000 0x100>;
 218                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 219                 clock-names = "saradc", "apb_pclk";
 220                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 221                 #io-channel-cells = <1>;
 222                 resets = <&cru SRST_TSADC>;
 223                 reset-names = "saradc-apb";
 224                 status = "disabled";
 225         };
 226
 227         usbphy: phy {
 228                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 229                 rockchip,grf = <&grf>;
 230                 #address-cells = <1>;
 231                 #size-cells = <0>;
 232                 status = "disabled";
 233
 234                 usbphy0: usb-phy@17c {
 235                         #phy-cells = <0>;
 236                         reg = <0x17c>;
 237                         clocks = <&cru SCLK_OTGPHY0>;
 238                         clock-names = "phyclk";
 239                         #clock-cells = <0>;
 240                 };
 241
 242                 usbphy1: usb-phy@188 {
 243                         #phy-cells = <0>;
 244                         reg = <0x188>;
 245                         clocks = <&cru SCLK_OTGPHY1>;
 246                         clock-names = "phyclk";
 247                         #clock-cells = <0>;
 248                 };
 249         };
 250
 251         pinctrl: pinctrl {
 252                 compatible = "rockchip,rk3066a-pinctrl";
 253                 rockchip,grf = <&grf>;
 254                 #address-cells = <1>;
 255                 #size-cells = <1>;
 256                 ranges;
 257
 258                 gpio0: gpio0@20034000 {
 259                         compatible = "rockchip,gpio-bank";
 260                         reg = <0x20034000 0x100>;
 261                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&cru PCLK_GPIO0>;
 263
 264                         gpio-controller;
 265                         #gpio-cells = <2>;
 266
 267                         interrupt-controller;
 268                         #interrupt-cells = <2>;
 269                 };
 270
 271                 gpio1: gpio1@2003c000 {
 272                         compatible = "rockchip,gpio-bank";
 273                         reg = <0x2003c000 0x100>;
 274                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&cru PCLK_GPIO1>;
 276
 277                         gpio-controller;
 278                         #gpio-cells = <2>;
 279
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                 };
 283
 284                 gpio2: gpio2@2003e000 {
 285                         compatible = "rockchip,gpio-bank";
 286                         reg = <0x2003e000 0x100>;
 287                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&cru PCLK_GPIO2>;
 289
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292
 293                         interrupt-controller;
 294                         #interrupt-cells = <2>;
 295                 };
 296
 297                 gpio3: gpio3@20080000 {
 298                         compatible = "rockchip,gpio-bank";
 299                         reg = <0x20080000 0x100>;
 300                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&cru PCLK_GPIO3>;
 302
 303                         gpio-controller;
 304                         #gpio-cells = <2>;
 305
 306                         interrupt-controller;
 307                         #interrupt-cells = <2>;
 308                 };
 309
 310                 gpio4: gpio4@20084000 {
 311                         compatible = "rockchip,gpio-bank";
 312                         reg = <0x20084000 0x100>;
 313                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&cru PCLK_GPIO4>;
 315
 316                         gpio-controller;
 317                         #gpio-cells = <2>;
 318
 319                         interrupt-controller;
 320                         #interrupt-cells = <2>;
 321                 };
 322
 323                 gpio6: gpio6@2000a000 {
 324                         compatible = "rockchip,gpio-bank";
 325                         reg = <0x2000a000 0x100>;
 326                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&cru PCLK_GPIO6>;
 328
 329                         gpio-controller;
 330                         #gpio-cells = <2>;
 331
 332                         interrupt-controller;
 333                         #interrupt-cells = <2>;
 334                 };
 335
 336                 pcfg_pull_default: pcfg_pull_default {
 337                         bias-pull-pin-default;
 338                 };
 339
 340                 pcfg_pull_none: pcfg_pull_none {
 341                         bias-disable;
 342                 };
 343
 344                 emac {
 345                         emac_xfer: emac-xfer {
 346                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 347                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 348                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 349                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 350                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 351                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 352                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 353                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 354                         };
 355
 356                         emac_mdio: emac-mdio {
 357                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 358                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 359                         };
 360                 };
 361
 362                 emmc {
 363                         emmc_clk: emmc-clk {
 364                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 365                         };
 366
 367                         emmc_cmd: emmc-cmd {
 368                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 369                         };
 370
 371                         emmc_rst: emmc-rst {
 372                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 373                         };
 374
 375                         /*
 376                          * The data pins are shared between nandc and emmc and
 377                          * not accessible through pinctrl. Also they should've
 378                          * been already set correctly by firmware, as
 379                          * flash/emmc is the boot-device.
 380                          */
 381                 };
 382
 383                 i2c0 {
 384                         i2c0_xfer: i2c0-xfer {
 385                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 386                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 387                         };
 388                 };
 389
 390                 i2c1 {
 391                         i2c1_xfer: i2c1-xfer {
 392                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 393                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 394                         };
 395                 };
 396
 397                 i2c2 {
 398                         i2c2_xfer: i2c2-xfer {
 399                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 400                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 401                         };
 402                 };
 403
 404                 i2c3 {
 405                         i2c3_xfer: i2c3-xfer {
 406                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 407                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 408                         };
 409                 };
 410
 411                 i2c4 {
 412                         i2c4_xfer: i2c4-xfer {
 413                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 414                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 415                         };
 416                 };
 417
 418                 pwm0 {
 419                         pwm0_out: pwm0-out {
 420                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 421                         };
 422                 };
 423
 424                 pwm1 {
 425                         pwm1_out: pwm1-out {
 426                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 427                         };
 428                 };
 429
 430                 pwm2 {
 431                         pwm2_out: pwm2-out {
 432                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 433                         };
 434                 };
 435
 436                 pwm3 {
 437                         pwm3_out: pwm3-out {
 438                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 439                         };
 440                 };
 441
 442                 spi0 {
 443                         spi0_clk: spi0-clk {
 444                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 445                         };
 446                         spi0_cs0: spi0-cs0 {
 447                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 448                         };
 449                         spi0_tx: spi0-tx {
 450                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 451                         };
 452                         spi0_rx: spi0-rx {
 453                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 454                         };
 455                         spi0_cs1: spi0-cs1 {
 456                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 457                         };
 458                 };
 459
 460                 spi1 {
 461                         spi1_clk: spi1-clk {
 462                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 463                         };
 464                         spi1_cs0: spi1-cs0 {
 465                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 466                         };
 467                         spi1_rx: spi1-rx {
 468                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 469                         };
 470                         spi1_tx: spi1-tx {
 471                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 472                         };
 473                         spi1_cs1: spi1-cs1 {
 474                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 475                         };
 476                 };
 477
 478                 uart0 {
 479                         uart0_xfer: uart0-xfer {
 480                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 481                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 482                         };
 483
 484                         uart0_cts: uart0-cts {
 485                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 486                         };
 487
 488                         uart0_rts: uart0-rts {
 489                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 490                         };
 491                 };
 492
 493                 uart1 {
 494                         uart1_xfer: uart1-xfer {
 495                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 496                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 497                         };
 498
 499                         uart1_cts: uart1-cts {
 500                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 501                         };
 502
 503                         uart1_rts: uart1-rts {
 504                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 505                         };
 506                 };
 507
 508                 uart2 {
 509                         uart2_xfer: uart2-xfer {
 510                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 511                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 512                         };
 513                         /* no rts / cts for uart2 */
 514                 };
 515
 516                 uart3 {
 517                         uart3_xfer: uart3-xfer {
 518                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 519                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 520                         };
 521
 522                         uart3_cts: uart3-cts {
 523                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 524                         };
 525
 526                         uart3_rts: uart3-rts {
 527                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 528                         };
 529                 };
 530
 531                 sd0 {
 532                         sd0_clk: sd0-clk {
 533                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 534                         };
 535
 536                         sd0_cmd: sd0-cmd {
 537                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 538                         };
 539
 540                         sd0_cd: sd0-cd {
 541                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 542                         };
 543
 544                         sd0_wp: sd0-wp {
 545                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 546                         };
 547
 548                         sd0_bus1: sd0-bus-width1 {
 549                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 550                         };
 551
 552                         sd0_bus4: sd0-bus-width4 {
 553                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 554                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 555                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 556                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 557                         };
 558                 };
 559
 560                 sd1 {
 561                         sd1_clk: sd1-clk {
 562                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 563                         };
 564
 565                         sd1_cmd: sd1-cmd {
 566                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 567                         };
 568
 569                         sd1_cd: sd1-cd {
 570                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 571                         };
 572
 573                         sd1_wp: sd1-wp {
 574                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 575                         };
 576
 577                         sd1_bus1: sd1-bus-width1 {
 578                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 579                         };
 580
 581                         sd1_bus4: sd1-bus-width4 {
 582                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 583                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 584                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 585                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 586                         };
 587                 };
 588
 589                 i2s0 {
 590                         i2s0_bus: i2s0-bus {
 591                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 592                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 593                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 594                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 595                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 596                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 597                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 598                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 599                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 600                         };
 601                 };
 602
 603                 i2s1 {
 604                         i2s1_bus: i2s1-bus {
 605                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 606                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 607                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 608                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 609                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 610                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 611                         };
 612                 };
 613
 614                 i2s2 {
 615                         i2s2_bus: i2s2-bus {
 616                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 617                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 618                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 619                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 620                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 621                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 622                         };
 623                 };
 624         };
 625 };
 626
 627 &gpu {
 628         compatible = "rockchip,rk3066-mali", "arm,mali-400";
 629         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 630                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 631                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 632                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 633                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 634                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 635                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 636                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 637                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 638                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 639         interrupt-names = "gp",
 640                           "gpmmu",
 641                           "pp0",
 642                           "ppmmu0",
 643                           "pp1",
 644                           "ppmmu1",
 645                           "pp2",
 646                           "ppmmu2",
 647                           "pp3",
 648                           "ppmmu3";
 649         power-domains = <&power RK3066_PD_GPU>;
 650 };
 651
 652 &i2c0 {
 653         pinctrl-names = "default";
 654         pinctrl-0 = <&i2c0_xfer>;
 655 };
 656
 657 &i2c1 {
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&i2c1_xfer>;
 660 };
 661
 662 &i2c2 {
 663         pinctrl-names = "default";
 664         pinctrl-0 = <&i2c2_xfer>;
 665 };
 666
 667 &i2c3 {
 668         pinctrl-names = "default";
 669         pinctrl-0 = <&i2c3_xfer>;
 670 };
 671
 672 &i2c4 {
 673         pinctrl-names = "default";
 674         pinctrl-0 = <&i2c4_xfer>;
 675 };
 676
 677 &mmc0 {
 678         clock-frequency = <50000000>;
 679         dmas = <&dmac2 1>;
 680         dma-names = "rx-tx";
 681         max-frequency = <50000000>;
 682         pinctrl-names = "default";
 683         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 684 };
 685
 686 &mmc1 {
 687         dmas = <&dmac2 3>;
 688         dma-names = "rx-tx";
 689         pinctrl-names = "default";
 690         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 691 };
 692
 693 &emmc {
 694         dmas = <&dmac2 4>;
 695         dma-names = "rx-tx";
 696 };
 697
 698 &pmu {
 699         power: power-controller {
 700                 compatible = "rockchip,rk3066-power-controller";
 701                 #power-domain-cells = <1>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704
 705                 pd_vio@RK3066_PD_VIO {
 706                         reg = <RK3066_PD_VIO>;
 707                         clocks = <&cru ACLK_LCDC0>,
 708                                  <&cru ACLK_LCDC1>,
 709                                  <&cru DCLK_LCDC0>,
 710                                  <&cru DCLK_LCDC1>,
 711                                  <&cru HCLK_LCDC0>,
 712                                  <&cru HCLK_LCDC1>,
 713                                  <&cru SCLK_CIF1>,
 714                                  <&cru ACLK_CIF1>,
 715                                  <&cru HCLK_CIF1>,
 716                                  <&cru SCLK_CIF0>,
 717                                  <&cru ACLK_CIF0>,
 718                                  <&cru HCLK_CIF0>,
 719                                  <&cru HCLK_HDMI>,
 720                                  <&cru ACLK_IPP>,
 721                                  <&cru HCLK_IPP>,
 722                                  <&cru ACLK_RGA>,
 723                                  <&cru HCLK_RGA>;
 724                         pm_qos = <&qos_lcdc0>,
 725                                  <&qos_lcdc1>,
 726                                  <&qos_cif0>,
 727                                  <&qos_cif1>,
 728                                  <&qos_ipp>,
 729                                  <&qos_rga>;
 730                 };
 731
 732                 pd_video@RK3066_PD_VIDEO {
 733                         reg = <RK3066_PD_VIDEO>;
 734                         clocks = <&cru ACLK_VDPU>,
 735                                  <&cru ACLK_VEPU>,
 736                                  <&cru HCLK_VDPU>,
 737                                  <&cru HCLK_VEPU>;
 738                         pm_qos = <&qos_vpu>;
 739                 };
 740
 741                 pd_gpu@RK3066_PD_GPU {
 742                         reg = <RK3066_PD_GPU>;
 743                         clocks = <&cru ACLK_GPU>;
 744                         pm_qos = <&qos_gpu>;
 745                 };
 746         };
 747 };
 748
 749 &pwm0 {
 750         pinctrl-names = "default";
 751         pinctrl-0 = <&pwm0_out>;
 752 };
 753
 754 &pwm1 {
 755         pinctrl-names = "default";
 756         pinctrl-0 = <&pwm1_out>;
 757 };
 758
 759 &pwm2 {
 760         pinctrl-names = "default";
 761         pinctrl-0 = <&pwm2_out>;
 762 };
 763
 764 &pwm3 {
 765         pinctrl-names = "default";
 766         pinctrl-0 = <&pwm3_out>;
 767 };
 768
 769 &spi0 {
 770         pinctrl-names = "default";
 771         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 772 };
 773
 774 &spi1 {
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 777 };
 778
 779 &uart0 {
 780         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 781         dmas = <&dmac1_s 0>, <&dmac1_s 1>;
 782         dma-names = "tx", "rx";
 783         pinctrl-names = "default";
 784         pinctrl-0 = <&uart0_xfer>;
 785 };
 786
 787 &uart1 {
 788         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 789         dmas = <&dmac1_s 2>, <&dmac1_s 3>;
 790         dma-names = "tx", "rx";
 791         pinctrl-names = "default";
 792         pinctrl-0 = <&uart1_xfer>;
 793 };
 794
 795 &uart2 {
 796         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 797         dmas = <&dmac2 6>, <&dmac2 7>;
 798         dma-names = "tx", "rx";
 799         pinctrl-names = "default";
 800         pinctrl-0 = <&uart2_xfer>;
 801 };
 802
 803 &uart3 {
 804         compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
 805         dmas = <&dmac2 8>, <&dmac2 9>;
 806         dma-names = "tx", "rx";
 807         pinctrl-names = "default";
 808         pinctrl-0 = <&uart3_xfer>;
 809 };
 810
 811 &wdt {
 812         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 813 };
 814
 815 &emac {
 816         compatible = "rockchip,rk3066-emac";
 817 };