arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include "rk3xxx.dtsi"
  19 #include "rk3066a-clocks.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3066a";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "rockchip,rk3066-smp";
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x1>;
  40                 };
  41         };
  42
  43         soc {
  44                 timer@20038000 {
  45                         compatible = "snps,dw-apb-timer-osc";
  46                         reg = <0x20038000 0x100>;
  47                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&clk_gates1 0>, <&clk_gates7 7>;
  49                         clock-names = "timer", "pclk";
  50                 };
  51
  52                 timer@2003a000 {
  53                         compatible = "snps,dw-apb-timer-osc";
  54                         reg = <0x2003a000 0x100>;
  55                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  56                         clocks = <&clk_gates1 1>, <&clk_gates7 8>;
  57                         clock-names = "timer", "pclk";
  58                 };
  59
  60                 timer@2000e000 {
  61                         compatible = "snps,dw-apb-timer-osc";
  62                         reg = <0x2000e000 0x100>;
  63                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  64                         clocks = <&clk_gates1 2>, <&clk_gates7 9>;
  65                         clock-names = "timer", "pclk";
  66                 };
  67
  68                 sram: sram@10080000 {
  69                         compatible = "mmio-sram";
  70                         reg = <0x10080000 0x10000>;
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         ranges = <0 0x10080000 0x10000>;
  74
  75                         smp-sram@0 {
  76                                 compatible = "rockchip,rk3066-smp-sram";
  77                                 reg = <0x0 0x50>;
  78                         };
  79                 };
  80
  81                 pinctrl@20008000 {
  82                         compatible = "rockchip,rk3066a-pinctrl";
  83                         rockchip,grf = <&grf>;
  84                         #address-cells = <1>;
  85                         #size-cells = <1>;
  86                         ranges;
  87
  88                         gpio0: gpio0@20034000 {
  89                                 compatible = "rockchip,gpio-bank";
  90                                 reg = <0x20034000 0x100>;
  91                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  92                                 clocks = <&clk_gates8 9>;
  93
  94                                 gpio-controller;
  95                                 #gpio-cells = <2>;
  96
  97                                 interrupt-controller;
  98                                 #interrupt-cells = <2>;
  99                         };
 100
 101                         gpio1: gpio1@2003c000 {
 102                                 compatible = "rockchip,gpio-bank";
 103                                 reg = <0x2003c000 0x100>;
 104                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 105                                 clocks = <&clk_gates8 10>;
 106
 107                                 gpio-controller;
 108                                 #gpio-cells = <2>;
 109
 110                                 interrupt-controller;
 111                                 #interrupt-cells = <2>;
 112                         };
 113
 114                         gpio2: gpio2@2003e000 {
 115                                 compatible = "rockchip,gpio-bank";
 116                                 reg = <0x2003e000 0x100>;
 117                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 118                                 clocks = <&clk_gates8 11>;
 119
 120                                 gpio-controller;
 121                                 #gpio-cells = <2>;
 122
 123                                 interrupt-controller;
 124                                 #interrupt-cells = <2>;
 125                         };
 126
 127                         gpio3: gpio3@20080000 {
 128                                 compatible = "rockchip,gpio-bank";
 129                                 reg = <0x20080000 0x100>;
 130                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 131                                 clocks = <&clk_gates8 12>;
 132
 133                                 gpio-controller;
 134                                 #gpio-cells = <2>;
 135
 136                                 interrupt-controller;
 137                                 #interrupt-cells = <2>;
 138                         };
 139
 140                         gpio4: gpio4@20084000 {
 141                                 compatible = "rockchip,gpio-bank";
 142                                 reg = <0x20084000 0x100>;
 143                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 144                                 clocks = <&clk_gates8 13>;
 145
 146                                 gpio-controller;
 147                                 #gpio-cells = <2>;
 148
 149                                 interrupt-controller;
 150                                 #interrupt-cells = <2>;
 151                         };
 152
 153                         gpio6: gpio6@2000a000 {
 154                                 compatible = "rockchip,gpio-bank";
 155                                 reg = <0x2000a000 0x100>;
 156                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 157                                 clocks = <&clk_gates8 15>;
 158
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161
 162                                 interrupt-controller;
 163                                 #interrupt-cells = <2>;
 164                         };
 165
 166                         pcfg_pull_default: pcfg_pull_default {
 167                                 bias-pull-pin-default;
 168                         };
 169
 170                         pcfg_pull_none: pcfg_pull_none {
 171                                 bias-disable;
 172                         };
 173
 174                         uart0 {
 175                                 uart0_xfer: uart0-xfer {
 176                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 177                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 178                                 };
 179
 180                                 uart0_cts: uart0-cts {
 181                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 182                                 };
 183
 184                                 uart0_rts: uart0-rts {
 185                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 186                                 };
 187                         };
 188
 189                         uart1 {
 190                                 uart1_xfer: uart1-xfer {
 191                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 192                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 193                                 };
 194
 195                                 uart1_cts: uart1-cts {
 196                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 197                                 };
 198
 199                                 uart1_rts: uart1-rts {
 200                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 201                                 };
 202                         };
 203
 204                         uart2 {
 205                                 uart2_xfer: uart2-xfer {
 206                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 207                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 208                                 };
 209                                 /* no rts / cts for uart2 */
 210                         };
 211
 212                         uart3 {
 213                                 uart3_xfer: uart3-xfer {
 214                                         rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 215                                                         <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 216                                 };
 217
 218                                 uart3_cts: uart3-cts {
 219                                         rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 220                                 };
 221
 222                                 uart3_rts: uart3-rts {
 223                                         rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 224                                 };
 225                         };
 226
 227                         sd0 {
 228                                 sd0_clk: sd0-clk {
 229                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 230                                 };
 231
 232                                 sd0_cmd: sd0-cmd {
 233                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 234                                 };
 235
 236                                 sd0_cd: sd0-cd {
 237                                         rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 238                                 };
 239
 240                                 sd0_wp: sd0-wp {
 241                                         rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 242                                 };
 243
 244                                 sd0_bus1: sd0-bus-width1 {
 245                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 246                                 };
 247
 248                                 sd0_bus4: sd0-bus-width4 {
 249                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 250                                                         <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 251                                                         <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 252                                                         <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 253                                 };
 254                         };
 255
 256                         sd1 {
 257                                 sd1_clk: sd1-clk {
 258                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 259                                 };
 260
 261                                 sd1_cmd: sd1-cmd {
 262                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 263                                 };
 264
 265                                 sd1_cd: sd1-cd {
 266                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 267                                 };
 268
 269                                 sd1_wp: sd1-wp {
 270                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 271                                 };
 272
 273                                 sd1_bus1: sd1-bus-width1 {
 274                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 275                                 };
 276
 277                                 sd1_bus4: sd1-bus-width4 {
 278                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 279                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 280                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 281                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 282                                 };
 283                         };
 284                 };
 285         };
 286 };